1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/IRBuilder.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Target/TargetCallingConv.h"
38 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class ImmutableCallSite;
50 class MachineBasicBlock;
51 class MachineFunction;
53 class MachineJumpTableInfo;
59 template<typename T> class SmallVectorImpl;
61 class TargetRegisterClass;
62 class TargetLibraryInfo;
63 class TargetLoweringObjectFile;
68 None, // No preference
69 Source, // Follow source order.
70 RegPressure, // Scheduling for lowest register pressure.
71 Hybrid, // Scheduling for both latency and register pressure.
72 ILP, // Scheduling for ILP in low register pressure mode.
73 VLIW // Scheduling for VLIW targets.
77 /// This base class for TargetLowering contains the SelectionDAG-independent
78 /// parts that can be used from the rest of CodeGen.
79 class TargetLoweringBase {
80 TargetLoweringBase(const TargetLoweringBase&) = delete;
81 void operator=(const TargetLoweringBase&) = delete;
84 /// This enum indicates whether operations are valid for a target, and if not,
85 /// what action should be used to make them valid.
87 Legal, // The target natively supports this operation.
88 Promote, // This operation should be executed in a larger type.
89 Expand, // Try to expand this to other ops, otherwise use a libcall.
90 Custom // Use the LowerOperation hook to implement custom lowering.
93 /// This enum indicates whether a types are legal for a target, and if not,
94 /// what action should be used to make them valid.
95 enum LegalizeTypeAction {
96 TypeLegal, // The target natively supports this type.
97 TypePromoteInteger, // Replace this integer with a larger one.
98 TypeExpandInteger, // Split this integer into two of half the size.
99 TypeSoftenFloat, // Convert this float to a same size integer type.
100 TypeExpandFloat, // Split this float into two of half the size.
101 TypeScalarizeVector, // Replace this one-element vector with its element.
102 TypeSplitVector, // Split this vector into two of half the size.
103 TypeWidenVector, // This vector should be widened into a larger vector.
104 TypePromoteFloat // Replace this float with a larger one.
107 /// LegalizeKind holds the legalization kind that needs to happen to EVT
108 /// in order to type-legalize it.
109 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
111 /// Enum that describes how the target represents true/false values.
112 enum BooleanContent {
113 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
114 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
115 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
118 /// Enum that describes what type of support for selects the target has.
119 enum SelectSupportKind {
120 ScalarValSelect, // The target supports scalar selects (ex: cmov).
121 ScalarCondVectorVal, // The target supports selects with a scalar condition
122 // and vector values (ex: cmov).
123 VectorMaskSelect // The target supports vector selects with a vector
124 // mask (ex: x86 blends).
127 /// Enum that specifies what a AtomicRMWInst is expanded to, if at all. Exists
128 /// because different targets have different levels of support for these
129 /// atomic RMW instructions, and also have different options w.r.t. what they should
131 enum class AtomicRMWExpansionKind {
132 None, // Don't expand the instruction.
133 LLSC, // Expand the instruction into loadlinked/storeconditional; used
134 // by ARM/AArch64. Implies `hasLoadLinkedStoreConditional`
136 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
139 static ISD::NodeType getExtendForContent(BooleanContent Content) {
141 case UndefinedBooleanContent:
142 // Extend by adding rubbish bits.
143 return ISD::ANY_EXTEND;
144 case ZeroOrOneBooleanContent:
145 // Extend by adding zero bits.
146 return ISD::ZERO_EXTEND;
147 case ZeroOrNegativeOneBooleanContent:
148 // Extend by copying the sign bit.
149 return ISD::SIGN_EXTEND;
151 llvm_unreachable("Invalid content kind");
154 /// NOTE: The TargetMachine owns TLOF.
155 explicit TargetLoweringBase(const TargetMachine &TM);
156 virtual ~TargetLoweringBase() {}
159 /// \brief Initialize all of the actions to default values.
163 const TargetMachine &getTargetMachine() const { return TM; }
164 const DataLayout *getDataLayout() const { return TM.getDataLayout(); }
166 bool isBigEndian() const { return !IsLittleEndian; }
167 bool isLittleEndian() const { return IsLittleEndian; }
168 virtual bool useSoftFloat() const { return false; }
170 /// Return the pointer type for the given address space, defaults to
171 /// the pointer type from the data layout.
172 /// FIXME: The default needs to be removed once all the code is updated.
173 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
174 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
175 unsigned getPointerTypeSizeInBits(Type *Ty) const;
176 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
178 EVT getShiftAmountTy(EVT LHSTy) const;
180 /// Returns the type to be used for the index operand of:
181 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
182 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
183 virtual MVT getVectorIdxTy() const {
184 return getPointerTy();
187 /// Return true if the select operation is expensive for this target.
188 bool isSelectExpensive() const { return SelectIsExpensive; }
190 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
194 /// Return true if multiple condition registers are available.
195 bool hasMultipleConditionRegisters() const {
196 return HasMultipleConditionRegisters;
199 /// Return true if the target has BitExtract instructions.
200 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
202 /// Return the preferred vector type legalization action.
203 virtual TargetLoweringBase::LegalizeTypeAction
204 getPreferredVectorAction(EVT VT) const {
205 // The default action for one element vectors is to scalarize
206 if (VT.getVectorNumElements() == 1)
207 return TypeScalarizeVector;
208 // The default action for other vectors is to promote
209 return TypePromoteInteger;
212 // There are two general methods for expanding a BUILD_VECTOR node:
213 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
215 // 2. Build the vector on the stack and then load it.
216 // If this function returns true, then method (1) will be used, subject to
217 // the constraint that all of the necessary shuffles are legal (as determined
218 // by isShuffleMaskLegal). If this function returns false, then method (2) is
219 // always used. The vector type, and the number of defined values, are
222 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
223 unsigned DefinedValues) const {
224 return DefinedValues < 3;
227 /// Return true if integer divide is usually cheaper than a sequence of
228 /// several shifts, adds, and multiplies for this target.
229 bool isIntDivCheap() const { return IntDivIsCheap; }
231 /// Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x)
232 bool isFsqrtCheap() const {
236 /// Returns true if target has indicated at least one type should be bypassed.
237 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
239 /// Returns map of slow types for division or remainder with corresponding
241 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
242 return BypassSlowDivWidths;
245 /// Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra.
246 bool isPow2SDivCheap() const { return Pow2SDivIsCheap; }
248 /// Return true if Flow Control is an expensive operation that should be
250 bool isJumpExpensive() const { return JumpIsExpensive; }
252 /// Return true if selects are only cheaper than branches if the branch is
253 /// unlikely to be predicted right.
254 bool isPredictableSelectExpensive() const {
255 return PredictableSelectIsExpensive;
258 /// isLoadBitCastBeneficial() - Return true if the following transform
260 /// fold (conv (load x)) -> (load (conv*)x)
261 /// On architectures that don't natively support some vector loads efficiently,
262 /// casting the load to a smaller vector of larger types and loading
263 /// is more efficient, however, this can be undone by optimizations in
265 virtual bool isLoadBitCastBeneficial(EVT /* Load */, EVT /* Bitcast */) const {
269 /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
270 virtual bool isCheapToSpeculateCttz() const {
274 /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
275 virtual bool isCheapToSpeculateCtlz() const {
279 /// \brief Return if the target supports combining a
282 /// %andResult = and %val1, #imm-with-one-bit-set;
283 /// %icmpResult = icmp %andResult, 0
284 /// br i1 %icmpResult, label %dest1, label %dest2
286 /// into a single machine instruction of a form like:
288 /// brOnBitSet %register, #bitNumber, dest
290 bool isMaskAndBranchFoldingLegal() const {
291 return MaskAndBranchFoldingIsLegal;
294 /// \brief Return true if the target wants to use the optimization that
295 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
296 /// promotedInst1(...(promotedInstN(ext(load)))).
297 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
299 /// Return true if the target can combine store(extractelement VectorTy,
301 /// \p Cost[out] gives the cost of that transformation when this is true.
302 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
303 unsigned &Cost) const {
307 /// Return true if target supports floating point exceptions.
308 bool hasFloatingPointExceptions() const {
309 return HasFloatingPointExceptions;
312 /// Return true if target always beneficiates from combining into FMA for a
313 /// given value type. This must typically return false on targets where FMA
314 /// takes more cycles to execute than FADD.
315 virtual bool enableAggressiveFMAFusion(EVT VT) const {
319 /// Return the ValueType of the result of SETCC operations.
320 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
322 /// Return the ValueType for comparison libcalls. Comparions libcalls include
323 /// floating point comparion calls, and Ordered/Unordered check calls on
324 /// floating point numbers.
326 MVT::SimpleValueType getCmpLibcallReturnType() const;
328 /// For targets without i1 registers, this gives the nature of the high-bits
329 /// of boolean values held in types wider than i1.
331 /// "Boolean values" are special true/false values produced by nodes like
332 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
333 /// Not to be confused with general values promoted from i1. Some cpus
334 /// distinguish between vectors of boolean and scalars; the isVec parameter
335 /// selects between the two kinds. For example on X86 a scalar boolean should
336 /// be zero extended from i1, while the elements of a vector of booleans
337 /// should be sign extended from i1.
339 /// Some cpus also treat floating point types the same way as they treat
340 /// vectors instead of the way they treat scalars.
341 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
343 return BooleanVectorContents;
344 return isFloat ? BooleanFloatContents : BooleanContents;
347 BooleanContent getBooleanContents(EVT Type) const {
348 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
351 /// Return target scheduling preference.
352 Sched::Preference getSchedulingPreference() const {
353 return SchedPreferenceInfo;
356 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
357 /// for different nodes. This function returns the preference (or none) for
359 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
363 /// Return the register class that should be used for the specified value
365 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
366 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
367 assert(RC && "This value type is not natively supported!");
371 /// Return the 'representative' register class for the specified value
374 /// The 'representative' register class is the largest legal super-reg
375 /// register class for the register class of the value type. For example, on
376 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
377 /// register class is GR64 on x86_64.
378 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
379 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
383 /// Return the cost of the 'representative' register class for the specified
385 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
386 return RepRegClassCostForVT[VT.SimpleTy];
389 /// Return true if the target has native support for the specified value type.
390 /// This means that it has a register that directly holds it without
391 /// promotions or expansions.
392 bool isTypeLegal(EVT VT) const {
393 assert(!VT.isSimple() ||
394 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
395 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
398 class ValueTypeActionImpl {
399 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
400 /// that indicates how instruction selection should deal with the type.
401 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
404 ValueTypeActionImpl() {
405 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
408 LegalizeTypeAction getTypeAction(MVT VT) const {
409 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
412 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
413 unsigned I = VT.SimpleTy;
414 ValueTypeActions[I] = Action;
418 const ValueTypeActionImpl &getValueTypeActions() const {
419 return ValueTypeActions;
422 /// Return how we should legalize values of this type, either it is already
423 /// legal (return 'Legal') or we need to promote it to a larger type (return
424 /// 'Promote'), or we need to expand it into multiple registers of smaller
425 /// integer type (return 'Expand'). 'Custom' is not an option.
426 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
427 return getTypeConversion(Context, VT).first;
429 LegalizeTypeAction getTypeAction(MVT VT) const {
430 return ValueTypeActions.getTypeAction(VT);
433 /// For types supported by the target, this is an identity function. For
434 /// types that must be promoted to larger types, this returns the larger type
435 /// to promote to. For integer types that are larger than the largest integer
436 /// register, this contains one step in the expansion to get to the smaller
437 /// register. For illegal floating point types, this returns the integer type
439 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
440 return getTypeConversion(Context, VT).second;
443 /// For types supported by the target, this is an identity function. For
444 /// types that must be expanded (i.e. integer types that are larger than the
445 /// largest integer register or illegal floating point types), this returns
446 /// the largest legal type it will be expanded to.
447 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
448 assert(!VT.isVector());
450 switch (getTypeAction(Context, VT)) {
453 case TypeExpandInteger:
454 VT = getTypeToTransformTo(Context, VT);
457 llvm_unreachable("Type is not legal nor is it to be expanded!");
462 /// Vector types are broken down into some number of legal first class types.
463 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
464 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
465 /// turns into 4 EVT::i32 values with both PPC and X86.
467 /// This method returns the number of registers needed, and the VT for each
468 /// register. It also returns the VT and quantity of the intermediate values
469 /// before they are promoted/expanded.
470 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
472 unsigned &NumIntermediates,
473 MVT &RegisterVT) const;
475 struct IntrinsicInfo {
476 unsigned opc; // target opcode
477 EVT memVT; // memory VT
478 const Value* ptrVal; // value representing memory location
479 int offset; // offset off of ptrVal
480 unsigned size; // the size of the memory location
481 // (taken from memVT if zero)
482 unsigned align; // alignment
483 bool vol; // is volatile?
484 bool readMem; // reads memory?
485 bool writeMem; // writes memory?
487 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
488 vol(false), readMem(false), writeMem(false) {}
491 /// Given an intrinsic, checks if on the target the intrinsic will need to map
492 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
493 /// true and store the intrinsic information into the IntrinsicInfo that was
494 /// passed to the function.
495 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
496 unsigned /*Intrinsic*/) const {
500 /// Returns true if the target can instruction select the specified FP
501 /// immediate natively. If false, the legalizer will materialize the FP
502 /// immediate as a load from a constant pool.
503 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
507 /// Targets can use this to indicate that they only support *some*
508 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
509 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
511 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
516 /// Returns true if the operation can trap for the value type.
518 /// VT must be a legal type. By default, we optimistically assume most
519 /// operations don't trap except for divide and remainder.
520 virtual bool canOpTrap(unsigned Op, EVT VT) const;
522 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
523 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
524 /// a VAND with a constant pool entry.
525 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
530 /// Return how this operation should be treated: either it is legal, needs to
531 /// be promoted to a larger size, needs to be expanded to some other code
532 /// sequence, or the target has a custom expander for it.
533 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
534 if (VT.isExtended()) return Expand;
535 // If a target-specific SDNode requires legalization, require the target
536 // to provide custom legalization for it.
537 if (Op > array_lengthof(OpActions[0])) return Custom;
538 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
539 return (LegalizeAction)OpActions[I][Op];
542 /// Return true if the specified operation is legal on this target or can be
543 /// made legal with custom lowering. This is used to help guide high-level
544 /// lowering decisions.
545 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
546 return (VT == MVT::Other || isTypeLegal(VT)) &&
547 (getOperationAction(Op, VT) == Legal ||
548 getOperationAction(Op, VT) == Custom);
551 /// Return true if the specified operation is legal on this target or can be
552 /// made legal using promotion. This is used to help guide high-level lowering
554 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
555 return (VT == MVT::Other || isTypeLegal(VT)) &&
556 (getOperationAction(Op, VT) == Legal ||
557 getOperationAction(Op, VT) == Promote);
560 /// Return true if the specified operation is illegal on this target or
561 /// unlikely to be made legal with custom lowering. This is used to help guide
562 /// high-level lowering decisions.
563 bool isOperationExpand(unsigned Op, EVT VT) const {
564 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
567 /// Return true if the specified operation is legal on this target.
568 bool isOperationLegal(unsigned Op, EVT VT) const {
569 return (VT == MVT::Other || isTypeLegal(VT)) &&
570 getOperationAction(Op, VT) == Legal;
573 /// Return how this load with extension should be treated: either it is legal,
574 /// needs to be promoted to a larger size, needs to be expanded to some other
575 /// code sequence, or the target has a custom expander for it.
576 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT, EVT MemVT) const {
577 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
578 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
579 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
580 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
581 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
582 return (LegalizeAction)LoadExtActions[ValI][MemI][ExtType];
585 /// Return true if the specified load with extension is legal on this target.
586 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
587 return ValVT.isSimple() && MemVT.isSimple() &&
588 getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
591 /// Return true if the specified load with extension is legal or custom
593 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
594 return ValVT.isSimple() && MemVT.isSimple() &&
595 (getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
596 getLoadExtAction(ExtType, ValVT, MemVT) == Custom);
599 /// Return how this store with truncation should be treated: either it is
600 /// legal, needs to be promoted to a larger size, needs to be expanded to some
601 /// other code sequence, or the target has a custom expander for it.
602 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
603 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
604 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
605 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
606 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
607 "Table isn't big enough!");
608 return (LegalizeAction)TruncStoreActions[ValI][MemI];
611 /// Return true if the specified store with truncation is legal on this
613 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
614 return isTypeLegal(ValVT) && MemVT.isSimple() &&
615 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
618 /// Return how the indexed load should be treated: either it is legal, needs
619 /// to be promoted to a larger size, needs to be expanded to some other code
620 /// sequence, or the target has a custom expander for it.
622 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
623 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
624 "Table isn't big enough!");
625 unsigned Ty = (unsigned)VT.SimpleTy;
626 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
629 /// Return true if the specified indexed load is legal on this target.
630 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
631 return VT.isSimple() &&
632 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
633 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
636 /// Return how the indexed store should be treated: either it is legal, needs
637 /// to be promoted to a larger size, needs to be expanded to some other code
638 /// sequence, or the target has a custom expander for it.
640 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
641 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
642 "Table isn't big enough!");
643 unsigned Ty = (unsigned)VT.SimpleTy;
644 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
647 /// Return true if the specified indexed load is legal on this target.
648 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
649 return VT.isSimple() &&
650 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
651 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
654 /// Return how the condition code should be treated: either it is legal, needs
655 /// to be expanded to some other code sequence, or the target has a custom
658 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
659 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
660 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
661 "Table isn't big enough!");
662 // See setCondCodeAction for how this is encoded.
663 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
664 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
665 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
666 assert(Action != Promote && "Can't promote condition code!");
670 /// Return true if the specified condition code is legal on this target.
671 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
673 getCondCodeAction(CC, VT) == Legal ||
674 getCondCodeAction(CC, VT) == Custom;
678 /// If the action for this operation is to promote, this method returns the
679 /// ValueType to promote to.
680 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
681 assert(getOperationAction(Op, VT) == Promote &&
682 "This operation isn't promoted!");
684 // See if this has an explicit type specified.
685 std::map<std::pair<unsigned, MVT::SimpleValueType>,
686 MVT::SimpleValueType>::const_iterator PTTI =
687 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
688 if (PTTI != PromoteToType.end()) return PTTI->second;
690 assert((VT.isInteger() || VT.isFloatingPoint()) &&
691 "Cannot autopromote this type, add it with AddPromotedToType.");
695 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
696 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
697 "Didn't find type to promote to!");
698 } while (!isTypeLegal(NVT) ||
699 getOperationAction(Op, NVT) == Promote);
703 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
704 /// operations except for the pointer size. If AllowUnknown is true, this
705 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
706 /// otherwise it will assert.
707 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
708 // Lower scalar pointers to native pointer types.
709 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
710 return getPointerTy(PTy->getAddressSpace());
712 if (Ty->isVectorTy()) {
713 VectorType *VTy = cast<VectorType>(Ty);
714 Type *Elm = VTy->getElementType();
715 // Lower vectors of pointers to native pointer types.
716 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
717 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
718 Elm = PointerTy.getTypeForEVT(Ty->getContext());
721 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
722 VTy->getNumElements());
724 return EVT::getEVT(Ty, AllowUnknown);
727 /// Return the MVT corresponding to this LLVM type. See getValueType.
728 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
729 return getValueType(Ty, AllowUnknown).getSimpleVT();
732 /// Return the desired alignment for ByVal or InAlloca aggregate function
733 /// arguments in the caller parameter area. This is the actual alignment, not
735 virtual unsigned getByValTypeAlignment(Type *Ty) const;
737 /// Return the type of registers that this ValueType will eventually require.
738 MVT getRegisterType(MVT VT) const {
739 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
740 return RegisterTypeForVT[VT.SimpleTy];
743 /// Return the type of registers that this ValueType will eventually require.
744 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
746 assert((unsigned)VT.getSimpleVT().SimpleTy <
747 array_lengthof(RegisterTypeForVT));
748 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
753 unsigned NumIntermediates;
754 (void)getVectorTypeBreakdown(Context, VT, VT1,
755 NumIntermediates, RegisterVT);
758 if (VT.isInteger()) {
759 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
761 llvm_unreachable("Unsupported extended type!");
764 /// Return the number of registers that this ValueType will eventually
767 /// This is one for any types promoted to live in larger registers, but may be
768 /// more than one for types (like i64) that are split into pieces. For types
769 /// like i140, which are first promoted then expanded, it is the number of
770 /// registers needed to hold all the bits of the original type. For an i140
771 /// on a 32 bit machine this means 5 registers.
772 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
774 assert((unsigned)VT.getSimpleVT().SimpleTy <
775 array_lengthof(NumRegistersForVT));
776 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
781 unsigned NumIntermediates;
782 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
784 if (VT.isInteger()) {
785 unsigned BitWidth = VT.getSizeInBits();
786 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
787 return (BitWidth + RegWidth - 1) / RegWidth;
789 llvm_unreachable("Unsupported extended type!");
792 /// If true, then instruction selection should seek to shrink the FP constant
793 /// of the specified type to a smaller type in order to save space and / or
795 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
797 // Return true if it is profitable to reduce the given load node to a smaller
800 // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
801 virtual bool shouldReduceLoadWidth(SDNode *Load,
802 ISD::LoadExtType ExtTy,
807 /// When splitting a value of the specified type into parts, does the Lo
808 /// or Hi part come first? This usually follows the endianness, except
809 /// for ppcf128, where the Hi part always comes first.
810 bool hasBigEndianPartOrdering(EVT VT) const {
811 return isBigEndian() || VT == MVT::ppcf128;
814 /// If true, the target has custom DAG combine transformations that it can
815 /// perform for the specified node.
816 bool hasTargetDAGCombine(ISD::NodeType NT) const {
817 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
818 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
821 /// \brief Get maximum # of store operations permitted for llvm.memset
823 /// This function returns the maximum number of store operations permitted
824 /// to replace a call to llvm.memset. The value is set by the target at the
825 /// performance threshold for such a replacement. If OptSize is true,
826 /// return the limit for functions that have OptSize attribute.
827 unsigned getMaxStoresPerMemset(bool OptSize) const {
828 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
831 /// \brief Get maximum # of store operations permitted for llvm.memcpy
833 /// This function returns the maximum number of store operations permitted
834 /// to replace a call to llvm.memcpy. The value is set by the target at the
835 /// performance threshold for such a replacement. If OptSize is true,
836 /// return the limit for functions that have OptSize attribute.
837 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
838 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
841 /// \brief Get maximum # of store operations permitted for llvm.memmove
843 /// This function returns the maximum number of store operations permitted
844 /// to replace a call to llvm.memmove. The value is set by the target at the
845 /// performance threshold for such a replacement. If OptSize is true,
846 /// return the limit for functions that have OptSize attribute.
847 unsigned getMaxStoresPerMemmove(bool OptSize) const {
848 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
851 /// \brief Determine if the target supports unaligned memory accesses.
853 /// This function returns true if the target allows unaligned memory accesses
854 /// of the specified type in the given address space. If true, it also returns
855 /// whether the unaligned memory access is "fast" in the last argument by
856 /// reference. This is used, for example, in situations where an array
857 /// copy/move/set is converted to a sequence of store operations. Its use
858 /// helps to ensure that such replacements don't generate code that causes an
859 /// alignment error (trap) on the target machine.
860 virtual bool allowsMisalignedMemoryAccesses(EVT,
861 unsigned AddrSpace = 0,
863 bool * /*Fast*/ = nullptr) const {
867 /// Returns the target specific optimal type for load and store operations as
868 /// a result of memset, memcpy, and memmove lowering.
870 /// If DstAlign is zero that means it's safe to destination alignment can
871 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
872 /// a need to check it against alignment requirement, probably because the
873 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
874 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
875 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
876 /// does not need to be loaded. It returns EVT::Other if the type should be
877 /// determined using generic target-independent logic.
878 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
879 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
882 bool /*MemcpyStrSrc*/,
883 MachineFunction &/*MF*/) const {
887 /// Returns true if it's safe to use load / store of the specified type to
888 /// expand memcpy / memset inline.
890 /// This is mostly true for all types except for some special cases. For
891 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
892 /// fstpl which also does type conversion. Note the specified type doesn't
893 /// have to be legal as the hook is used before type legalization.
894 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
896 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
897 bool usesUnderscoreSetJmp() const {
898 return UseUnderscoreSetJmp;
901 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
902 bool usesUnderscoreLongJmp() const {
903 return UseUnderscoreLongJmp;
906 /// Return integer threshold on number of blocks to use jump tables rather
907 /// than if sequence.
908 int getMinimumJumpTableEntries() const {
909 return MinimumJumpTableEntries;
912 /// If a physical register, this specifies the register that
913 /// llvm.savestack/llvm.restorestack should save and restore.
914 unsigned getStackPointerRegisterToSaveRestore() const {
915 return StackPointerRegisterToSaveRestore;
918 /// If a physical register, this returns the register that receives the
919 /// exception address on entry to a landing pad.
920 unsigned getExceptionPointerRegister() const {
921 return ExceptionPointerRegister;
924 /// If a physical register, this returns the register that receives the
925 /// exception typeid on entry to a landing pad.
926 unsigned getExceptionSelectorRegister() const {
927 return ExceptionSelectorRegister;
930 /// Returns the target's jmp_buf size in bytes (if never set, the default is
932 unsigned getJumpBufSize() const {
936 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
938 unsigned getJumpBufAlignment() const {
939 return JumpBufAlignment;
942 /// Return the minimum stack alignment of an argument.
943 unsigned getMinStackArgumentAlignment() const {
944 return MinStackArgumentAlignment;
947 /// Return the minimum function alignment.
948 unsigned getMinFunctionAlignment() const {
949 return MinFunctionAlignment;
952 /// Return the preferred function alignment.
953 unsigned getPrefFunctionAlignment() const {
954 return PrefFunctionAlignment;
957 /// Return the preferred loop alignment.
958 virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
959 return PrefLoopAlignment;
962 /// Return whether the DAG builder should automatically insert fences and
963 /// reduce ordering for atomics.
964 bool getInsertFencesForAtomic() const {
965 return InsertFencesForAtomic;
968 /// Return true if the target stores stack protector cookies at a fixed offset
969 /// in some non-standard address space, and populates the address space and
970 /// offset as appropriate.
971 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
972 unsigned &/*Offset*/) const {
976 /// Returns true if a cast between SrcAS and DestAS is a noop.
977 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
981 /// Return true if the pointer arguments to CI should be aligned by aligning
982 /// the object whose address is being passed. If so then MinSize is set to the
983 /// minimum size the object must be to be aligned and PrefAlign is set to the
984 /// preferred alignment.
985 virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
986 unsigned & /*PrefAlign*/) const {
990 //===--------------------------------------------------------------------===//
991 /// \name Helpers for TargetTransformInfo implementations
994 /// Get the ISD node that corresponds to the Instruction class opcode.
995 int InstructionOpcodeToISD(unsigned Opcode) const;
997 /// Estimate the cost of type-legalization and the legalized type.
998 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
1002 //===--------------------------------------------------------------------===//
1003 /// \name Helpers for atomic expansion.
1006 /// True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional
1007 /// and expand AtomicCmpXchgInst.
1008 virtual bool hasLoadLinkedStoreConditional() const { return false; }
1010 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1011 /// corresponding pointee type. This may entail some non-trivial operations to
1012 /// truncate or reconstruct types that will be illegal in the backend. See
1013 /// ARMISelLowering for an example implementation.
1014 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1015 AtomicOrdering Ord) const {
1016 llvm_unreachable("Load linked unimplemented on this target");
1019 /// Perform a store-conditional operation to Addr. Return the status of the
1020 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1021 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1022 Value *Addr, AtomicOrdering Ord) const {
1023 llvm_unreachable("Store conditional unimplemented on this target");
1026 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1027 /// It is called by AtomicExpandPass before expanding an
1028 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
1029 /// RMW and CmpXchg set both IsStore and IsLoad to true.
1030 /// This function should either return a nullptr, or a pointer to an IR-level
1031 /// Instruction*. Even complex fence sequences can be represented by a
1032 /// single Instruction* through an intrinsic to be lowered later.
1033 /// Backends with !getInsertFencesForAtomic() should keep a no-op here.
1034 /// Backends should override this method to produce target-specific intrinsic
1035 /// for their fences.
1036 /// FIXME: Please note that the default implementation here in terms of
1037 /// IR-level fences exists for historical/compatibility reasons and is
1038 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1039 /// consistency. For example, consider the following example:
1040 /// atomic<int> x = y = 0;
1041 /// int r1, r2, r3, r4;
1052 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1053 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1054 /// IR-level fences can prevent it.
1056 virtual Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
1057 bool IsStore, bool IsLoad) const {
1058 if (!getInsertFencesForAtomic())
1061 if (isAtLeastRelease(Ord) && IsStore)
1062 return Builder.CreateFence(Ord);
1067 virtual Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
1068 bool IsStore, bool IsLoad) const {
1069 if (!getInsertFencesForAtomic())
1072 if (isAtLeastAcquire(Ord))
1073 return Builder.CreateFence(Ord);
1079 /// Returns true if the given (atomic) store should be expanded by the
1080 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1081 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1085 /// Returns true if arguments should be sign-extended in lib calls.
1086 virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1090 /// Returns true if the given (atomic) load should be expanded by the
1091 /// IR-level AtomicExpand pass into a load-linked instruction
1092 /// (through emitLoadLinked()).
1093 virtual bool shouldExpandAtomicLoadInIR(LoadInst *LI) const { return false; }
1095 /// Returns how the IR-level AtomicExpand pass should expand the given
1096 /// AtomicRMW, if at all. Default is to never expand.
1097 virtual AtomicRMWExpansionKind
1098 shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1099 return AtomicRMWExpansionKind::None;
1102 /// On some platforms, an AtomicRMW that never actually modifies the value
1103 /// (such as fetch_add of 0) can be turned into a fence followed by an
1104 /// atomic load. This may sound useless, but it makes it possible for the
1105 /// processor to keep the cacheline shared, dramatically improving
1106 /// performance. And such idempotent RMWs are useful for implementing some
1107 /// kinds of locks, see for example (justification + benchmarks):
1108 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1109 /// This method tries doing that transformation, returning the atomic load if
1110 /// it succeeds, and nullptr otherwise.
1111 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1112 /// another round of expansion.
1113 virtual LoadInst *lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1117 /// Returns true if we should normalize
1118 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1119 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1120 /// that it saves us from materializing N0 and N1 in an integer register.
1121 /// Targets that are able to perform and/or on flags should return false here.
1122 virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1124 // If a target has multiple condition registers, then it likely has logical
1125 // operations on those registers.
1126 if (hasMultipleConditionRegisters())
1128 // Only do the transform if the value won't be split into multiple
1130 LegalizeTypeAction Action = getTypeAction(Context, VT);
1131 return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1132 Action != TypeSplitVector;
1135 //===--------------------------------------------------------------------===//
1136 // TargetLowering Configuration Methods - These methods should be invoked by
1137 // the derived class constructor to configure this object for the target.
1140 /// Specify how the target extends the result of integer and floating point
1141 /// boolean values from i1 to a wider type. See getBooleanContents.
1142 void setBooleanContents(BooleanContent Ty) {
1143 BooleanContents = Ty;
1144 BooleanFloatContents = Ty;
1147 /// Specify how the target extends the result of integer and floating point
1148 /// boolean values from i1 to a wider type. See getBooleanContents.
1149 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1150 BooleanContents = IntTy;
1151 BooleanFloatContents = FloatTy;
1154 /// Specify how the target extends the result of a vector boolean value from a
1155 /// vector of i1 to a wider type. See getBooleanContents.
1156 void setBooleanVectorContents(BooleanContent Ty) {
1157 BooleanVectorContents = Ty;
1160 /// Specify the target scheduling preference.
1161 void setSchedulingPreference(Sched::Preference Pref) {
1162 SchedPreferenceInfo = Pref;
1165 /// Indicate whether this target prefers to use _setjmp to implement
1166 /// llvm.setjmp or the version without _. Defaults to false.
1167 void setUseUnderscoreSetJmp(bool Val) {
1168 UseUnderscoreSetJmp = Val;
1171 /// Indicate whether this target prefers to use _longjmp to implement
1172 /// llvm.longjmp or the version without _. Defaults to false.
1173 void setUseUnderscoreLongJmp(bool Val) {
1174 UseUnderscoreLongJmp = Val;
1177 /// Indicate the number of blocks to generate jump tables rather than if
1179 void setMinimumJumpTableEntries(int Val) {
1180 MinimumJumpTableEntries = Val;
1183 /// If set to a physical register, this specifies the register that
1184 /// llvm.savestack/llvm.restorestack should save and restore.
1185 void setStackPointerRegisterToSaveRestore(unsigned R) {
1186 StackPointerRegisterToSaveRestore = R;
1189 /// If set to a physical register, this sets the register that receives the
1190 /// exception address on entry to a landing pad.
1191 void setExceptionPointerRegister(unsigned R) {
1192 ExceptionPointerRegister = R;
1195 /// If set to a physical register, this sets the register that receives the
1196 /// exception typeid on entry to a landing pad.
1197 void setExceptionSelectorRegister(unsigned R) {
1198 ExceptionSelectorRegister = R;
1201 /// Tells the code generator not to expand operations into sequences that use
1202 /// the select operations if possible.
1203 void setSelectIsExpensive(bool isExpensive = true) {
1204 SelectIsExpensive = isExpensive;
1207 /// Tells the code generator that the target has multiple (allocatable)
1208 /// condition registers that can be used to store the results of comparisons
1209 /// for use by selects and conditional branches. With multiple condition
1210 /// registers, the code generator will not aggressively sink comparisons into
1211 /// the blocks of their users.
1212 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1213 HasMultipleConditionRegisters = hasManyRegs;
1216 /// Tells the code generator that the target has BitExtract instructions.
1217 /// The code generator will aggressively sink "shift"s into the blocks of
1218 /// their users if the users will generate "and" instructions which can be
1219 /// combined with "shift" to BitExtract instructions.
1220 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1221 HasExtractBitsInsn = hasExtractInsn;
1224 /// Tells the code generator not to expand sequence of operations into a
1225 /// separate sequences that increases the amount of flow control.
1226 void setJumpIsExpensive(bool isExpensive = true) {
1227 JumpIsExpensive = isExpensive;
1230 /// Tells the code generator that integer divide is expensive, and if
1231 /// possible, should be replaced by an alternate sequence of instructions not
1232 /// containing an integer divide.
1233 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1235 /// Tells the code generator that fsqrt is cheap, and should not be replaced
1236 /// with an alternative sequence of instructions.
1237 void setFsqrtIsCheap(bool isCheap = true) { FsqrtIsCheap = isCheap; }
1239 /// Tells the code generator that this target supports floating point
1240 /// exceptions and cares about preserving floating point exception behavior.
1241 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1242 HasFloatingPointExceptions = FPExceptions;
1245 /// Tells the code generator which bitwidths to bypass.
1246 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1247 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1250 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1251 /// signed divide by power of two; let the target handle it.
1252 void setPow2SDivIsCheap(bool isCheap = true) { Pow2SDivIsCheap = isCheap; }
1254 /// Add the specified register class as an available regclass for the
1255 /// specified value type. This indicates the selector can handle values of
1256 /// that class natively.
1257 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1258 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1259 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1260 RegClassForVT[VT.SimpleTy] = RC;
1263 /// Remove all register classes.
1264 void clearRegisterClasses() {
1265 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1267 AvailableRegClasses.clear();
1270 /// \brief Remove all operation actions.
1271 void clearOperationActions() {
1274 /// Return the largest legal super-reg register class of the register class
1275 /// for the specified type and its associated "cost".
1276 virtual std::pair<const TargetRegisterClass *, uint8_t>
1277 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1279 /// Once all of the register classes are added, this allows us to compute
1280 /// derived properties we expose.
1281 void computeRegisterProperties(const TargetRegisterInfo *TRI);
1283 /// Indicate that the specified operation does not work with the specified
1284 /// type and indicate what to do about it.
1285 void setOperationAction(unsigned Op, MVT VT,
1286 LegalizeAction Action) {
1287 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1288 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1291 /// Indicate that the specified load with extension does not work with the
1292 /// specified type and indicate what to do about it.
1293 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1294 LegalizeAction Action) {
1295 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1296 MemVT.isValid() && "Table isn't big enough!");
1297 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy][ExtType] = (uint8_t)Action;
1300 /// Indicate that the specified truncating store does not work with the
1301 /// specified type and indicate what to do about it.
1302 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1303 LegalizeAction Action) {
1304 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1305 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1308 /// Indicate that the specified indexed load does or does not work with the
1309 /// specified type and indicate what to do abort it.
1311 /// NOTE: All indexed mode loads are initialized to Expand in
1312 /// TargetLowering.cpp
1313 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1314 LegalizeAction Action) {
1315 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1316 (unsigned)Action < 0xf && "Table isn't big enough!");
1317 // Load action are kept in the upper half.
1318 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1319 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1322 /// Indicate that the specified indexed store does or does not work with the
1323 /// specified type and indicate what to do about it.
1325 /// NOTE: All indexed mode stores are initialized to Expand in
1326 /// TargetLowering.cpp
1327 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1328 LegalizeAction Action) {
1329 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1330 (unsigned)Action < 0xf && "Table isn't big enough!");
1331 // Store action are kept in the lower half.
1332 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1333 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1336 /// Indicate that the specified condition code is or isn't supported on the
1337 /// target and indicate what to do about it.
1338 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1339 LegalizeAction Action) {
1340 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1341 "Table isn't big enough!");
1342 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1343 /// value and the upper 27 bits index into the second dimension of the array
1344 /// to select what 32-bit value to use.
1345 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1346 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1347 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1350 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1351 /// to trying a larger integer/fp until it can find one that works. If that
1352 /// default is insufficient, this method can be used by the target to override
1354 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1355 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1358 /// Targets should invoke this method for each target independent node that
1359 /// they want to provide a custom DAG combiner for by implementing the
1360 /// PerformDAGCombine virtual method.
1361 void setTargetDAGCombine(ISD::NodeType NT) {
1362 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1363 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1366 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1367 void setJumpBufSize(unsigned Size) {
1371 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1373 void setJumpBufAlignment(unsigned Align) {
1374 JumpBufAlignment = Align;
1377 /// Set the target's minimum function alignment (in log2(bytes))
1378 void setMinFunctionAlignment(unsigned Align) {
1379 MinFunctionAlignment = Align;
1382 /// Set the target's preferred function alignment. This should be set if
1383 /// there is a performance benefit to higher-than-minimum alignment (in
1385 void setPrefFunctionAlignment(unsigned Align) {
1386 PrefFunctionAlignment = Align;
1389 /// Set the target's preferred loop alignment. Default alignment is zero, it
1390 /// means the target does not care about loop alignment. The alignment is
1391 /// specified in log2(bytes). The target may also override
1392 /// getPrefLoopAlignment to provide per-loop values.
1393 void setPrefLoopAlignment(unsigned Align) {
1394 PrefLoopAlignment = Align;
1397 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1398 void setMinStackArgumentAlignment(unsigned Align) {
1399 MinStackArgumentAlignment = Align;
1402 /// Set if the DAG builder should automatically insert fences and reduce the
1403 /// order of atomic memory operations to Monotonic.
1404 void setInsertFencesForAtomic(bool fence) {
1405 InsertFencesForAtomic = fence;
1409 //===--------------------------------------------------------------------===//
1410 // Addressing mode description hooks (used by LSR etc).
1413 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1414 /// instructions reading the address. This allows as much computation as
1415 /// possible to be done in the address mode for that operand. This hook lets
1416 /// targets also pass back when this should be done on intrinsics which
1418 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1419 SmallVectorImpl<Value*> &/*Ops*/,
1420 Type *&/*AccessTy*/) const {
1424 /// This represents an addressing mode of:
1425 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1426 /// If BaseGV is null, there is no BaseGV.
1427 /// If BaseOffs is zero, there is no base offset.
1428 /// If HasBaseReg is false, there is no base register.
1429 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1432 GlobalValue *BaseGV;
1436 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1439 /// Return true if the addressing mode represented by AM is legal for this
1440 /// target, for a load/store of the specified type.
1442 /// The type may be VoidTy, in which case only return true if the addressing
1443 /// mode is legal for a load/store of any legal type. TODO: Handle
1444 /// pre/postinc as well.
1445 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1447 /// \brief Return the cost of the scaling factor used in the addressing mode
1448 /// represented by AM for this target, for a load/store of the specified type.
1450 /// If the AM is supported, the return value must be >= 0.
1451 /// If the AM is not supported, it returns a negative value.
1452 /// TODO: Handle pre/postinc as well.
1453 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
1454 // Default: assume that any scaling factor used in a legal AM is free.
1455 if (isLegalAddressingMode(AM, Ty)) return 0;
1459 /// Return true if the specified immediate is legal icmp immediate, that is
1460 /// the target has icmp instructions which can compare a register against the
1461 /// immediate without having to materialize the immediate into a register.
1462 virtual bool isLegalICmpImmediate(int64_t) const {
1466 /// Return true if the specified immediate is legal add immediate, that is the
1467 /// target has add instructions which can add a register with the immediate
1468 /// without having to materialize the immediate into a register.
1469 virtual bool isLegalAddImmediate(int64_t) const {
1473 /// Return true if it's significantly cheaper to shift a vector by a uniform
1474 /// scalar than by an amount which will vary across each lane. On x86, for
1475 /// example, there is a "psllw" instruction for the former case, but no simple
1476 /// instruction for a general "a << b" operation on vectors.
1477 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1481 /// Return true if it's free to truncate a value of type Ty1 to type
1482 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1483 /// by referencing its sub-register AX.
1484 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1488 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1489 /// whether a call is in tail position. Typically this means that both results
1490 /// would be assigned to the same register or stack slot, but it could mean
1491 /// the target performs adequate checks of its own before proceeding with the
1493 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1497 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1501 virtual bool isProfitableToHoist(Instruction *I) const { return true; }
1503 /// Return true if the extension represented by \p I is free.
1504 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
1505 /// this method can use the context provided by \p I to decide
1506 /// whether or not \p I is free.
1507 /// This method extends the behavior of the is[Z|FP]ExtFree family.
1508 /// In other words, if is[Z|FP]Free returns true, then this method
1509 /// returns true as well. The converse is not true.
1510 /// The target can perform the adequate checks by overriding isExtFreeImpl.
1511 /// \pre \p I must be a sign, zero, or fp extension.
1512 bool isExtFree(const Instruction *I) const {
1513 switch (I->getOpcode()) {
1514 case Instruction::FPExt:
1515 if (isFPExtFree(EVT::getEVT(I->getType())))
1518 case Instruction::ZExt:
1519 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
1522 case Instruction::SExt:
1525 llvm_unreachable("Instruction is not an extension");
1527 return isExtFreeImpl(I);
1530 /// Return true if any actual instruction that defines a value of type Ty1
1531 /// implicitly zero-extends the value to Ty2 in the result register.
1533 /// This does not necessarily include registers defined in unknown ways, such
1534 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1535 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1536 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1537 /// values implicit zero-extend the result out to 64 bits.
1538 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1542 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1546 /// Return true if the target supplies and combines to a paired load
1547 /// two loaded values of type LoadedType next to each other in memory.
1548 /// RequiredAlignment gives the minimal alignment constraints that must be met
1549 /// to be able to select this paired load.
1551 /// This information is *not* used to generate actual paired loads, but it is
1552 /// used to generate a sequence of loads that is easier to combine into a
1554 /// For instance, something like this:
1555 /// a = load i64* addr
1556 /// b = trunc i64 a to i32
1557 /// c = lshr i64 a, 32
1558 /// d = trunc i64 c to i32
1559 /// will be optimized into:
1560 /// b = load i32* addr1
1561 /// d = load i32* addr2
1562 /// Where addr1 = addr2 +/- sizeof(i32).
1564 /// In other words, unless the target performs a post-isel load combining,
1565 /// this information should not be provided because it will generate more
1567 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1568 unsigned & /*RequiredAligment*/) const {
1572 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1573 unsigned & /*RequiredAligment*/) const {
1577 /// Return true if zero-extending the specific node Val to type VT2 is free
1578 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1579 /// because it's folded such as X86 zero-extending loads).
1580 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1581 return isZExtFree(Val.getValueType(), VT2);
1584 /// Return true if an fpext operation is free (for instance, because
1585 /// single-precision floating-point numbers are implicitly extended to
1586 /// double-precision).
1587 virtual bool isFPExtFree(EVT VT) const {
1588 assert(VT.isFloatingPoint());
1592 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
1593 /// extend node) is profitable.
1594 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
1596 /// Return true if an fneg operation is free to the point where it is never
1597 /// worthwhile to replace it with a bitwise operation.
1598 virtual bool isFNegFree(EVT VT) const {
1599 assert(VT.isFloatingPoint());
1603 /// Return true if an fabs operation is free to the point where it is never
1604 /// worthwhile to replace it with a bitwise operation.
1605 virtual bool isFAbsFree(EVT VT) const {
1606 assert(VT.isFloatingPoint());
1610 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1611 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1612 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1614 /// NOTE: This may be called before legalization on types for which FMAs are
1615 /// not legal, but should return true if those types will eventually legalize
1616 /// to types that support FMAs. After legalization, it will only be called on
1617 /// types that support FMAs (via Legal or Custom actions)
1618 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1622 /// Return true if it's profitable to narrow operations of type VT1 to
1623 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1625 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1629 /// \brief Return true if it is beneficial to convert a load of a constant to
1630 /// just the constant itself.
1631 /// On some targets it might be more efficient to use a combination of
1632 /// arithmetic instructions to materialize the constant instead of loading it
1633 /// from a constant pool.
1634 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1639 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1640 /// with this index. This is needed because EXTRACT_SUBVECTOR usually
1641 /// has custom lowering that depends on the index of the first element,
1642 /// and only the target knows which lowering is cheap.
1643 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const {
1647 //===--------------------------------------------------------------------===//
1648 // Runtime Library hooks
1651 /// Rename the default libcall routine name for the specified libcall.
1652 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1653 LibcallRoutineNames[Call] = Name;
1656 /// Get the libcall routine name for the specified libcall.
1657 const char *getLibcallName(RTLIB::Libcall Call) const {
1658 return LibcallRoutineNames[Call];
1661 /// Override the default CondCode to be used to test the result of the
1662 /// comparison libcall against zero.
1663 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1664 CmpLibcallCCs[Call] = CC;
1667 /// Get the CondCode that's to be used to test the result of the comparison
1668 /// libcall against zero.
1669 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1670 return CmpLibcallCCs[Call];
1673 /// Set the CallingConv that should be used for the specified libcall.
1674 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1675 LibcallCallingConvs[Call] = CC;
1678 /// Get the CallingConv that should be used for the specified libcall.
1679 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1680 return LibcallCallingConvs[Call];
1684 const TargetMachine &TM;
1686 /// True if this is a little endian target.
1687 bool IsLittleEndian;
1689 /// Tells the code generator not to expand operations into sequences that use
1690 /// the select operations if possible.
1691 bool SelectIsExpensive;
1693 /// Tells the code generator that the target has multiple (allocatable)
1694 /// condition registers that can be used to store the results of comparisons
1695 /// for use by selects and conditional branches. With multiple condition
1696 /// registers, the code generator will not aggressively sink comparisons into
1697 /// the blocks of their users.
1698 bool HasMultipleConditionRegisters;
1700 /// Tells the code generator that the target has BitExtract instructions.
1701 /// The code generator will aggressively sink "shift"s into the blocks of
1702 /// their users if the users will generate "and" instructions which can be
1703 /// combined with "shift" to BitExtract instructions.
1704 bool HasExtractBitsInsn;
1706 /// Tells the code generator not to expand integer divides by constants into a
1707 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1708 /// model is in place. If we ever optimize for size, this will be set to true
1709 /// unconditionally.
1712 // Don't expand fsqrt with an approximation based on the inverse sqrt.
1715 /// Tells the code generator to bypass slow divide or remainder
1716 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1717 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1718 /// div/rem when the operands are positive and less than 256.
1719 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1721 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1722 /// signed divide by power of two; let the target handle it.
1723 bool Pow2SDivIsCheap;
1725 /// Tells the code generator that it shouldn't generate extra flow control
1726 /// instructions and should attempt to combine flow control instructions via
1728 bool JumpIsExpensive;
1730 /// Whether the target supports or cares about preserving floating point
1731 /// exception behavior.
1732 bool HasFloatingPointExceptions;
1734 /// This target prefers to use _setjmp to implement llvm.setjmp.
1736 /// Defaults to false.
1737 bool UseUnderscoreSetJmp;
1739 /// This target prefers to use _longjmp to implement llvm.longjmp.
1741 /// Defaults to false.
1742 bool UseUnderscoreLongJmp;
1744 /// Number of blocks threshold to use jump tables.
1745 int MinimumJumpTableEntries;
1747 /// Information about the contents of the high-bits in boolean values held in
1748 /// a type wider than i1. See getBooleanContents.
1749 BooleanContent BooleanContents;
1751 /// Information about the contents of the high-bits in boolean values held in
1752 /// a type wider than i1. See getBooleanContents.
1753 BooleanContent BooleanFloatContents;
1755 /// Information about the contents of the high-bits in boolean vector values
1756 /// when the element type is wider than i1. See getBooleanContents.
1757 BooleanContent BooleanVectorContents;
1759 /// The target scheduling preference: shortest possible total cycles or lowest
1761 Sched::Preference SchedPreferenceInfo;
1763 /// The size, in bytes, of the target's jmp_buf buffers
1764 unsigned JumpBufSize;
1766 /// The alignment, in bytes, of the target's jmp_buf buffers
1767 unsigned JumpBufAlignment;
1769 /// The minimum alignment that any argument on the stack needs to have.
1770 unsigned MinStackArgumentAlignment;
1772 /// The minimum function alignment (used when optimizing for size, and to
1773 /// prevent explicitly provided alignment from leading to incorrect code).
1774 unsigned MinFunctionAlignment;
1776 /// The preferred function alignment (used when alignment unspecified and
1777 /// optimizing for speed).
1778 unsigned PrefFunctionAlignment;
1780 /// The preferred loop alignment.
1781 unsigned PrefLoopAlignment;
1783 /// Whether the DAG builder should automatically insert fences and reduce
1784 /// ordering for atomics. (This will be set for for most architectures with
1785 /// weak memory ordering.)
1786 bool InsertFencesForAtomic;
1788 /// If set to a physical register, this specifies the register that
1789 /// llvm.savestack/llvm.restorestack should save and restore.
1790 unsigned StackPointerRegisterToSaveRestore;
1792 /// If set to a physical register, this specifies the register that receives
1793 /// the exception address on entry to a landing pad.
1794 unsigned ExceptionPointerRegister;
1796 /// If set to a physical register, this specifies the register that receives
1797 /// the exception typeid on entry to a landing pad.
1798 unsigned ExceptionSelectorRegister;
1800 /// This indicates the default register class to use for each ValueType the
1801 /// target supports natively.
1802 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1803 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1804 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1806 /// This indicates the "representative" register class to use for each
1807 /// ValueType the target supports natively. This information is used by the
1808 /// scheduler to track register pressure. By default, the representative
1809 /// register class is the largest legal super-reg register class of the
1810 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1811 /// representative class would be GR32.
1812 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1814 /// This indicates the "cost" of the "representative" register class for each
1815 /// ValueType. The cost is used by the scheduler to approximate register
1817 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1819 /// For any value types we are promoting or expanding, this contains the value
1820 /// type that we are changing to. For Expanded types, this contains one step
1821 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1822 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1823 /// the same type (e.g. i32 -> i32).
1824 MVT TransformToType[MVT::LAST_VALUETYPE];
1826 /// For each operation and each value type, keep a LegalizeAction that
1827 /// indicates how instruction selection should deal with the operation. Most
1828 /// operations are Legal (aka, supported natively by the target), but
1829 /// operations that are not should be described. Note that operations on
1830 /// non-legal value types are not described here.
1831 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1833 /// For each load extension type and each value type, keep a LegalizeAction
1834 /// that indicates how instruction selection should deal with a load of a
1835 /// specific value type and extension type.
1836 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
1837 [ISD::LAST_LOADEXT_TYPE];
1839 /// For each value type pair keep a LegalizeAction that indicates whether a
1840 /// truncating store of a specific value type and truncating type is legal.
1841 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1843 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1844 /// that indicates how instruction selection should deal with the load /
1847 /// The first dimension is the value_type for the reference. The second
1848 /// dimension represents the various modes for load store.
1849 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1851 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1852 /// indicates how instruction selection should deal with the condition code.
1854 /// Because each CC action takes up 2 bits, we need to have the array size be
1855 /// large enough to fit all of the value types. This can be done by rounding
1856 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1857 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1859 ValueTypeActionImpl ValueTypeActions;
1862 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
1865 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1867 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1868 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1871 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1873 /// For operations that must be promoted to a specific type, this holds the
1874 /// destination type. This map should be sparse, so don't hold it as an
1877 /// Targets add entries to this map with AddPromotedToType(..), clients access
1878 /// this with getTypeToPromoteTo(..).
1879 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1882 /// Stores the name each libcall.
1883 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1885 /// The ISD::CondCode that should be used to test the result of each of the
1886 /// comparison libcall against zero.
1887 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1889 /// Stores the CallingConv that should be used for each libcall.
1890 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1893 /// Return true if the extension represented by \p I is free.
1894 /// \pre \p I is a sign, zero, or fp extension and
1895 /// is[Z|FP]ExtFree of the related types is not true.
1896 virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
1898 /// \brief Specify maximum number of store instructions per memset call.
1900 /// When lowering \@llvm.memset this field specifies the maximum number of
1901 /// store operations that may be substituted for the call to memset. Targets
1902 /// must set this value based on the cost threshold for that target. Targets
1903 /// should assume that the memset will be done using as many of the largest
1904 /// store operations first, followed by smaller ones, if necessary, per
1905 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1906 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1907 /// store. This only applies to setting a constant array of a constant size.
1908 unsigned MaxStoresPerMemset;
1910 /// Maximum number of stores operations that may be substituted for the call
1911 /// to memset, used for functions with OptSize attribute.
1912 unsigned MaxStoresPerMemsetOptSize;
1914 /// \brief Specify maximum bytes of store instructions per memcpy call.
1916 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1917 /// store operations that may be substituted for a call to memcpy. Targets
1918 /// must set this value based on the cost threshold for that target. Targets
1919 /// should assume that the memcpy will be done using as many of the largest
1920 /// store operations first, followed by smaller ones, if necessary, per
1921 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1922 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1923 /// and one 1-byte store. This only applies to copying a constant array of
1925 unsigned MaxStoresPerMemcpy;
1927 /// Maximum number of store operations that may be substituted for a call to
1928 /// memcpy, used for functions with OptSize attribute.
1929 unsigned MaxStoresPerMemcpyOptSize;
1931 /// \brief Specify maximum bytes of store instructions per memmove call.
1933 /// When lowering \@llvm.memmove this field specifies the maximum number of
1934 /// store instructions that may be substituted for a call to memmove. Targets
1935 /// must set this value based on the cost threshold for that target. Targets
1936 /// should assume that the memmove will be done using as many of the largest
1937 /// store operations first, followed by smaller ones, if necessary, per
1938 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1939 /// with 8-bit alignment would result in nine 1-byte stores. This only
1940 /// applies to copying a constant array of constant size.
1941 unsigned MaxStoresPerMemmove;
1943 /// Maximum number of store instructions that may be substituted for a call to
1944 /// memmove, used for functions with OpSize attribute.
1945 unsigned MaxStoresPerMemmoveOptSize;
1947 /// Tells the code generator that select is more expensive than a branch if
1948 /// the branch is usually predicted right.
1949 bool PredictableSelectIsExpensive;
1951 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
1952 /// a mask of a single bit, a compare, and a branch into a single instruction.
1953 bool MaskAndBranchFoldingIsLegal;
1955 /// \see enableExtLdPromotion.
1956 bool EnableExtLdPromotion;
1959 /// Return true if the value types that can be represented by the specified
1960 /// register class are all legal.
1961 bool isLegalRC(const TargetRegisterClass *RC) const;
1963 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1964 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1965 MachineBasicBlock *emitPatchPoint(MachineInstr *MI, MachineBasicBlock *MBB) const;
1968 /// This class defines information used to lower LLVM code to legal SelectionDAG
1969 /// operators that the target instruction selector can accept natively.
1971 /// This class also defines callbacks that targets must implement to lower
1972 /// target-specific constructs to SelectionDAG operators.
1973 class TargetLowering : public TargetLoweringBase {
1974 TargetLowering(const TargetLowering&) = delete;
1975 void operator=(const TargetLowering&) = delete;
1978 /// NOTE: The TargetMachine owns TLOF.
1979 explicit TargetLowering(const TargetMachine &TM);
1981 /// Returns true by value, base pointer and offset pointer and addressing mode
1982 /// by reference if the node's address can be legally represented as
1983 /// pre-indexed load / store address.
1984 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
1985 SDValue &/*Offset*/,
1986 ISD::MemIndexedMode &/*AM*/,
1987 SelectionDAG &/*DAG*/) const {
1991 /// Returns true by value, base pointer and offset pointer and addressing mode
1992 /// by reference if this node can be combined with a load / store to form a
1993 /// post-indexed load / store.
1994 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
1996 SDValue &/*Offset*/,
1997 ISD::MemIndexedMode &/*AM*/,
1998 SelectionDAG &/*DAG*/) const {
2002 /// Return the entry encoding for a jump table in the current function. The
2003 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2004 virtual unsigned getJumpTableEncoding() const;
2006 virtual const MCExpr *
2007 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2008 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2009 MCContext &/*Ctx*/) const {
2010 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2013 /// Returns relocation base for the given PIC jumptable.
2014 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2015 SelectionDAG &DAG) const;
2017 /// This returns the relocation base for the given PIC jumptable, the same as
2018 /// getPICJumpTableRelocBase, but as an MCExpr.
2019 virtual const MCExpr *
2020 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2021 unsigned JTI, MCContext &Ctx) const;
2023 /// Return true if folding a constant offset with the given GlobalAddress is
2024 /// legal. It is frequently not legal in PIC relocation models.
2025 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2027 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2028 SDValue &Chain) const;
2030 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
2031 SDValue &NewLHS, SDValue &NewRHS,
2032 ISD::CondCode &CCCode, SDLoc DL) const;
2034 /// Returns a pair of (return value, chain).
2035 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2036 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2037 EVT RetVT, const SDValue *Ops,
2038 unsigned NumOps, bool isSigned,
2039 SDLoc dl, bool doesNotReturn = false,
2040 bool isReturnValueUsed = true) const;
2042 //===--------------------------------------------------------------------===//
2043 // TargetLowering Optimization Methods
2046 /// A convenience struct that encapsulates a DAG, and two SDValues for
2047 /// returning information from TargetLowering to its clients that want to
2049 struct TargetLoweringOpt {
2056 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2058 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2060 bool LegalTypes() const { return LegalTys; }
2061 bool LegalOperations() const { return LegalOps; }
2063 bool CombineTo(SDValue O, SDValue N) {
2069 /// Check to see if the specified operand of the specified instruction is a
2070 /// constant integer. If so, check to see if there are any bits set in the
2071 /// constant that are not demanded. If so, shrink the constant and return
2073 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
2075 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2076 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2077 /// generalized for targets with other types of implicit widening casts.
2078 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2082 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2083 /// result of Op are ever used downstream. If we can use this information to
2084 /// simplify Op, create a new simplified DAG node and return true, returning
2085 /// the original and new nodes in Old and New. Otherwise, analyze the
2086 /// expression and return a mask of KnownOne and KnownZero bits for the
2087 /// expression (used to simplify the caller). The KnownZero/One bits may only
2088 /// be accurate for those bits in the DemandedMask.
2089 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2090 APInt &KnownZero, APInt &KnownOne,
2091 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2093 /// Determine which of the bits specified in Mask are known to be either zero
2094 /// or one and return them in the KnownZero/KnownOne bitsets.
2095 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2098 const SelectionDAG &DAG,
2099 unsigned Depth = 0) const;
2101 /// This method can be implemented by targets that want to expose additional
2102 /// information about sign bits to the DAG Combiner.
2103 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2104 const SelectionDAG &DAG,
2105 unsigned Depth = 0) const;
2107 struct DAGCombinerInfo {
2108 void *DC; // The DAG Combiner object.
2110 bool CalledByLegalizer;
2114 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2115 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2117 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2118 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2119 bool isAfterLegalizeVectorOps() const {
2120 return Level == AfterLegalizeDAG;
2122 CombineLevel getDAGCombineLevel() { return Level; }
2123 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2125 void AddToWorklist(SDNode *N);
2126 void RemoveFromWorklist(SDNode *N);
2127 SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2128 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2129 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2131 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2134 /// Return if the N is a constant or constant vector equal to the true value
2135 /// from getBooleanContents().
2136 bool isConstTrueVal(const SDNode *N) const;
2138 /// Return if the N is a constant or constant vector equal to the false value
2139 /// from getBooleanContents().
2140 bool isConstFalseVal(const SDNode *N) const;
2142 /// Try to simplify a setcc built with the specified operands and cc. If it is
2143 /// unable to simplify it, return a null SDValue.
2144 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2145 ISD::CondCode Cond, bool foldBooleans,
2146 DAGCombinerInfo &DCI, SDLoc dl) const;
2148 /// Returns true (and the GlobalValue and the offset) if the node is a
2149 /// GlobalAddress + offset.
2151 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2153 /// This method will be invoked for all target nodes and for any
2154 /// target-independent nodes that the target has registered with invoke it
2157 /// The semantics are as follows:
2159 /// SDValue.Val == 0 - No change was made
2160 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2161 /// otherwise - N should be replaced by the returned Operand.
2163 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2164 /// more complex transformations.
2166 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2168 /// Return true if it is profitable to move a following shift through this
2169 // node, adjusting any immediate operands as necessary to preserve semantics.
2170 // This transformation may not be desirable if it disrupts a particularly
2171 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2172 // By default, it returns true.
2173 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2177 /// Return true if the target has native support for the specified value type
2178 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2179 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2180 /// and some i16 instructions are slow.
2181 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2182 // By default, assume all legal types are desirable.
2183 return isTypeLegal(VT);
2186 /// Return true if it is profitable for dag combiner to transform a floating
2187 /// point op of specified opcode to a equivalent op of an integer
2188 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2189 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2194 /// This method query the target whether it is beneficial for dag combiner to
2195 /// promote the specified node. If true, it should return the desired
2196 /// promotion type by reference.
2197 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2201 //===--------------------------------------------------------------------===//
2202 // Lowering methods - These methods must be implemented by targets so that
2203 // the SelectionDAGBuilder code knows how to lower these.
2206 /// This hook must be implemented to lower the incoming (formal) arguments,
2207 /// described by the Ins array, into the specified DAG. The implementation
2208 /// should fill in the InVals array with legal-type argument values, and
2209 /// return the resulting token chain value.
2212 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2214 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2215 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2216 SmallVectorImpl<SDValue> &/*InVals*/) const {
2217 llvm_unreachable("Not Implemented");
2220 struct ArgListEntry {
2229 bool isInAlloca : 1;
2230 bool isReturned : 1;
2233 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2234 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2235 isReturned(false), Alignment(0) { }
2237 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2239 typedef std::vector<ArgListEntry> ArgListTy;
2241 /// This structure contains all information that is necessary for lowering
2242 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2243 /// needs to lower a call, and targets will see this struct in their LowerCall
2245 struct CallLoweringInfo {
2252 bool DoesNotReturn : 1;
2253 bool IsReturnValueUsed : 1;
2255 // IsTailCall should be modified by implementations of
2256 // TargetLowering::LowerCall that perform tail call conversions.
2259 unsigned NumFixedArgs;
2260 CallingConv::ID CallConv;
2265 ImmutableCallSite *CS;
2267 SmallVector<ISD::OutputArg, 32> Outs;
2268 SmallVector<SDValue, 32> OutVals;
2269 SmallVector<ISD::InputArg, 32> Ins;
2271 CallLoweringInfo(SelectionDAG &DAG)
2272 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2273 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2274 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2275 DAG(DAG), CS(nullptr), IsPatchPoint(false) {}
2277 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2282 CallLoweringInfo &setChain(SDValue InChain) {
2287 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2288 SDValue Target, ArgListTy &&ArgsList,
2289 unsigned FixedArgs = -1) {
2294 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2295 Args = std::move(ArgsList);
2299 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2300 SDValue Target, ArgListTy &&ArgsList,
2301 ImmutableCallSite &Call) {
2304 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2305 DoesNotReturn = Call.doesNotReturn();
2306 IsVarArg = FTy->isVarArg();
2307 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2308 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2309 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2313 CallConv = Call.getCallingConv();
2314 NumFixedArgs = FTy->getNumParams();
2315 Args = std::move(ArgsList);
2322 CallLoweringInfo &setInRegister(bool Value = true) {
2327 CallLoweringInfo &setNoReturn(bool Value = true) {
2328 DoesNotReturn = Value;
2332 CallLoweringInfo &setVarArg(bool Value = true) {
2337 CallLoweringInfo &setTailCall(bool Value = true) {
2342 CallLoweringInfo &setDiscardResult(bool Value = true) {
2343 IsReturnValueUsed = !Value;
2347 CallLoweringInfo &setSExtResult(bool Value = true) {
2352 CallLoweringInfo &setZExtResult(bool Value = true) {
2357 CallLoweringInfo &setIsPatchPoint(bool Value = true) {
2358 IsPatchPoint = Value;
2362 ArgListTy &getArgs() {
2367 /// This function lowers an abstract call to a function into an actual call.
2368 /// This returns a pair of operands. The first element is the return value
2369 /// for the function (if RetTy is not VoidTy). The second element is the
2370 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2371 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2373 /// This hook must be implemented to lower calls into the the specified
2374 /// DAG. The outgoing arguments to the call are described by the Outs array,
2375 /// and the values to be returned by the call are described by the Ins
2376 /// array. The implementation should fill in the InVals array with legal-type
2377 /// return values from the call, and return the resulting token chain value.
2379 LowerCall(CallLoweringInfo &/*CLI*/,
2380 SmallVectorImpl<SDValue> &/*InVals*/) const {
2381 llvm_unreachable("Not Implemented");
2384 /// Target-specific cleanup for formal ByVal parameters.
2385 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2387 /// This hook should be implemented to check whether the return values
2388 /// described by the Outs array can fit into the return registers. If false
2389 /// is returned, an sret-demotion is performed.
2390 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2391 MachineFunction &/*MF*/, bool /*isVarArg*/,
2392 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2393 LLVMContext &/*Context*/) const
2395 // Return true by default to get preexisting behavior.
2399 /// This hook must be implemented to lower outgoing return values, described
2400 /// by the Outs array, into the specified DAG. The implementation should
2401 /// return the resulting token chain value.
2403 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2405 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2406 const SmallVectorImpl<SDValue> &/*OutVals*/,
2407 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2408 llvm_unreachable("Not Implemented");
2411 /// Return true if result of the specified node is used by a return node
2412 /// only. It also compute and return the input chain for the tail call.
2414 /// This is used to determine whether it is possible to codegen a libcall as
2415 /// tail call at legalization time.
2416 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2420 /// Return true if the target may be able emit the call instruction as a tail
2421 /// call. This is used by optimization passes to determine if it's profitable
2422 /// to duplicate return instructions to enable tailcall optimization.
2423 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2427 /// Return the builtin name for the __builtin___clear_cache intrinsic
2428 /// Default is to invoke the clear cache library call
2429 virtual const char * getClearCacheBuiltinName() const {
2430 return "__clear_cache";
2433 /// Return the register ID of the name passed in. Used by named register
2434 /// global variables extension. There is no target-independent behaviour
2435 /// so the default action is to bail.
2436 virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
2437 report_fatal_error("Named registers not implemented for this target");
2440 /// Return the type that should be used to zero or sign extend a
2441 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2442 /// convention requires the return type to be promoted, but this is not true
2443 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2444 /// calling conventions. The frontend should handle this and include all of
2445 /// the necessary information.
2446 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2447 ISD::NodeType /*ExtendKind*/) const {
2448 EVT MinVT = getRegisterType(Context, MVT::i32);
2449 return VT.bitsLT(MinVT) ? MinVT : VT;
2452 /// For some targets, an LLVM struct type must be broken down into multiple
2453 /// simple types, but the calling convention specifies that the entire struct
2454 /// must be passed in a block of consecutive registers.
2456 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2457 bool isVarArg) const {
2461 /// Returns a 0 terminated array of registers that can be safely used as
2462 /// scratch registers.
2463 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2467 /// This callback is used to prepare for a volatile or atomic load.
2468 /// It takes a chain node as input and returns the chain for the load itself.
2470 /// Having a callback like this is necessary for targets like SystemZ,
2471 /// which allows a CPU to reuse the result of a previous load indefinitely,
2472 /// even if a cache-coherent store is performed by another CPU. The default
2473 /// implementation does nothing.
2474 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2475 SelectionDAG &DAG) const {
2479 /// This callback is invoked by the type legalizer to legalize nodes with an
2480 /// illegal operand type but legal result types. It replaces the
2481 /// LowerOperation callback in the type Legalizer. The reason we can not do
2482 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2483 /// use this callback.
2485 /// TODO: Consider merging with ReplaceNodeResults.
2487 /// The target places new result values for the node in Results (their number
2488 /// and types must exactly match those of the original return values of
2489 /// the node), or leaves Results empty, which indicates that the node is not
2490 /// to be custom lowered after all.
2491 /// The default implementation calls LowerOperation.
2492 virtual void LowerOperationWrapper(SDNode *N,
2493 SmallVectorImpl<SDValue> &Results,
2494 SelectionDAG &DAG) const;
2496 /// This callback is invoked for operations that are unsupported by the
2497 /// target, which are registered to use 'custom' lowering, and whose defined
2498 /// values are all legal. If the target has no operations that require custom
2499 /// lowering, it need not implement this. The default implementation of this
2501 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2503 /// This callback is invoked when a node result type is illegal for the
2504 /// target, and the operation was registered to use 'custom' lowering for that
2505 /// result type. The target places new result values for the node in Results
2506 /// (their number and types must exactly match those of the original return
2507 /// values of the node), or leaves Results empty, which indicates that the
2508 /// node is not to be custom lowered after all.
2510 /// If the target has no operations that require custom lowering, it need not
2511 /// implement this. The default implementation aborts.
2512 virtual void ReplaceNodeResults(SDNode * /*N*/,
2513 SmallVectorImpl<SDValue> &/*Results*/,
2514 SelectionDAG &/*DAG*/) const {
2515 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2518 /// This method returns the name of a target specific DAG node.
2519 virtual const char *getTargetNodeName(unsigned Opcode) const;
2521 /// This method returns a target specific FastISel object, or null if the
2522 /// target does not support "fast" ISel.
2523 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2524 const TargetLibraryInfo *) const {
2529 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2530 SelectionDAG &DAG) const;
2532 //===--------------------------------------------------------------------===//
2533 // Inline Asm Support hooks
2536 /// This hook allows the target to expand an inline asm call to be explicit
2537 /// llvm code if it wants to. This is useful for turning simple inline asms
2538 /// into LLVM intrinsics, which gives the compiler more information about the
2539 /// behavior of the code.
2540 virtual bool ExpandInlineAsm(CallInst *) const {
2544 enum ConstraintType {
2545 C_Register, // Constraint represents specific register(s).
2546 C_RegisterClass, // Constraint represents any of register(s) in class.
2547 C_Memory, // Memory constraint.
2548 C_Other, // Something else.
2549 C_Unknown // Unsupported constraint.
2552 enum ConstraintWeight {
2554 CW_Invalid = -1, // No match.
2555 CW_Okay = 0, // Acceptable.
2556 CW_Good = 1, // Good weight.
2557 CW_Better = 2, // Better weight.
2558 CW_Best = 3, // Best weight.
2560 // Well-known weights.
2561 CW_SpecificReg = CW_Okay, // Specific register operands.
2562 CW_Register = CW_Good, // Register operands.
2563 CW_Memory = CW_Better, // Memory operands.
2564 CW_Constant = CW_Best, // Constant operand.
2565 CW_Default = CW_Okay // Default or don't know type.
2568 /// This contains information for each constraint that we are lowering.
2569 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2570 /// This contains the actual string for the code, like "m". TargetLowering
2571 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2572 /// matches the operand.
2573 std::string ConstraintCode;
2575 /// Information about the constraint code, e.g. Register, RegisterClass,
2576 /// Memory, Other, Unknown.
2577 TargetLowering::ConstraintType ConstraintType;
2579 /// If this is the result output operand or a clobber, this is null,
2580 /// otherwise it is the incoming operand to the CallInst. This gets
2581 /// modified as the asm is processed.
2582 Value *CallOperandVal;
2584 /// The ValueType for the operand value.
2587 /// Return true of this is an input operand that is a matching constraint
2589 bool isMatchingInputConstraint() const;
2591 /// If this is an input matching constraint, this method returns the output
2592 /// operand it matches.
2593 unsigned getMatchedOperand() const;
2595 /// Copy constructor for copying from a ConstraintInfo.
2596 AsmOperandInfo(InlineAsm::ConstraintInfo Info)
2597 : InlineAsm::ConstraintInfo(std::move(Info)),
2598 ConstraintType(TargetLowering::C_Unknown), CallOperandVal(nullptr),
2599 ConstraintVT(MVT::Other) {}
2602 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2604 /// Split up the constraint string from the inline assembly value into the
2605 /// specific constraints and their prefixes, and also tie in the associated
2606 /// operand values. If this returns an empty vector, and if the constraint
2607 /// string itself isn't empty, there was an error parsing.
2608 virtual AsmOperandInfoVector ParseConstraints(const TargetRegisterInfo *TRI,
2609 ImmutableCallSite CS) const;
2611 /// Examine constraint type and operand type and determine a weight value.
2612 /// The operand object must already have been set up with the operand type.
2613 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2614 AsmOperandInfo &info, int maIndex) const;
2616 /// Examine constraint string and operand type and determine a weight value.
2617 /// The operand object must already have been set up with the operand type.
2618 virtual ConstraintWeight getSingleConstraintMatchWeight(
2619 AsmOperandInfo &info, const char *constraint) const;
2621 /// Determines the constraint code and constraint type to use for the specific
2622 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2623 /// If the actual operand being passed in is available, it can be passed in as
2624 /// Op, otherwise an empty SDValue can be passed.
2625 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2627 SelectionDAG *DAG = nullptr) const;
2629 /// Given a constraint, return the type of constraint it is for this target.
2630 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2632 /// Given a physical register constraint (e.g. {edx}), return the register
2633 /// number and the register class for the register.
2635 /// Given a register class constraint, like 'r', if this corresponds directly
2636 /// to an LLVM register class, return a register of 0 and the register class
2639 /// This should only be used for C_Register constraints. On error, this
2640 /// returns a register number of 0 and a null register class pointer.
2641 virtual std::pair<unsigned, const TargetRegisterClass *>
2642 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2643 const std::string &Constraint, MVT VT) const;
2646 getInlineAsmMemConstraint(const std::string &ConstraintCode) const {
2647 if (ConstraintCode == "i")
2648 return InlineAsm::Constraint_i;
2649 else if (ConstraintCode == "m")
2650 return InlineAsm::Constraint_m;
2651 return InlineAsm::Constraint_Unknown;
2654 /// Try to replace an X constraint, which matches anything, with another that
2655 /// has more specific requirements based on the type of the corresponding
2656 /// operand. This returns null if there is no replacement to make.
2657 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2659 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2660 /// add anything to Ops.
2661 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2662 std::vector<SDValue> &Ops,
2663 SelectionDAG &DAG) const;
2665 //===--------------------------------------------------------------------===//
2666 // Div utility functions
2668 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2669 SelectionDAG &DAG) const;
2670 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2671 bool IsAfterLegalization,
2672 std::vector<SDNode *> *Created) const;
2673 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2674 bool IsAfterLegalization,
2675 std::vector<SDNode *> *Created) const;
2676 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2678 std::vector<SDNode *> *Created) const {
2682 /// Indicate whether this target prefers to combine the given number of FDIVs
2683 /// with the same divisor.
2684 virtual bool combineRepeatedFPDivisors(unsigned NumUsers) const {
2688 /// Hooks for building estimates in place of slower divisions and square
2691 /// Return a reciprocal square root estimate value for the input operand.
2692 /// The RefinementSteps output is the number of Newton-Raphson refinement
2693 /// iterations required to generate a sufficient (though not necessarily
2694 /// IEEE-754 compliant) estimate for the value type.
2695 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
2696 /// algorithm implementation that uses one constant or two constants.
2697 /// A target may choose to implement its own refinement within this function.
2698 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2699 /// any further refinement of the estimate.
2700 /// An empty SDValue return means no estimate sequence can be created.
2701 virtual SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2702 unsigned &RefinementSteps,
2703 bool &UseOneConstNR) const {
2707 /// Return a reciprocal estimate value for the input operand.
2708 /// The RefinementSteps output is the number of Newton-Raphson refinement
2709 /// iterations required to generate a sufficient (though not necessarily
2710 /// IEEE-754 compliant) estimate for the value type.
2711 /// A target may choose to implement its own refinement within this function.
2712 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2713 /// any further refinement of the estimate.
2714 /// An empty SDValue return means no estimate sequence can be created.
2715 virtual SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2716 unsigned &RefinementSteps) const {
2720 //===--------------------------------------------------------------------===//
2721 // Legalization utility functions
2724 /// Expand a MUL into two nodes. One that computes the high bits of
2725 /// the result and one that computes the low bits.
2726 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2727 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2728 /// if you want to control how low bits are extracted from the LHS.
2729 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2730 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2731 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2732 /// \returns true if the node has been expanded. false if it has not
2733 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2734 SelectionDAG &DAG, SDValue LL = SDValue(),
2735 SDValue LH = SDValue(), SDValue RL = SDValue(),
2736 SDValue RH = SDValue()) const;
2738 /// Expand float(f32) to SINT(i64) conversion
2739 /// \param N Node to expand
2740 /// \param Result output after conversion
2741 /// \returns True, if the expansion was successful, false otherwise
2742 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
2744 //===--------------------------------------------------------------------===//
2745 // Instruction Emitting Hooks
2748 /// This method should be implemented by targets that mark instructions with
2749 /// the 'usesCustomInserter' flag. These instructions are special in various
2750 /// ways, which require special support to insert. The specified MachineInstr
2751 /// is created but not inserted into any basic blocks, and this method is
2752 /// called to expand it into a sequence of instructions, potentially also
2753 /// creating new basic blocks and control flow.
2754 /// As long as the returned basic block is different (i.e., we created a new
2755 /// one), the custom inserter is free to modify the rest of \p MBB.
2756 virtual MachineBasicBlock *
2757 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2759 /// This method should be implemented by targets that mark instructions with
2760 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2761 /// instruction selection by target hooks. e.g. To fill in optional defs for
2762 /// ARM 's' setting instructions.
2764 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2766 /// If this function returns true, SelectionDAGBuilder emits a
2767 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
2768 virtual bool useLoadStackGuardNode() const {
2773 /// Given an LLVM IR type and return type attributes, compute the return value
2774 /// EVTs and flags, and optionally also the offsets, if the return value is
2775 /// being lowered to memory.
2776 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2777 SmallVectorImpl<ISD::OutputArg> &Outs,
2778 const TargetLowering &TLI);
2780 } // end llvm namespace