1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/IRBuilder.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Target/TargetCallingConv.h"
38 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class ImmutableCallSite;
50 class MachineBasicBlock;
51 class MachineFunction;
53 class MachineJumpTableInfo;
59 template<typename T> class SmallVectorImpl;
61 class TargetRegisterClass;
62 class TargetLibraryInfo;
63 class TargetLoweringObjectFile;
68 None, // No preference
69 Source, // Follow source order.
70 RegPressure, // Scheduling for lowest register pressure.
71 Hybrid, // Scheduling for both latency and register pressure.
72 ILP, // Scheduling for ILP in low register pressure mode.
73 VLIW // Scheduling for VLIW targets.
77 /// This base class for TargetLowering contains the SelectionDAG-independent
78 /// parts that can be used from the rest of CodeGen.
79 class TargetLoweringBase {
80 TargetLoweringBase(const TargetLoweringBase&) = delete;
81 void operator=(const TargetLoweringBase&) = delete;
84 /// This enum indicates whether operations are valid for a target, and if not,
85 /// what action should be used to make them valid.
87 Legal, // The target natively supports this operation.
88 Promote, // This operation should be executed in a larger type.
89 Expand, // Try to expand this to other ops, otherwise use a libcall.
90 Custom // Use the LowerOperation hook to implement custom lowering.
93 /// This enum indicates whether a types are legal for a target, and if not,
94 /// what action should be used to make them valid.
95 enum LegalizeTypeAction {
96 TypeLegal, // The target natively supports this type.
97 TypePromoteInteger, // Replace this integer with a larger one.
98 TypeExpandInteger, // Split this integer into two of half the size.
99 TypeSoftenFloat, // Convert this float to a same size integer type.
100 TypeExpandFloat, // Split this float into two of half the size.
101 TypeScalarizeVector, // Replace this one-element vector with its element.
102 TypeSplitVector, // Split this vector into two of half the size.
103 TypeWidenVector, // This vector should be widened into a larger vector.
104 TypePromoteFloat // Replace this float with a larger one.
107 /// LegalizeKind holds the legalization kind that needs to happen to EVT
108 /// in order to type-legalize it.
109 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
111 /// Enum that describes how the target represents true/false values.
112 enum BooleanContent {
113 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
114 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
115 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
118 /// Enum that describes what type of support for selects the target has.
119 enum SelectSupportKind {
120 ScalarValSelect, // The target supports scalar selects (ex: cmov).
121 ScalarCondVectorVal, // The target supports selects with a scalar condition
122 // and vector values (ex: cmov).
123 VectorMaskSelect // The target supports vector selects with a vector
124 // mask (ex: x86 blends).
127 /// Enum that specifies what a AtomicRMWInst is expanded to, if at all. Exists
128 /// because different targets have different levels of support for these
129 /// atomic RMW instructions, and also have different options w.r.t. what they
130 /// should expand to.
131 enum class AtomicRMWExpansionKind {
132 None, // Don't expand the instruction.
133 LLSC, // Expand the instruction into loadlinked/storeconditional; used
134 // by ARM/AArch64. Implies `hasLoadLinkedStoreConditional`
136 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
139 static ISD::NodeType getExtendForContent(BooleanContent Content) {
141 case UndefinedBooleanContent:
142 // Extend by adding rubbish bits.
143 return ISD::ANY_EXTEND;
144 case ZeroOrOneBooleanContent:
145 // Extend by adding zero bits.
146 return ISD::ZERO_EXTEND;
147 case ZeroOrNegativeOneBooleanContent:
148 // Extend by copying the sign bit.
149 return ISD::SIGN_EXTEND;
151 llvm_unreachable("Invalid content kind");
154 /// NOTE: The TargetMachine owns TLOF.
155 explicit TargetLoweringBase(const TargetMachine &TM);
156 virtual ~TargetLoweringBase() {}
159 /// \brief Initialize all of the actions to default values.
163 const TargetMachine &getTargetMachine() const { return TM; }
164 const DataLayout *getDataLayout() const { return TM.getDataLayout(); }
166 bool isBigEndian() const { return !IsLittleEndian; }
167 bool isLittleEndian() const { return IsLittleEndian; }
168 virtual bool useSoftFloat() const { return false; }
170 /// Return the pointer type for the given address space, defaults to
171 /// the pointer type from the data layout.
172 /// FIXME: The default needs to be removed once all the code is updated.
173 virtual MVT getPointerTy(uint32_t /*AS*/ = 0) const;
174 unsigned getPointerSizeInBits(uint32_t AS = 0) const;
175 unsigned getPointerTypeSizeInBits(Type *Ty) const;
176 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
178 EVT getShiftAmountTy(EVT LHSTy) const;
180 /// Returns the type to be used for the index operand of:
181 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
182 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
183 virtual MVT getVectorIdxTy() const {
184 return getPointerTy();
187 /// Return true if the select operation is expensive for this target.
188 bool isSelectExpensive() const { return SelectIsExpensive; }
190 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
194 /// Return true if multiple condition registers are available.
195 bool hasMultipleConditionRegisters() const {
196 return HasMultipleConditionRegisters;
199 /// Return true if the target has BitExtract instructions.
200 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
202 /// Return the preferred vector type legalization action.
203 virtual TargetLoweringBase::LegalizeTypeAction
204 getPreferredVectorAction(EVT VT) const {
205 // The default action for one element vectors is to scalarize
206 if (VT.getVectorNumElements() == 1)
207 return TypeScalarizeVector;
208 // The default action for other vectors is to promote
209 return TypePromoteInteger;
212 // There are two general methods for expanding a BUILD_VECTOR node:
213 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
215 // 2. Build the vector on the stack and then load it.
216 // If this function returns true, then method (1) will be used, subject to
217 // the constraint that all of the necessary shuffles are legal (as determined
218 // by isShuffleMaskLegal). If this function returns false, then method (2) is
219 // always used. The vector type, and the number of defined values, are
222 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
223 unsigned DefinedValues) const {
224 return DefinedValues < 3;
227 /// Return true if integer divide is usually cheaper than a sequence of
228 /// several shifts, adds, and multiplies for this target.
229 bool isIntDivCheap() const { return IntDivIsCheap; }
231 /// Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x)
232 bool isFsqrtCheap() const {
236 /// Returns true if target has indicated at least one type should be bypassed.
237 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
239 /// Returns map of slow types for division or remainder with corresponding
241 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
242 return BypassSlowDivWidths;
245 /// Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra.
246 bool isPow2SDivCheap() const { return Pow2SDivIsCheap; }
248 /// Return true if Flow Control is an expensive operation that should be
250 bool isJumpExpensive() const { return JumpIsExpensive; }
252 /// Return true if selects are only cheaper than branches if the branch is
253 /// unlikely to be predicted right.
254 bool isPredictableSelectExpensive() const {
255 return PredictableSelectIsExpensive;
258 /// isLoadBitCastBeneficial() - Return true if the following transform
260 /// fold (conv (load x)) -> (load (conv*)x)
261 /// On architectures that don't natively support some vector loads
262 /// efficiently, casting the load to a smaller vector of larger types and
263 /// loading is more efficient, however, this can be undone by optimizations in
265 virtual bool isLoadBitCastBeneficial(EVT /* Load */,
266 EVT /* Bitcast */) const {
270 /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
271 virtual bool isCheapToSpeculateCttz() const {
275 /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
276 virtual bool isCheapToSpeculateCtlz() const {
280 /// \brief Return if the target supports combining a
283 /// %andResult = and %val1, #imm-with-one-bit-set;
284 /// %icmpResult = icmp %andResult, 0
285 /// br i1 %icmpResult, label %dest1, label %dest2
287 /// into a single machine instruction of a form like:
289 /// brOnBitSet %register, #bitNumber, dest
291 bool isMaskAndBranchFoldingLegal() const {
292 return MaskAndBranchFoldingIsLegal;
295 /// \brief Return true if the target wants to use the optimization that
296 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
297 /// promotedInst1(...(promotedInstN(ext(load)))).
298 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
300 /// Return true if the target can combine store(extractelement VectorTy,
302 /// \p Cost[out] gives the cost of that transformation when this is true.
303 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
304 unsigned &Cost) const {
308 /// Return true if target supports floating point exceptions.
309 bool hasFloatingPointExceptions() const {
310 return HasFloatingPointExceptions;
313 /// Return true if target always beneficiates from combining into FMA for a
314 /// given value type. This must typically return false on targets where FMA
315 /// takes more cycles to execute than FADD.
316 virtual bool enableAggressiveFMAFusion(EVT VT) const {
320 /// Return the ValueType of the result of SETCC operations.
321 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
323 /// Return the ValueType for comparison libcalls. Comparions libcalls include
324 /// floating point comparion calls, and Ordered/Unordered check calls on
325 /// floating point numbers.
327 MVT::SimpleValueType getCmpLibcallReturnType() const;
329 /// For targets without i1 registers, this gives the nature of the high-bits
330 /// of boolean values held in types wider than i1.
332 /// "Boolean values" are special true/false values produced by nodes like
333 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
334 /// Not to be confused with general values promoted from i1. Some cpus
335 /// distinguish between vectors of boolean and scalars; the isVec parameter
336 /// selects between the two kinds. For example on X86 a scalar boolean should
337 /// be zero extended from i1, while the elements of a vector of booleans
338 /// should be sign extended from i1.
340 /// Some cpus also treat floating point types the same way as they treat
341 /// vectors instead of the way they treat scalars.
342 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
344 return BooleanVectorContents;
345 return isFloat ? BooleanFloatContents : BooleanContents;
348 BooleanContent getBooleanContents(EVT Type) const {
349 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
352 /// Return target scheduling preference.
353 Sched::Preference getSchedulingPreference() const {
354 return SchedPreferenceInfo;
357 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
358 /// for different nodes. This function returns the preference (or none) for
360 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
364 /// Return the register class that should be used for the specified value
366 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
367 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
368 assert(RC && "This value type is not natively supported!");
372 /// Return the 'representative' register class for the specified value
375 /// The 'representative' register class is the largest legal super-reg
376 /// register class for the register class of the value type. For example, on
377 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
378 /// register class is GR64 on x86_64.
379 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
380 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
384 /// Return the cost of the 'representative' register class for the specified
386 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
387 return RepRegClassCostForVT[VT.SimpleTy];
390 /// Return true if the target has native support for the specified value type.
391 /// This means that it has a register that directly holds it without
392 /// promotions or expansions.
393 bool isTypeLegal(EVT VT) const {
394 assert(!VT.isSimple() ||
395 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
396 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
399 class ValueTypeActionImpl {
400 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
401 /// that indicates how instruction selection should deal with the type.
402 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
405 ValueTypeActionImpl() {
406 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
409 LegalizeTypeAction getTypeAction(MVT VT) const {
410 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
413 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
414 unsigned I = VT.SimpleTy;
415 ValueTypeActions[I] = Action;
419 const ValueTypeActionImpl &getValueTypeActions() const {
420 return ValueTypeActions;
423 /// Return how we should legalize values of this type, either it is already
424 /// legal (return 'Legal') or we need to promote it to a larger type (return
425 /// 'Promote'), or we need to expand it into multiple registers of smaller
426 /// integer type (return 'Expand'). 'Custom' is not an option.
427 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
428 return getTypeConversion(Context, VT).first;
430 LegalizeTypeAction getTypeAction(MVT VT) const {
431 return ValueTypeActions.getTypeAction(VT);
434 /// For types supported by the target, this is an identity function. For
435 /// types that must be promoted to larger types, this returns the larger type
436 /// to promote to. For integer types that are larger than the largest integer
437 /// register, this contains one step in the expansion to get to the smaller
438 /// register. For illegal floating point types, this returns the integer type
440 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
441 return getTypeConversion(Context, VT).second;
444 /// For types supported by the target, this is an identity function. For
445 /// types that must be expanded (i.e. integer types that are larger than the
446 /// largest integer register or illegal floating point types), this returns
447 /// the largest legal type it will be expanded to.
448 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
449 assert(!VT.isVector());
451 switch (getTypeAction(Context, VT)) {
454 case TypeExpandInteger:
455 VT = getTypeToTransformTo(Context, VT);
458 llvm_unreachable("Type is not legal nor is it to be expanded!");
463 /// Vector types are broken down into some number of legal first class types.
464 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
465 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
466 /// turns into 4 EVT::i32 values with both PPC and X86.
468 /// This method returns the number of registers needed, and the VT for each
469 /// register. It also returns the VT and quantity of the intermediate values
470 /// before they are promoted/expanded.
471 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
473 unsigned &NumIntermediates,
474 MVT &RegisterVT) const;
476 struct IntrinsicInfo {
477 unsigned opc; // target opcode
478 EVT memVT; // memory VT
479 const Value* ptrVal; // value representing memory location
480 int offset; // offset off of ptrVal
481 unsigned size; // the size of the memory location
482 // (taken from memVT if zero)
483 unsigned align; // alignment
484 bool vol; // is volatile?
485 bool readMem; // reads memory?
486 bool writeMem; // writes memory?
488 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
489 vol(false), readMem(false), writeMem(false) {}
492 /// Given an intrinsic, checks if on the target the intrinsic will need to map
493 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
494 /// true and store the intrinsic information into the IntrinsicInfo that was
495 /// passed to the function.
496 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
497 unsigned /*Intrinsic*/) const {
501 /// Returns true if the target can instruction select the specified FP
502 /// immediate natively. If false, the legalizer will materialize the FP
503 /// immediate as a load from a constant pool.
504 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
508 /// Targets can use this to indicate that they only support *some*
509 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
510 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
512 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
517 /// Returns true if the operation can trap for the value type.
519 /// VT must be a legal type. By default, we optimistically assume most
520 /// operations don't trap except for divide and remainder.
521 virtual bool canOpTrap(unsigned Op, EVT VT) const;
523 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
524 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
525 /// a VAND with a constant pool entry.
526 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
531 /// Return how this operation should be treated: either it is legal, needs to
532 /// be promoted to a larger size, needs to be expanded to some other code
533 /// sequence, or the target has a custom expander for it.
534 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
535 if (VT.isExtended()) return Expand;
536 // If a target-specific SDNode requires legalization, require the target
537 // to provide custom legalization for it.
538 if (Op > array_lengthof(OpActions[0])) return Custom;
539 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
540 return (LegalizeAction)OpActions[I][Op];
543 /// Return true if the specified operation is legal on this target or can be
544 /// made legal with custom lowering. This is used to help guide high-level
545 /// lowering decisions.
546 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
547 return (VT == MVT::Other || isTypeLegal(VT)) &&
548 (getOperationAction(Op, VT) == Legal ||
549 getOperationAction(Op, VT) == Custom);
552 /// Return true if the specified operation is legal on this target or can be
553 /// made legal using promotion. This is used to help guide high-level lowering
555 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
556 return (VT == MVT::Other || isTypeLegal(VT)) &&
557 (getOperationAction(Op, VT) == Legal ||
558 getOperationAction(Op, VT) == Promote);
561 /// Return true if the specified operation is illegal on this target or
562 /// unlikely to be made legal with custom lowering. This is used to help guide
563 /// high-level lowering decisions.
564 bool isOperationExpand(unsigned Op, EVT VT) const {
565 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
568 /// Return true if the specified operation is legal on this target.
569 bool isOperationLegal(unsigned Op, EVT VT) const {
570 return (VT == MVT::Other || isTypeLegal(VT)) &&
571 getOperationAction(Op, VT) == Legal;
574 /// Return how this load with extension should be treated: either it is legal,
575 /// needs to be promoted to a larger size, needs to be expanded to some other
576 /// code sequence, or the target has a custom expander for it.
577 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
579 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
580 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
581 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
582 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
583 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
584 return (LegalizeAction)LoadExtActions[ValI][MemI][ExtType];
587 /// Return true if the specified load with extension is legal on this target.
588 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
589 return ValVT.isSimple() && MemVT.isSimple() &&
590 getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
593 /// Return true if the specified load with extension is legal or custom
595 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
596 return ValVT.isSimple() && MemVT.isSimple() &&
597 (getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
598 getLoadExtAction(ExtType, ValVT, MemVT) == Custom);
601 /// Return how this store with truncation should be treated: either it is
602 /// legal, needs to be promoted to a larger size, needs to be expanded to some
603 /// other code sequence, or the target has a custom expander for it.
604 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
605 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
606 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
607 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
608 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
609 "Table isn't big enough!");
610 return (LegalizeAction)TruncStoreActions[ValI][MemI];
613 /// Return true if the specified store with truncation is legal on this
615 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
616 return isTypeLegal(ValVT) && MemVT.isSimple() &&
617 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
620 /// Return how the indexed load should be treated: either it is legal, needs
621 /// to be promoted to a larger size, needs to be expanded to some other code
622 /// sequence, or the target has a custom expander for it.
624 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
625 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
626 "Table isn't big enough!");
627 unsigned Ty = (unsigned)VT.SimpleTy;
628 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
631 /// Return true if the specified indexed load is legal on this target.
632 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
633 return VT.isSimple() &&
634 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
635 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
638 /// Return how the indexed store should be treated: either it is legal, needs
639 /// to be promoted to a larger size, needs to be expanded to some other code
640 /// sequence, or the target has a custom expander for it.
642 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
643 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
644 "Table isn't big enough!");
645 unsigned Ty = (unsigned)VT.SimpleTy;
646 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
649 /// Return true if the specified indexed load is legal on this target.
650 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
651 return VT.isSimple() &&
652 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
653 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
656 /// Return how the condition code should be treated: either it is legal, needs
657 /// to be expanded to some other code sequence, or the target has a custom
660 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
661 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
662 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
663 "Table isn't big enough!");
664 // See setCondCodeAction for how this is encoded.
665 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
666 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
667 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
668 assert(Action != Promote && "Can't promote condition code!");
672 /// Return true if the specified condition code is legal on this target.
673 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
675 getCondCodeAction(CC, VT) == Legal ||
676 getCondCodeAction(CC, VT) == Custom;
680 /// If the action for this operation is to promote, this method returns the
681 /// ValueType to promote to.
682 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
683 assert(getOperationAction(Op, VT) == Promote &&
684 "This operation isn't promoted!");
686 // See if this has an explicit type specified.
687 std::map<std::pair<unsigned, MVT::SimpleValueType>,
688 MVT::SimpleValueType>::const_iterator PTTI =
689 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
690 if (PTTI != PromoteToType.end()) return PTTI->second;
692 assert((VT.isInteger() || VT.isFloatingPoint()) &&
693 "Cannot autopromote this type, add it with AddPromotedToType.");
697 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
698 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
699 "Didn't find type to promote to!");
700 } while (!isTypeLegal(NVT) ||
701 getOperationAction(Op, NVT) == Promote);
705 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
706 /// operations except for the pointer size. If AllowUnknown is true, this
707 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
708 /// otherwise it will assert.
709 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
710 // Lower scalar pointers to native pointer types.
711 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
712 return getPointerTy(PTy->getAddressSpace());
714 if (Ty->isVectorTy()) {
715 VectorType *VTy = cast<VectorType>(Ty);
716 Type *Elm = VTy->getElementType();
717 // Lower vectors of pointers to native pointer types.
718 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
719 EVT PointerTy(getPointerTy(PT->getAddressSpace()));
720 Elm = PointerTy.getTypeForEVT(Ty->getContext());
723 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
724 VTy->getNumElements());
726 return EVT::getEVT(Ty, AllowUnknown);
729 /// Return the MVT corresponding to this LLVM type. See getValueType.
730 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
731 return getValueType(Ty, AllowUnknown).getSimpleVT();
734 /// Return the desired alignment for ByVal or InAlloca aggregate function
735 /// arguments in the caller parameter area. This is the actual alignment, not
737 virtual unsigned getByValTypeAlignment(Type *Ty) const;
739 /// Return the type of registers that this ValueType will eventually require.
740 MVT getRegisterType(MVT VT) const {
741 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
742 return RegisterTypeForVT[VT.SimpleTy];
745 /// Return the type of registers that this ValueType will eventually require.
746 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
748 assert((unsigned)VT.getSimpleVT().SimpleTy <
749 array_lengthof(RegisterTypeForVT));
750 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
755 unsigned NumIntermediates;
756 (void)getVectorTypeBreakdown(Context, VT, VT1,
757 NumIntermediates, RegisterVT);
760 if (VT.isInteger()) {
761 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
763 llvm_unreachable("Unsupported extended type!");
766 /// Return the number of registers that this ValueType will eventually
769 /// This is one for any types promoted to live in larger registers, but may be
770 /// more than one for types (like i64) that are split into pieces. For types
771 /// like i140, which are first promoted then expanded, it is the number of
772 /// registers needed to hold all the bits of the original type. For an i140
773 /// on a 32 bit machine this means 5 registers.
774 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
776 assert((unsigned)VT.getSimpleVT().SimpleTy <
777 array_lengthof(NumRegistersForVT));
778 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
783 unsigned NumIntermediates;
784 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
786 if (VT.isInteger()) {
787 unsigned BitWidth = VT.getSizeInBits();
788 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
789 return (BitWidth + RegWidth - 1) / RegWidth;
791 llvm_unreachable("Unsupported extended type!");
794 /// If true, then instruction selection should seek to shrink the FP constant
795 /// of the specified type to a smaller type in order to save space and / or
797 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
799 // Return true if it is profitable to reduce the given load node to a smaller
802 // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
803 virtual bool shouldReduceLoadWidth(SDNode *Load,
804 ISD::LoadExtType ExtTy,
809 /// When splitting a value of the specified type into parts, does the Lo
810 /// or Hi part come first? This usually follows the endianness, except
811 /// for ppcf128, where the Hi part always comes first.
812 bool hasBigEndianPartOrdering(EVT VT) const {
813 return isBigEndian() || VT == MVT::ppcf128;
816 /// If true, the target has custom DAG combine transformations that it can
817 /// perform for the specified node.
818 bool hasTargetDAGCombine(ISD::NodeType NT) const {
819 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
820 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
823 /// \brief Get maximum # of store operations permitted for llvm.memset
825 /// This function returns the maximum number of store operations permitted
826 /// to replace a call to llvm.memset. The value is set by the target at the
827 /// performance threshold for such a replacement. If OptSize is true,
828 /// return the limit for functions that have OptSize attribute.
829 unsigned getMaxStoresPerMemset(bool OptSize) const {
830 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
833 /// \brief Get maximum # of store operations permitted for llvm.memcpy
835 /// This function returns the maximum number of store operations permitted
836 /// to replace a call to llvm.memcpy. The value is set by the target at the
837 /// performance threshold for such a replacement. If OptSize is true,
838 /// return the limit for functions that have OptSize attribute.
839 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
840 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
843 /// \brief Get maximum # of store operations permitted for llvm.memmove
845 /// This function returns the maximum number of store operations permitted
846 /// to replace a call to llvm.memmove. The value is set by the target at the
847 /// performance threshold for such a replacement. If OptSize is true,
848 /// return the limit for functions that have OptSize attribute.
849 unsigned getMaxStoresPerMemmove(bool OptSize) const {
850 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
853 /// \brief Determine if the target supports unaligned memory accesses.
855 /// This function returns true if the target allows unaligned memory accesses
856 /// of the specified type in the given address space. If true, it also returns
857 /// whether the unaligned memory access is "fast" in the last argument by
858 /// reference. This is used, for example, in situations where an array
859 /// copy/move/set is converted to a sequence of store operations. Its use
860 /// helps to ensure that such replacements don't generate code that causes an
861 /// alignment error (trap) on the target machine.
862 virtual bool allowsMisalignedMemoryAccesses(EVT,
863 unsigned AddrSpace = 0,
865 bool * /*Fast*/ = nullptr) const {
869 /// Returns the target specific optimal type for load and store operations as
870 /// a result of memset, memcpy, and memmove lowering.
872 /// If DstAlign is zero that means it's safe to destination alignment can
873 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
874 /// a need to check it against alignment requirement, probably because the
875 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
876 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
877 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
878 /// does not need to be loaded. It returns EVT::Other if the type should be
879 /// determined using generic target-independent logic.
880 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
881 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
884 bool /*MemcpyStrSrc*/,
885 MachineFunction &/*MF*/) const {
889 /// Returns true if it's safe to use load / store of the specified type to
890 /// expand memcpy / memset inline.
892 /// This is mostly true for all types except for some special cases. For
893 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
894 /// fstpl which also does type conversion. Note the specified type doesn't
895 /// have to be legal as the hook is used before type legalization.
896 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
898 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
899 bool usesUnderscoreSetJmp() const {
900 return UseUnderscoreSetJmp;
903 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
904 bool usesUnderscoreLongJmp() const {
905 return UseUnderscoreLongJmp;
908 /// Return integer threshold on number of blocks to use jump tables rather
909 /// than if sequence.
910 int getMinimumJumpTableEntries() const {
911 return MinimumJumpTableEntries;
914 /// If a physical register, this specifies the register that
915 /// llvm.savestack/llvm.restorestack should save and restore.
916 unsigned getStackPointerRegisterToSaveRestore() const {
917 return StackPointerRegisterToSaveRestore;
920 /// If a physical register, this returns the register that receives the
921 /// exception address on entry to a landing pad.
922 unsigned getExceptionPointerRegister() const {
923 return ExceptionPointerRegister;
926 /// If a physical register, this returns the register that receives the
927 /// exception typeid on entry to a landing pad.
928 unsigned getExceptionSelectorRegister() const {
929 return ExceptionSelectorRegister;
932 /// Returns the target's jmp_buf size in bytes (if never set, the default is
934 unsigned getJumpBufSize() const {
938 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
940 unsigned getJumpBufAlignment() const {
941 return JumpBufAlignment;
944 /// Return the minimum stack alignment of an argument.
945 unsigned getMinStackArgumentAlignment() const {
946 return MinStackArgumentAlignment;
949 /// Return the minimum function alignment.
950 unsigned getMinFunctionAlignment() const {
951 return MinFunctionAlignment;
954 /// Return the preferred function alignment.
955 unsigned getPrefFunctionAlignment() const {
956 return PrefFunctionAlignment;
959 /// Return the preferred loop alignment.
960 virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
961 return PrefLoopAlignment;
964 /// Return whether the DAG builder should automatically insert fences and
965 /// reduce ordering for atomics.
966 bool getInsertFencesForAtomic() const {
967 return InsertFencesForAtomic;
970 /// Return true if the target stores stack protector cookies at a fixed offset
971 /// in some non-standard address space, and populates the address space and
972 /// offset as appropriate.
973 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
974 unsigned &/*Offset*/) const {
978 /// Returns true if a cast between SrcAS and DestAS is a noop.
979 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
983 /// Return true if the pointer arguments to CI should be aligned by aligning
984 /// the object whose address is being passed. If so then MinSize is set to the
985 /// minimum size the object must be to be aligned and PrefAlign is set to the
986 /// preferred alignment.
987 virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
988 unsigned & /*PrefAlign*/) const {
992 //===--------------------------------------------------------------------===//
993 /// \name Helpers for TargetTransformInfo implementations
996 /// Get the ISD node that corresponds to the Instruction class opcode.
997 int InstructionOpcodeToISD(unsigned Opcode) const;
999 /// Estimate the cost of type-legalization and the legalized type.
1000 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
1004 //===--------------------------------------------------------------------===//
1005 /// \name Helpers for atomic expansion.
1008 /// True if AtomicExpandPass should use emitLoadLinked/emitStoreConditional
1009 /// and expand AtomicCmpXchgInst.
1010 virtual bool hasLoadLinkedStoreConditional() const { return false; }
1012 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1013 /// corresponding pointee type. This may entail some non-trivial operations to
1014 /// truncate or reconstruct types that will be illegal in the backend. See
1015 /// ARMISelLowering for an example implementation.
1016 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1017 AtomicOrdering Ord) const {
1018 llvm_unreachable("Load linked unimplemented on this target");
1021 /// Perform a store-conditional operation to Addr. Return the status of the
1022 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1023 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1024 Value *Addr, AtomicOrdering Ord) const {
1025 llvm_unreachable("Store conditional unimplemented on this target");
1028 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1029 /// It is called by AtomicExpandPass before expanding an
1030 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
1031 /// RMW and CmpXchg set both IsStore and IsLoad to true.
1032 /// This function should either return a nullptr, or a pointer to an IR-level
1033 /// Instruction*. Even complex fence sequences can be represented by a
1034 /// single Instruction* through an intrinsic to be lowered later.
1035 /// Backends with !getInsertFencesForAtomic() should keep a no-op here.
1036 /// Backends should override this method to produce target-specific intrinsic
1037 /// for their fences.
1038 /// FIXME: Please note that the default implementation here in terms of
1039 /// IR-level fences exists for historical/compatibility reasons and is
1040 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1041 /// consistency. For example, consider the following example:
1042 /// atomic<int> x = y = 0;
1043 /// int r1, r2, r3, r4;
1054 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1055 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1056 /// IR-level fences can prevent it.
1058 virtual Instruction *emitLeadingFence(IRBuilder<> &Builder,
1059 AtomicOrdering Ord, bool IsStore,
1060 bool IsLoad) const {
1061 if (!getInsertFencesForAtomic())
1064 if (isAtLeastRelease(Ord) && IsStore)
1065 return Builder.CreateFence(Ord);
1070 virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1071 AtomicOrdering Ord, bool IsStore,
1072 bool IsLoad) const {
1073 if (!getInsertFencesForAtomic())
1076 if (isAtLeastAcquire(Ord))
1077 return Builder.CreateFence(Ord);
1083 /// Returns true if the given (atomic) store should be expanded by the
1084 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1085 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1089 /// Returns true if arguments should be sign-extended in lib calls.
1090 virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1094 /// Returns true if the given (atomic) load should be expanded by the
1095 /// IR-level AtomicExpand pass into a load-linked instruction
1096 /// (through emitLoadLinked()).
1097 virtual bool shouldExpandAtomicLoadInIR(LoadInst *LI) const { return false; }
1099 /// Returns how the IR-level AtomicExpand pass should expand the given
1100 /// AtomicRMW, if at all. Default is to never expand.
1101 virtual AtomicRMWExpansionKind
1102 shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1103 return AtomicRMWExpansionKind::None;
1106 /// On some platforms, an AtomicRMW that never actually modifies the value
1107 /// (such as fetch_add of 0) can be turned into a fence followed by an
1108 /// atomic load. This may sound useless, but it makes it possible for the
1109 /// processor to keep the cacheline shared, dramatically improving
1110 /// performance. And such idempotent RMWs are useful for implementing some
1111 /// kinds of locks, see for example (justification + benchmarks):
1112 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1113 /// This method tries doing that transformation, returning the atomic load if
1114 /// it succeeds, and nullptr otherwise.
1115 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1116 /// another round of expansion.
1118 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1122 /// Returns true if we should normalize
1123 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1124 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1125 /// that it saves us from materializing N0 and N1 in an integer register.
1126 /// Targets that are able to perform and/or on flags should return false here.
1127 virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1129 // If a target has multiple condition registers, then it likely has logical
1130 // operations on those registers.
1131 if (hasMultipleConditionRegisters())
1133 // Only do the transform if the value won't be split into multiple
1135 LegalizeTypeAction Action = getTypeAction(Context, VT);
1136 return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1137 Action != TypeSplitVector;
1140 //===--------------------------------------------------------------------===//
1141 // TargetLowering Configuration Methods - These methods should be invoked by
1142 // the derived class constructor to configure this object for the target.
1145 /// Specify how the target extends the result of integer and floating point
1146 /// boolean values from i1 to a wider type. See getBooleanContents.
1147 void setBooleanContents(BooleanContent Ty) {
1148 BooleanContents = Ty;
1149 BooleanFloatContents = Ty;
1152 /// Specify how the target extends the result of integer and floating point
1153 /// boolean values from i1 to a wider type. See getBooleanContents.
1154 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1155 BooleanContents = IntTy;
1156 BooleanFloatContents = FloatTy;
1159 /// Specify how the target extends the result of a vector boolean value from a
1160 /// vector of i1 to a wider type. See getBooleanContents.
1161 void setBooleanVectorContents(BooleanContent Ty) {
1162 BooleanVectorContents = Ty;
1165 /// Specify the target scheduling preference.
1166 void setSchedulingPreference(Sched::Preference Pref) {
1167 SchedPreferenceInfo = Pref;
1170 /// Indicate whether this target prefers to use _setjmp to implement
1171 /// llvm.setjmp or the version without _. Defaults to false.
1172 void setUseUnderscoreSetJmp(bool Val) {
1173 UseUnderscoreSetJmp = Val;
1176 /// Indicate whether this target prefers to use _longjmp to implement
1177 /// llvm.longjmp or the version without _. Defaults to false.
1178 void setUseUnderscoreLongJmp(bool Val) {
1179 UseUnderscoreLongJmp = Val;
1182 /// Indicate the number of blocks to generate jump tables rather than if
1184 void setMinimumJumpTableEntries(int Val) {
1185 MinimumJumpTableEntries = Val;
1188 /// If set to a physical register, this specifies the register that
1189 /// llvm.savestack/llvm.restorestack should save and restore.
1190 void setStackPointerRegisterToSaveRestore(unsigned R) {
1191 StackPointerRegisterToSaveRestore = R;
1194 /// If set to a physical register, this sets the register that receives the
1195 /// exception address on entry to a landing pad.
1196 void setExceptionPointerRegister(unsigned R) {
1197 ExceptionPointerRegister = R;
1200 /// If set to a physical register, this sets the register that receives the
1201 /// exception typeid on entry to a landing pad.
1202 void setExceptionSelectorRegister(unsigned R) {
1203 ExceptionSelectorRegister = R;
1206 /// Tells the code generator not to expand operations into sequences that use
1207 /// the select operations if possible.
1208 void setSelectIsExpensive(bool isExpensive = true) {
1209 SelectIsExpensive = isExpensive;
1212 /// Tells the code generator that the target has multiple (allocatable)
1213 /// condition registers that can be used to store the results of comparisons
1214 /// for use by selects and conditional branches. With multiple condition
1215 /// registers, the code generator will not aggressively sink comparisons into
1216 /// the blocks of their users.
1217 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1218 HasMultipleConditionRegisters = hasManyRegs;
1221 /// Tells the code generator that the target has BitExtract instructions.
1222 /// The code generator will aggressively sink "shift"s into the blocks of
1223 /// their users if the users will generate "and" instructions which can be
1224 /// combined with "shift" to BitExtract instructions.
1225 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1226 HasExtractBitsInsn = hasExtractInsn;
1229 /// Tells the code generator not to expand sequence of operations into a
1230 /// separate sequences that increases the amount of flow control.
1231 void setJumpIsExpensive(bool isExpensive = true) {
1232 JumpIsExpensive = isExpensive;
1235 /// Tells the code generator that integer divide is expensive, and if
1236 /// possible, should be replaced by an alternate sequence of instructions not
1237 /// containing an integer divide.
1238 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
1240 /// Tells the code generator that fsqrt is cheap, and should not be replaced
1241 /// with an alternative sequence of instructions.
1242 void setFsqrtIsCheap(bool isCheap = true) { FsqrtIsCheap = isCheap; }
1244 /// Tells the code generator that this target supports floating point
1245 /// exceptions and cares about preserving floating point exception behavior.
1246 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1247 HasFloatingPointExceptions = FPExceptions;
1250 /// Tells the code generator which bitwidths to bypass.
1251 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1252 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1255 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1256 /// signed divide by power of two; let the target handle it.
1257 void setPow2SDivIsCheap(bool isCheap = true) { Pow2SDivIsCheap = isCheap; }
1259 /// Add the specified register class as an available regclass for the
1260 /// specified value type. This indicates the selector can handle values of
1261 /// that class natively.
1262 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1263 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1264 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1265 RegClassForVT[VT.SimpleTy] = RC;
1268 /// Remove all register classes.
1269 void clearRegisterClasses() {
1270 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1272 AvailableRegClasses.clear();
1275 /// \brief Remove all operation actions.
1276 void clearOperationActions() {
1279 /// Return the largest legal super-reg register class of the register class
1280 /// for the specified type and its associated "cost".
1281 virtual std::pair<const TargetRegisterClass *, uint8_t>
1282 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1284 /// Once all of the register classes are added, this allows us to compute
1285 /// derived properties we expose.
1286 void computeRegisterProperties(const TargetRegisterInfo *TRI);
1288 /// Indicate that the specified operation does not work with the specified
1289 /// type and indicate what to do about it.
1290 void setOperationAction(unsigned Op, MVT VT,
1291 LegalizeAction Action) {
1292 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1293 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1296 /// Indicate that the specified load with extension does not work with the
1297 /// specified type and indicate what to do about it.
1298 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1299 LegalizeAction Action) {
1300 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1301 MemVT.isValid() && "Table isn't big enough!");
1302 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy][ExtType] = (uint8_t)Action;
1305 /// Indicate that the specified truncating store does not work with the
1306 /// specified type and indicate what to do about it.
1307 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1308 LegalizeAction Action) {
1309 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1310 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1313 /// Indicate that the specified indexed load does or does not work with the
1314 /// specified type and indicate what to do abort it.
1316 /// NOTE: All indexed mode loads are initialized to Expand in
1317 /// TargetLowering.cpp
1318 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1319 LegalizeAction Action) {
1320 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1321 (unsigned)Action < 0xf && "Table isn't big enough!");
1322 // Load action are kept in the upper half.
1323 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1324 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1327 /// Indicate that the specified indexed store does or does not work with the
1328 /// specified type and indicate what to do about it.
1330 /// NOTE: All indexed mode stores are initialized to Expand in
1331 /// TargetLowering.cpp
1332 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1333 LegalizeAction Action) {
1334 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1335 (unsigned)Action < 0xf && "Table isn't big enough!");
1336 // Store action are kept in the lower half.
1337 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1338 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1341 /// Indicate that the specified condition code is or isn't supported on the
1342 /// target and indicate what to do about it.
1343 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1344 LegalizeAction Action) {
1345 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1346 "Table isn't big enough!");
1347 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1348 /// value and the upper 27 bits index into the second dimension of the array
1349 /// to select what 32-bit value to use.
1350 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1351 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1352 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1355 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1356 /// to trying a larger integer/fp until it can find one that works. If that
1357 /// default is insufficient, this method can be used by the target to override
1359 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1360 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1363 /// Targets should invoke this method for each target independent node that
1364 /// they want to provide a custom DAG combiner for by implementing the
1365 /// PerformDAGCombine virtual method.
1366 void setTargetDAGCombine(ISD::NodeType NT) {
1367 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1368 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1371 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1372 void setJumpBufSize(unsigned Size) {
1376 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1378 void setJumpBufAlignment(unsigned Align) {
1379 JumpBufAlignment = Align;
1382 /// Set the target's minimum function alignment (in log2(bytes))
1383 void setMinFunctionAlignment(unsigned Align) {
1384 MinFunctionAlignment = Align;
1387 /// Set the target's preferred function alignment. This should be set if
1388 /// there is a performance benefit to higher-than-minimum alignment (in
1390 void setPrefFunctionAlignment(unsigned Align) {
1391 PrefFunctionAlignment = Align;
1394 /// Set the target's preferred loop alignment. Default alignment is zero, it
1395 /// means the target does not care about loop alignment. The alignment is
1396 /// specified in log2(bytes). The target may also override
1397 /// getPrefLoopAlignment to provide per-loop values.
1398 void setPrefLoopAlignment(unsigned Align) {
1399 PrefLoopAlignment = Align;
1402 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1403 void setMinStackArgumentAlignment(unsigned Align) {
1404 MinStackArgumentAlignment = Align;
1407 /// Set if the DAG builder should automatically insert fences and reduce the
1408 /// order of atomic memory operations to Monotonic.
1409 void setInsertFencesForAtomic(bool fence) {
1410 InsertFencesForAtomic = fence;
1414 //===--------------------------------------------------------------------===//
1415 // Addressing mode description hooks (used by LSR etc).
1418 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1419 /// instructions reading the address. This allows as much computation as
1420 /// possible to be done in the address mode for that operand. This hook lets
1421 /// targets also pass back when this should be done on intrinsics which
1423 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1424 SmallVectorImpl<Value*> &/*Ops*/,
1425 Type *&/*AccessTy*/) const {
1429 /// This represents an addressing mode of:
1430 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1431 /// If BaseGV is null, there is no BaseGV.
1432 /// If BaseOffs is zero, there is no base offset.
1433 /// If HasBaseReg is false, there is no base register.
1434 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1437 GlobalValue *BaseGV;
1441 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1444 /// Return true if the addressing mode represented by AM is legal for this
1445 /// target, for a load/store of the specified type.
1447 /// The type may be VoidTy, in which case only return true if the addressing
1448 /// mode is legal for a load/store of any legal type. TODO: Handle
1449 /// pre/postinc as well.
1450 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1452 /// \brief Return the cost of the scaling factor used in the addressing mode
1453 /// represented by AM for this target, for a load/store of the specified type.
1455 /// If the AM is supported, the return value must be >= 0.
1456 /// If the AM is not supported, it returns a negative value.
1457 /// TODO: Handle pre/postinc as well.
1458 virtual int getScalingFactorCost(const AddrMode &AM, Type *Ty) const {
1459 // Default: assume that any scaling factor used in a legal AM is free.
1460 if (isLegalAddressingMode(AM, Ty)) return 0;
1464 /// Return true if the specified immediate is legal icmp immediate, that is
1465 /// the target has icmp instructions which can compare a register against the
1466 /// immediate without having to materialize the immediate into a register.
1467 virtual bool isLegalICmpImmediate(int64_t) const {
1471 /// Return true if the specified immediate is legal add immediate, that is the
1472 /// target has add instructions which can add a register with the immediate
1473 /// without having to materialize the immediate into a register.
1474 virtual bool isLegalAddImmediate(int64_t) const {
1478 /// Return true if it's significantly cheaper to shift a vector by a uniform
1479 /// scalar than by an amount which will vary across each lane. On x86, for
1480 /// example, there is a "psllw" instruction for the former case, but no simple
1481 /// instruction for a general "a << b" operation on vectors.
1482 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1486 /// Return true if it's free to truncate a value of type Ty1 to type
1487 /// Ty2. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1488 /// by referencing its sub-register AX.
1489 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1493 /// Return true if a truncation from Ty1 to Ty2 is permitted when deciding
1494 /// whether a call is in tail position. Typically this means that both results
1495 /// would be assigned to the same register or stack slot, but it could mean
1496 /// the target performs adequate checks of its own before proceeding with the
1498 virtual bool allowTruncateForTailCall(Type * /*Ty1*/, Type * /*Ty2*/) const {
1502 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1506 virtual bool isProfitableToHoist(Instruction *I) const { return true; }
1508 /// Return true if the extension represented by \p I is free.
1509 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
1510 /// this method can use the context provided by \p I to decide
1511 /// whether or not \p I is free.
1512 /// This method extends the behavior of the is[Z|FP]ExtFree family.
1513 /// In other words, if is[Z|FP]Free returns true, then this method
1514 /// returns true as well. The converse is not true.
1515 /// The target can perform the adequate checks by overriding isExtFreeImpl.
1516 /// \pre \p I must be a sign, zero, or fp extension.
1517 bool isExtFree(const Instruction *I) const {
1518 switch (I->getOpcode()) {
1519 case Instruction::FPExt:
1520 if (isFPExtFree(EVT::getEVT(I->getType())))
1523 case Instruction::ZExt:
1524 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
1527 case Instruction::SExt:
1530 llvm_unreachable("Instruction is not an extension");
1532 return isExtFreeImpl(I);
1535 /// Return true if any actual instruction that defines a value of type Ty1
1536 /// implicitly zero-extends the value to Ty2 in the result register.
1538 /// This does not necessarily include registers defined in unknown ways, such
1539 /// as incoming arguments, or copies from unknown virtual registers. Also, if
1540 /// isTruncateFree(Ty2, Ty1) is true, this does not necessarily apply to
1541 /// truncate instructions. e.g. on x86-64, all instructions that define 32-bit
1542 /// values implicit zero-extend the result out to 64 bits.
1543 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1547 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1551 /// Return true if the target supplies and combines to a paired load
1552 /// two loaded values of type LoadedType next to each other in memory.
1553 /// RequiredAlignment gives the minimal alignment constraints that must be met
1554 /// to be able to select this paired load.
1556 /// This information is *not* used to generate actual paired loads, but it is
1557 /// used to generate a sequence of loads that is easier to combine into a
1559 /// For instance, something like this:
1560 /// a = load i64* addr
1561 /// b = trunc i64 a to i32
1562 /// c = lshr i64 a, 32
1563 /// d = trunc i64 c to i32
1564 /// will be optimized into:
1565 /// b = load i32* addr1
1566 /// d = load i32* addr2
1567 /// Where addr1 = addr2 +/- sizeof(i32).
1569 /// In other words, unless the target performs a post-isel load combining,
1570 /// this information should not be provided because it will generate more
1572 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1573 unsigned & /*RequiredAligment*/) const {
1577 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1578 unsigned & /*RequiredAligment*/) const {
1582 /// Return true if zero-extending the specific node Val to type VT2 is free
1583 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1584 /// because it's folded such as X86 zero-extending loads).
1585 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1586 return isZExtFree(Val.getValueType(), VT2);
1589 /// Return true if an fpext operation is free (for instance, because
1590 /// single-precision floating-point numbers are implicitly extended to
1591 /// double-precision).
1592 virtual bool isFPExtFree(EVT VT) const {
1593 assert(VT.isFloatingPoint());
1597 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
1598 /// extend node) is profitable.
1599 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
1601 /// Return true if an fneg operation is free to the point where it is never
1602 /// worthwhile to replace it with a bitwise operation.
1603 virtual bool isFNegFree(EVT VT) const {
1604 assert(VT.isFloatingPoint());
1608 /// Return true if an fabs operation is free to the point where it is never
1609 /// worthwhile to replace it with a bitwise operation.
1610 virtual bool isFAbsFree(EVT VT) const {
1611 assert(VT.isFloatingPoint());
1615 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1616 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1617 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1619 /// NOTE: This may be called before legalization on types for which FMAs are
1620 /// not legal, but should return true if those types will eventually legalize
1621 /// to types that support FMAs. After legalization, it will only be called on
1622 /// types that support FMAs (via Legal or Custom actions)
1623 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1627 /// Return true if it's profitable to narrow operations of type VT1 to
1628 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1630 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1634 /// \brief Return true if it is beneficial to convert a load of a constant to
1635 /// just the constant itself.
1636 /// On some targets it might be more efficient to use a combination of
1637 /// arithmetic instructions to materialize the constant instead of loading it
1638 /// from a constant pool.
1639 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1644 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1645 /// with this index. This is needed because EXTRACT_SUBVECTOR usually
1646 /// has custom lowering that depends on the index of the first element,
1647 /// and only the target knows which lowering is cheap.
1648 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const {
1652 //===--------------------------------------------------------------------===//
1653 // Runtime Library hooks
1656 /// Rename the default libcall routine name for the specified libcall.
1657 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1658 LibcallRoutineNames[Call] = Name;
1661 /// Get the libcall routine name for the specified libcall.
1662 const char *getLibcallName(RTLIB::Libcall Call) const {
1663 return LibcallRoutineNames[Call];
1666 /// Override the default CondCode to be used to test the result of the
1667 /// comparison libcall against zero.
1668 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1669 CmpLibcallCCs[Call] = CC;
1672 /// Get the CondCode that's to be used to test the result of the comparison
1673 /// libcall against zero.
1674 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1675 return CmpLibcallCCs[Call];
1678 /// Set the CallingConv that should be used for the specified libcall.
1679 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1680 LibcallCallingConvs[Call] = CC;
1683 /// Get the CallingConv that should be used for the specified libcall.
1684 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1685 return LibcallCallingConvs[Call];
1689 const TargetMachine &TM;
1691 /// True if this is a little endian target.
1692 bool IsLittleEndian;
1694 /// Tells the code generator not to expand operations into sequences that use
1695 /// the select operations if possible.
1696 bool SelectIsExpensive;
1698 /// Tells the code generator that the target has multiple (allocatable)
1699 /// condition registers that can be used to store the results of comparisons
1700 /// for use by selects and conditional branches. With multiple condition
1701 /// registers, the code generator will not aggressively sink comparisons into
1702 /// the blocks of their users.
1703 bool HasMultipleConditionRegisters;
1705 /// Tells the code generator that the target has BitExtract instructions.
1706 /// The code generator will aggressively sink "shift"s into the blocks of
1707 /// their users if the users will generate "and" instructions which can be
1708 /// combined with "shift" to BitExtract instructions.
1709 bool HasExtractBitsInsn;
1711 /// Tells the code generator not to expand integer divides by constants into a
1712 /// sequence of muls, adds, and shifts. This is a hack until a real cost
1713 /// model is in place. If we ever optimize for size, this will be set to true
1714 /// unconditionally.
1717 // Don't expand fsqrt with an approximation based on the inverse sqrt.
1720 /// Tells the code generator to bypass slow divide or remainder
1721 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1722 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1723 /// div/rem when the operands are positive and less than 256.
1724 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1726 /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a
1727 /// signed divide by power of two; let the target handle it.
1728 bool Pow2SDivIsCheap;
1730 /// Tells the code generator that it shouldn't generate extra flow control
1731 /// instructions and should attempt to combine flow control instructions via
1733 bool JumpIsExpensive;
1735 /// Whether the target supports or cares about preserving floating point
1736 /// exception behavior.
1737 bool HasFloatingPointExceptions;
1739 /// This target prefers to use _setjmp to implement llvm.setjmp.
1741 /// Defaults to false.
1742 bool UseUnderscoreSetJmp;
1744 /// This target prefers to use _longjmp to implement llvm.longjmp.
1746 /// Defaults to false.
1747 bool UseUnderscoreLongJmp;
1749 /// Number of blocks threshold to use jump tables.
1750 int MinimumJumpTableEntries;
1752 /// Information about the contents of the high-bits in boolean values held in
1753 /// a type wider than i1. See getBooleanContents.
1754 BooleanContent BooleanContents;
1756 /// Information about the contents of the high-bits in boolean values held in
1757 /// a type wider than i1. See getBooleanContents.
1758 BooleanContent BooleanFloatContents;
1760 /// Information about the contents of the high-bits in boolean vector values
1761 /// when the element type is wider than i1. See getBooleanContents.
1762 BooleanContent BooleanVectorContents;
1764 /// The target scheduling preference: shortest possible total cycles or lowest
1766 Sched::Preference SchedPreferenceInfo;
1768 /// The size, in bytes, of the target's jmp_buf buffers
1769 unsigned JumpBufSize;
1771 /// The alignment, in bytes, of the target's jmp_buf buffers
1772 unsigned JumpBufAlignment;
1774 /// The minimum alignment that any argument on the stack needs to have.
1775 unsigned MinStackArgumentAlignment;
1777 /// The minimum function alignment (used when optimizing for size, and to
1778 /// prevent explicitly provided alignment from leading to incorrect code).
1779 unsigned MinFunctionAlignment;
1781 /// The preferred function alignment (used when alignment unspecified and
1782 /// optimizing for speed).
1783 unsigned PrefFunctionAlignment;
1785 /// The preferred loop alignment.
1786 unsigned PrefLoopAlignment;
1788 /// Whether the DAG builder should automatically insert fences and reduce
1789 /// ordering for atomics. (This will be set for for most architectures with
1790 /// weak memory ordering.)
1791 bool InsertFencesForAtomic;
1793 /// If set to a physical register, this specifies the register that
1794 /// llvm.savestack/llvm.restorestack should save and restore.
1795 unsigned StackPointerRegisterToSaveRestore;
1797 /// If set to a physical register, this specifies the register that receives
1798 /// the exception address on entry to a landing pad.
1799 unsigned ExceptionPointerRegister;
1801 /// If set to a physical register, this specifies the register that receives
1802 /// the exception typeid on entry to a landing pad.
1803 unsigned ExceptionSelectorRegister;
1805 /// This indicates the default register class to use for each ValueType the
1806 /// target supports natively.
1807 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1808 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1809 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1811 /// This indicates the "representative" register class to use for each
1812 /// ValueType the target supports natively. This information is used by the
1813 /// scheduler to track register pressure. By default, the representative
1814 /// register class is the largest legal super-reg register class of the
1815 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1816 /// representative class would be GR32.
1817 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1819 /// This indicates the "cost" of the "representative" register class for each
1820 /// ValueType. The cost is used by the scheduler to approximate register
1822 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1824 /// For any value types we are promoting or expanding, this contains the value
1825 /// type that we are changing to. For Expanded types, this contains one step
1826 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1827 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1828 /// the same type (e.g. i32 -> i32).
1829 MVT TransformToType[MVT::LAST_VALUETYPE];
1831 /// For each operation and each value type, keep a LegalizeAction that
1832 /// indicates how instruction selection should deal with the operation. Most
1833 /// operations are Legal (aka, supported natively by the target), but
1834 /// operations that are not should be described. Note that operations on
1835 /// non-legal value types are not described here.
1836 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1838 /// For each load extension type and each value type, keep a LegalizeAction
1839 /// that indicates how instruction selection should deal with a load of a
1840 /// specific value type and extension type.
1841 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
1842 [ISD::LAST_LOADEXT_TYPE];
1844 /// For each value type pair keep a LegalizeAction that indicates whether a
1845 /// truncating store of a specific value type and truncating type is legal.
1846 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1848 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1849 /// that indicates how instruction selection should deal with the load /
1852 /// The first dimension is the value_type for the reference. The second
1853 /// dimension represents the various modes for load store.
1854 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1856 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1857 /// indicates how instruction selection should deal with the condition code.
1859 /// Because each CC action takes up 2 bits, we need to have the array size be
1860 /// large enough to fit all of the value types. This can be done by rounding
1861 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1862 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1864 ValueTypeActionImpl ValueTypeActions;
1867 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
1870 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1872 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1873 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1876 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1878 /// For operations that must be promoted to a specific type, this holds the
1879 /// destination type. This map should be sparse, so don't hold it as an
1882 /// Targets add entries to this map with AddPromotedToType(..), clients access
1883 /// this with getTypeToPromoteTo(..).
1884 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1887 /// Stores the name each libcall.
1888 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1890 /// The ISD::CondCode that should be used to test the result of each of the
1891 /// comparison libcall against zero.
1892 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1894 /// Stores the CallingConv that should be used for each libcall.
1895 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1898 /// Return true if the extension represented by \p I is free.
1899 /// \pre \p I is a sign, zero, or fp extension and
1900 /// is[Z|FP]ExtFree of the related types is not true.
1901 virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
1903 /// \brief Specify maximum number of store instructions per memset call.
1905 /// When lowering \@llvm.memset this field specifies the maximum number of
1906 /// store operations that may be substituted for the call to memset. Targets
1907 /// must set this value based on the cost threshold for that target. Targets
1908 /// should assume that the memset will be done using as many of the largest
1909 /// store operations first, followed by smaller ones, if necessary, per
1910 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1911 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1912 /// store. This only applies to setting a constant array of a constant size.
1913 unsigned MaxStoresPerMemset;
1915 /// Maximum number of stores operations that may be substituted for the call
1916 /// to memset, used for functions with OptSize attribute.
1917 unsigned MaxStoresPerMemsetOptSize;
1919 /// \brief Specify maximum bytes of store instructions per memcpy call.
1921 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1922 /// store operations that may be substituted for a call to memcpy. Targets
1923 /// must set this value based on the cost threshold for that target. Targets
1924 /// should assume that the memcpy will be done using as many of the largest
1925 /// store operations first, followed by smaller ones, if necessary, per
1926 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1927 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1928 /// and one 1-byte store. This only applies to copying a constant array of
1930 unsigned MaxStoresPerMemcpy;
1932 /// Maximum number of store operations that may be substituted for a call to
1933 /// memcpy, used for functions with OptSize attribute.
1934 unsigned MaxStoresPerMemcpyOptSize;
1936 /// \brief Specify maximum bytes of store instructions per memmove call.
1938 /// When lowering \@llvm.memmove this field specifies the maximum number of
1939 /// store instructions that may be substituted for a call to memmove. Targets
1940 /// must set this value based on the cost threshold for that target. Targets
1941 /// should assume that the memmove will be done using as many of the largest
1942 /// store operations first, followed by smaller ones, if necessary, per
1943 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1944 /// with 8-bit alignment would result in nine 1-byte stores. This only
1945 /// applies to copying a constant array of constant size.
1946 unsigned MaxStoresPerMemmove;
1948 /// Maximum number of store instructions that may be substituted for a call to
1949 /// memmove, used for functions with OpSize attribute.
1950 unsigned MaxStoresPerMemmoveOptSize;
1952 /// Tells the code generator that select is more expensive than a branch if
1953 /// the branch is usually predicted right.
1954 bool PredictableSelectIsExpensive;
1956 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
1957 /// a mask of a single bit, a compare, and a branch into a single instruction.
1958 bool MaskAndBranchFoldingIsLegal;
1960 /// \see enableExtLdPromotion.
1961 bool EnableExtLdPromotion;
1964 /// Return true if the value types that can be represented by the specified
1965 /// register class are all legal.
1966 bool isLegalRC(const TargetRegisterClass *RC) const;
1968 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
1969 /// sequence of memory operands that is recognized by PrologEpilogInserter.
1970 MachineBasicBlock *emitPatchPoint(MachineInstr *MI,
1971 MachineBasicBlock *MBB) const;
1974 /// This class defines information used to lower LLVM code to legal SelectionDAG
1975 /// operators that the target instruction selector can accept natively.
1977 /// This class also defines callbacks that targets must implement to lower
1978 /// target-specific constructs to SelectionDAG operators.
1979 class TargetLowering : public TargetLoweringBase {
1980 TargetLowering(const TargetLowering&) = delete;
1981 void operator=(const TargetLowering&) = delete;
1984 /// NOTE: The TargetMachine owns TLOF.
1985 explicit TargetLowering(const TargetMachine &TM);
1987 /// Returns true by value, base pointer and offset pointer and addressing mode
1988 /// by reference if the node's address can be legally represented as
1989 /// pre-indexed load / store address.
1990 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
1991 SDValue &/*Offset*/,
1992 ISD::MemIndexedMode &/*AM*/,
1993 SelectionDAG &/*DAG*/) const {
1997 /// Returns true by value, base pointer and offset pointer and addressing mode
1998 /// by reference if this node can be combined with a load / store to form a
1999 /// post-indexed load / store.
2000 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2002 SDValue &/*Offset*/,
2003 ISD::MemIndexedMode &/*AM*/,
2004 SelectionDAG &/*DAG*/) const {
2008 /// Return the entry encoding for a jump table in the current function. The
2009 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2010 virtual unsigned getJumpTableEncoding() const;
2012 virtual const MCExpr *
2013 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2014 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2015 MCContext &/*Ctx*/) const {
2016 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2019 /// Returns relocation base for the given PIC jumptable.
2020 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2021 SelectionDAG &DAG) const;
2023 /// This returns the relocation base for the given PIC jumptable, the same as
2024 /// getPICJumpTableRelocBase, but as an MCExpr.
2025 virtual const MCExpr *
2026 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2027 unsigned JTI, MCContext &Ctx) const;
2029 /// Return true if folding a constant offset with the given GlobalAddress is
2030 /// legal. It is frequently not legal in PIC relocation models.
2031 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2033 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2034 SDValue &Chain) const;
2036 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
2037 SDValue &NewLHS, SDValue &NewRHS,
2038 ISD::CondCode &CCCode, SDLoc DL) const;
2040 /// Returns a pair of (return value, chain).
2041 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2042 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2043 EVT RetVT, const SDValue *Ops,
2044 unsigned NumOps, bool isSigned,
2045 SDLoc dl, bool doesNotReturn = false,
2046 bool isReturnValueUsed = true) const;
2048 //===--------------------------------------------------------------------===//
2049 // TargetLowering Optimization Methods
2052 /// A convenience struct that encapsulates a DAG, and two SDValues for
2053 /// returning information from TargetLowering to its clients that want to
2055 struct TargetLoweringOpt {
2062 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2064 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2066 bool LegalTypes() const { return LegalTys; }
2067 bool LegalOperations() const { return LegalOps; }
2069 bool CombineTo(SDValue O, SDValue N) {
2075 /// Check to see if the specified operand of the specified instruction is a
2076 /// constant integer. If so, check to see if there are any bits set in the
2077 /// constant that are not demanded. If so, shrink the constant and return
2079 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
2081 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2082 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2083 /// generalized for targets with other types of implicit widening casts.
2084 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2088 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2089 /// result of Op are ever used downstream. If we can use this information to
2090 /// simplify Op, create a new simplified DAG node and return true, returning
2091 /// the original and new nodes in Old and New. Otherwise, analyze the
2092 /// expression and return a mask of KnownOne and KnownZero bits for the
2093 /// expression (used to simplify the caller). The KnownZero/One bits may only
2094 /// be accurate for those bits in the DemandedMask.
2095 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2096 APInt &KnownZero, APInt &KnownOne,
2097 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2099 /// Determine which of the bits specified in Mask are known to be either zero
2100 /// or one and return them in the KnownZero/KnownOne bitsets.
2101 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2104 const SelectionDAG &DAG,
2105 unsigned Depth = 0) const;
2107 /// This method can be implemented by targets that want to expose additional
2108 /// information about sign bits to the DAG Combiner.
2109 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2110 const SelectionDAG &DAG,
2111 unsigned Depth = 0) const;
2113 struct DAGCombinerInfo {
2114 void *DC; // The DAG Combiner object.
2116 bool CalledByLegalizer;
2120 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2121 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2123 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2124 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2125 bool isAfterLegalizeVectorOps() const {
2126 return Level == AfterLegalizeDAG;
2128 CombineLevel getDAGCombineLevel() { return Level; }
2129 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2131 void AddToWorklist(SDNode *N);
2132 void RemoveFromWorklist(SDNode *N);
2133 SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2134 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2135 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2137 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2140 /// Return if the N is a constant or constant vector equal to the true value
2141 /// from getBooleanContents().
2142 bool isConstTrueVal(const SDNode *N) const;
2144 /// Return if the N is a constant or constant vector equal to the false value
2145 /// from getBooleanContents().
2146 bool isConstFalseVal(const SDNode *N) const;
2148 /// Try to simplify a setcc built with the specified operands and cc. If it is
2149 /// unable to simplify it, return a null SDValue.
2150 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2151 ISD::CondCode Cond, bool foldBooleans,
2152 DAGCombinerInfo &DCI, SDLoc dl) const;
2154 /// Returns true (and the GlobalValue and the offset) if the node is a
2155 /// GlobalAddress + offset.
2157 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2159 /// This method will be invoked for all target nodes and for any
2160 /// target-independent nodes that the target has registered with invoke it
2163 /// The semantics are as follows:
2165 /// SDValue.Val == 0 - No change was made
2166 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2167 /// otherwise - N should be replaced by the returned Operand.
2169 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2170 /// more complex transformations.
2172 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2174 /// Return true if it is profitable to move a following shift through this
2175 // node, adjusting any immediate operands as necessary to preserve semantics.
2176 // This transformation may not be desirable if it disrupts a particularly
2177 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2178 // By default, it returns true.
2179 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2183 /// Return true if the target has native support for the specified value type
2184 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2185 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2186 /// and some i16 instructions are slow.
2187 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2188 // By default, assume all legal types are desirable.
2189 return isTypeLegal(VT);
2192 /// Return true if it is profitable for dag combiner to transform a floating
2193 /// point op of specified opcode to a equivalent op of an integer
2194 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2195 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2200 /// This method query the target whether it is beneficial for dag combiner to
2201 /// promote the specified node. If true, it should return the desired
2202 /// promotion type by reference.
2203 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2207 //===--------------------------------------------------------------------===//
2208 // Lowering methods - These methods must be implemented by targets so that
2209 // the SelectionDAGBuilder code knows how to lower these.
2212 /// This hook must be implemented to lower the incoming (formal) arguments,
2213 /// described by the Ins array, into the specified DAG. The implementation
2214 /// should fill in the InVals array with legal-type argument values, and
2215 /// return the resulting token chain value.
2218 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2220 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2221 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2222 SmallVectorImpl<SDValue> &/*InVals*/) const {
2223 llvm_unreachable("Not Implemented");
2226 struct ArgListEntry {
2235 bool isInAlloca : 1;
2236 bool isReturned : 1;
2239 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2240 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2241 isReturned(false), Alignment(0) { }
2243 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2245 typedef std::vector<ArgListEntry> ArgListTy;
2247 /// This structure contains all information that is necessary for lowering
2248 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2249 /// needs to lower a call, and targets will see this struct in their LowerCall
2251 struct CallLoweringInfo {
2258 bool DoesNotReturn : 1;
2259 bool IsReturnValueUsed : 1;
2261 // IsTailCall should be modified by implementations of
2262 // TargetLowering::LowerCall that perform tail call conversions.
2265 unsigned NumFixedArgs;
2266 CallingConv::ID CallConv;
2271 ImmutableCallSite *CS;
2273 SmallVector<ISD::OutputArg, 32> Outs;
2274 SmallVector<SDValue, 32> OutVals;
2275 SmallVector<ISD::InputArg, 32> Ins;
2277 CallLoweringInfo(SelectionDAG &DAG)
2278 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2279 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2280 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2281 DAG(DAG), CS(nullptr), IsPatchPoint(false) {}
2283 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2288 CallLoweringInfo &setChain(SDValue InChain) {
2293 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2294 SDValue Target, ArgListTy &&ArgsList,
2295 unsigned FixedArgs = -1) {
2300 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2301 Args = std::move(ArgsList);
2305 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2306 SDValue Target, ArgListTy &&ArgsList,
2307 ImmutableCallSite &Call) {
2310 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2311 DoesNotReturn = Call.doesNotReturn();
2312 IsVarArg = FTy->isVarArg();
2313 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2314 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2315 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2319 CallConv = Call.getCallingConv();
2320 NumFixedArgs = FTy->getNumParams();
2321 Args = std::move(ArgsList);
2328 CallLoweringInfo &setInRegister(bool Value = true) {
2333 CallLoweringInfo &setNoReturn(bool Value = true) {
2334 DoesNotReturn = Value;
2338 CallLoweringInfo &setVarArg(bool Value = true) {
2343 CallLoweringInfo &setTailCall(bool Value = true) {
2348 CallLoweringInfo &setDiscardResult(bool Value = true) {
2349 IsReturnValueUsed = !Value;
2353 CallLoweringInfo &setSExtResult(bool Value = true) {
2358 CallLoweringInfo &setZExtResult(bool Value = true) {
2363 CallLoweringInfo &setIsPatchPoint(bool Value = true) {
2364 IsPatchPoint = Value;
2368 ArgListTy &getArgs() {
2373 /// This function lowers an abstract call to a function into an actual call.
2374 /// This returns a pair of operands. The first element is the return value
2375 /// for the function (if RetTy is not VoidTy). The second element is the
2376 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2377 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2379 /// This hook must be implemented to lower calls into the the specified
2380 /// DAG. The outgoing arguments to the call are described by the Outs array,
2381 /// and the values to be returned by the call are described by the Ins
2382 /// array. The implementation should fill in the InVals array with legal-type
2383 /// return values from the call, and return the resulting token chain value.
2385 LowerCall(CallLoweringInfo &/*CLI*/,
2386 SmallVectorImpl<SDValue> &/*InVals*/) const {
2387 llvm_unreachable("Not Implemented");
2390 /// Target-specific cleanup for formal ByVal parameters.
2391 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2393 /// This hook should be implemented to check whether the return values
2394 /// described by the Outs array can fit into the return registers. If false
2395 /// is returned, an sret-demotion is performed.
2396 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2397 MachineFunction &/*MF*/, bool /*isVarArg*/,
2398 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2399 LLVMContext &/*Context*/) const
2401 // Return true by default to get preexisting behavior.
2405 /// This hook must be implemented to lower outgoing return values, described
2406 /// by the Outs array, into the specified DAG. The implementation should
2407 /// return the resulting token chain value.
2409 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2411 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2412 const SmallVectorImpl<SDValue> &/*OutVals*/,
2413 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2414 llvm_unreachable("Not Implemented");
2417 /// Return true if result of the specified node is used by a return node
2418 /// only. It also compute and return the input chain for the tail call.
2420 /// This is used to determine whether it is possible to codegen a libcall as
2421 /// tail call at legalization time.
2422 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2426 /// Return true if the target may be able emit the call instruction as a tail
2427 /// call. This is used by optimization passes to determine if it's profitable
2428 /// to duplicate return instructions to enable tailcall optimization.
2429 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2433 /// Return the builtin name for the __builtin___clear_cache intrinsic
2434 /// Default is to invoke the clear cache library call
2435 virtual const char * getClearCacheBuiltinName() const {
2436 return "__clear_cache";
2439 /// Return the register ID of the name passed in. Used by named register
2440 /// global variables extension. There is no target-independent behaviour
2441 /// so the default action is to bail.
2442 virtual unsigned getRegisterByName(const char* RegName, EVT VT) const {
2443 report_fatal_error("Named registers not implemented for this target");
2446 /// Return the type that should be used to zero or sign extend a
2447 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2448 /// convention requires the return type to be promoted, but this is not true
2449 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2450 /// calling conventions. The frontend should handle this and include all of
2451 /// the necessary information.
2452 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2453 ISD::NodeType /*ExtendKind*/) const {
2454 EVT MinVT = getRegisterType(Context, MVT::i32);
2455 return VT.bitsLT(MinVT) ? MinVT : VT;
2458 /// For some targets, an LLVM struct type must be broken down into multiple
2459 /// simple types, but the calling convention specifies that the entire struct
2460 /// must be passed in a block of consecutive registers.
2462 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2463 bool isVarArg) const {
2467 /// Returns a 0 terminated array of registers that can be safely used as
2468 /// scratch registers.
2469 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2473 /// This callback is used to prepare for a volatile or atomic load.
2474 /// It takes a chain node as input and returns the chain for the load itself.
2476 /// Having a callback like this is necessary for targets like SystemZ,
2477 /// which allows a CPU to reuse the result of a previous load indefinitely,
2478 /// even if a cache-coherent store is performed by another CPU. The default
2479 /// implementation does nothing.
2480 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2481 SelectionDAG &DAG) const {
2485 /// This callback is invoked by the type legalizer to legalize nodes with an
2486 /// illegal operand type but legal result types. It replaces the
2487 /// LowerOperation callback in the type Legalizer. The reason we can not do
2488 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2489 /// use this callback.
2491 /// TODO: Consider merging with ReplaceNodeResults.
2493 /// The target places new result values for the node in Results (their number
2494 /// and types must exactly match those of the original return values of
2495 /// the node), or leaves Results empty, which indicates that the node is not
2496 /// to be custom lowered after all.
2497 /// The default implementation calls LowerOperation.
2498 virtual void LowerOperationWrapper(SDNode *N,
2499 SmallVectorImpl<SDValue> &Results,
2500 SelectionDAG &DAG) const;
2502 /// This callback is invoked for operations that are unsupported by the
2503 /// target, which are registered to use 'custom' lowering, and whose defined
2504 /// values are all legal. If the target has no operations that require custom
2505 /// lowering, it need not implement this. The default implementation of this
2507 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2509 /// This callback is invoked when a node result type is illegal for the
2510 /// target, and the operation was registered to use 'custom' lowering for that
2511 /// result type. The target places new result values for the node in Results
2512 /// (their number and types must exactly match those of the original return
2513 /// values of the node), or leaves Results empty, which indicates that the
2514 /// node is not to be custom lowered after all.
2516 /// If the target has no operations that require custom lowering, it need not
2517 /// implement this. The default implementation aborts.
2518 virtual void ReplaceNodeResults(SDNode * /*N*/,
2519 SmallVectorImpl<SDValue> &/*Results*/,
2520 SelectionDAG &/*DAG*/) const {
2521 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2524 /// This method returns the name of a target specific DAG node.
2525 virtual const char *getTargetNodeName(unsigned Opcode) const;
2527 /// This method returns a target specific FastISel object, or null if the
2528 /// target does not support "fast" ISel.
2529 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2530 const TargetLibraryInfo *) const {
2535 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2536 SelectionDAG &DAG) const;
2538 //===--------------------------------------------------------------------===//
2539 // Inline Asm Support hooks
2542 /// This hook allows the target to expand an inline asm call to be explicit
2543 /// llvm code if it wants to. This is useful for turning simple inline asms
2544 /// into LLVM intrinsics, which gives the compiler more information about the
2545 /// behavior of the code.
2546 virtual bool ExpandInlineAsm(CallInst *) const {
2550 enum ConstraintType {
2551 C_Register, // Constraint represents specific register(s).
2552 C_RegisterClass, // Constraint represents any of register(s) in class.
2553 C_Memory, // Memory constraint.
2554 C_Other, // Something else.
2555 C_Unknown // Unsupported constraint.
2558 enum ConstraintWeight {
2560 CW_Invalid = -1, // No match.
2561 CW_Okay = 0, // Acceptable.
2562 CW_Good = 1, // Good weight.
2563 CW_Better = 2, // Better weight.
2564 CW_Best = 3, // Best weight.
2566 // Well-known weights.
2567 CW_SpecificReg = CW_Okay, // Specific register operands.
2568 CW_Register = CW_Good, // Register operands.
2569 CW_Memory = CW_Better, // Memory operands.
2570 CW_Constant = CW_Best, // Constant operand.
2571 CW_Default = CW_Okay // Default or don't know type.
2574 /// This contains information for each constraint that we are lowering.
2575 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2576 /// This contains the actual string for the code, like "m". TargetLowering
2577 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2578 /// matches the operand.
2579 std::string ConstraintCode;
2581 /// Information about the constraint code, e.g. Register, RegisterClass,
2582 /// Memory, Other, Unknown.
2583 TargetLowering::ConstraintType ConstraintType;
2585 /// If this is the result output operand or a clobber, this is null,
2586 /// otherwise it is the incoming operand to the CallInst. This gets
2587 /// modified as the asm is processed.
2588 Value *CallOperandVal;
2590 /// The ValueType for the operand value.
2593 /// Return true of this is an input operand that is a matching constraint
2595 bool isMatchingInputConstraint() const;
2597 /// If this is an input matching constraint, this method returns the output
2598 /// operand it matches.
2599 unsigned getMatchedOperand() const;
2601 /// Copy constructor for copying from a ConstraintInfo.
2602 AsmOperandInfo(InlineAsm::ConstraintInfo Info)
2603 : InlineAsm::ConstraintInfo(std::move(Info)),
2604 ConstraintType(TargetLowering::C_Unknown), CallOperandVal(nullptr),
2605 ConstraintVT(MVT::Other) {}
2608 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2610 /// Split up the constraint string from the inline assembly value into the
2611 /// specific constraints and their prefixes, and also tie in the associated
2612 /// operand values. If this returns an empty vector, and if the constraint
2613 /// string itself isn't empty, there was an error parsing.
2614 virtual AsmOperandInfoVector ParseConstraints(const TargetRegisterInfo *TRI,
2615 ImmutableCallSite CS) const;
2617 /// Examine constraint type and operand type and determine a weight value.
2618 /// The operand object must already have been set up with the operand type.
2619 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2620 AsmOperandInfo &info, int maIndex) const;
2622 /// Examine constraint string and operand type and determine a weight value.
2623 /// The operand object must already have been set up with the operand type.
2624 virtual ConstraintWeight getSingleConstraintMatchWeight(
2625 AsmOperandInfo &info, const char *constraint) const;
2627 /// Determines the constraint code and constraint type to use for the specific
2628 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2629 /// If the actual operand being passed in is available, it can be passed in as
2630 /// Op, otherwise an empty SDValue can be passed.
2631 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2633 SelectionDAG *DAG = nullptr) const;
2635 /// Given a constraint, return the type of constraint it is for this target.
2636 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2638 /// Given a physical register constraint (e.g. {edx}), return the register
2639 /// number and the register class for the register.
2641 /// Given a register class constraint, like 'r', if this corresponds directly
2642 /// to an LLVM register class, return a register of 0 and the register class
2645 /// This should only be used for C_Register constraints. On error, this
2646 /// returns a register number of 0 and a null register class pointer.
2647 virtual std::pair<unsigned, const TargetRegisterClass *>
2648 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2649 const std::string &Constraint, MVT VT) const;
2652 getInlineAsmMemConstraint(const std::string &ConstraintCode) const {
2653 if (ConstraintCode == "i")
2654 return InlineAsm::Constraint_i;
2655 else if (ConstraintCode == "m")
2656 return InlineAsm::Constraint_m;
2657 return InlineAsm::Constraint_Unknown;
2660 /// Try to replace an X constraint, which matches anything, with another that
2661 /// has more specific requirements based on the type of the corresponding
2662 /// operand. This returns null if there is no replacement to make.
2663 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2665 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2666 /// add anything to Ops.
2667 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2668 std::vector<SDValue> &Ops,
2669 SelectionDAG &DAG) const;
2671 //===--------------------------------------------------------------------===//
2672 // Div utility functions
2674 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2675 SelectionDAG &DAG) const;
2676 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2677 bool IsAfterLegalization,
2678 std::vector<SDNode *> *Created) const;
2679 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2680 bool IsAfterLegalization,
2681 std::vector<SDNode *> *Created) const;
2682 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2684 std::vector<SDNode *> *Created) const {
2688 /// Indicate whether this target prefers to combine the given number of FDIVs
2689 /// with the same divisor.
2690 virtual bool combineRepeatedFPDivisors(unsigned NumUsers) const {
2694 /// Hooks for building estimates in place of slower divisions and square
2697 /// Return a reciprocal square root estimate value for the input operand.
2698 /// The RefinementSteps output is the number of Newton-Raphson refinement
2699 /// iterations required to generate a sufficient (though not necessarily
2700 /// IEEE-754 compliant) estimate for the value type.
2701 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
2702 /// algorithm implementation that uses one constant or two constants.
2703 /// A target may choose to implement its own refinement within this function.
2704 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2705 /// any further refinement of the estimate.
2706 /// An empty SDValue return means no estimate sequence can be created.
2707 virtual SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2708 unsigned &RefinementSteps,
2709 bool &UseOneConstNR) const {
2713 /// Return a reciprocal estimate value for the input operand.
2714 /// The RefinementSteps output is the number of Newton-Raphson refinement
2715 /// iterations required to generate a sufficient (though not necessarily
2716 /// IEEE-754 compliant) estimate for the value type.
2717 /// A target may choose to implement its own refinement within this function.
2718 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2719 /// any further refinement of the estimate.
2720 /// An empty SDValue return means no estimate sequence can be created.
2721 virtual SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2722 unsigned &RefinementSteps) const {
2726 //===--------------------------------------------------------------------===//
2727 // Legalization utility functions
2730 /// Expand a MUL into two nodes. One that computes the high bits of
2731 /// the result and one that computes the low bits.
2732 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2733 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2734 /// if you want to control how low bits are extracted from the LHS.
2735 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2736 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2737 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2738 /// \returns true if the node has been expanded. false if it has not
2739 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2740 SelectionDAG &DAG, SDValue LL = SDValue(),
2741 SDValue LH = SDValue(), SDValue RL = SDValue(),
2742 SDValue RH = SDValue()) const;
2744 /// Expand float(f32) to SINT(i64) conversion
2745 /// \param N Node to expand
2746 /// \param Result output after conversion
2747 /// \returns True, if the expansion was successful, false otherwise
2748 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
2750 //===--------------------------------------------------------------------===//
2751 // Instruction Emitting Hooks
2754 /// This method should be implemented by targets that mark instructions with
2755 /// the 'usesCustomInserter' flag. These instructions are special in various
2756 /// ways, which require special support to insert. The specified MachineInstr
2757 /// is created but not inserted into any basic blocks, and this method is
2758 /// called to expand it into a sequence of instructions, potentially also
2759 /// creating new basic blocks and control flow.
2760 /// As long as the returned basic block is different (i.e., we created a new
2761 /// one), the custom inserter is free to modify the rest of \p MBB.
2762 virtual MachineBasicBlock *
2763 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2765 /// This method should be implemented by targets that mark instructions with
2766 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2767 /// instruction selection by target hooks. e.g. To fill in optional defs for
2768 /// ARM 's' setting instructions.
2770 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2772 /// If this function returns true, SelectionDAGBuilder emits a
2773 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
2774 virtual bool useLoadStackGuardNode() const {
2779 /// Given an LLVM IR type and return type attributes, compute the return value
2780 /// EVTs and flags, and optionally also the offsets, if the return value is
2781 /// being lowered to memory.
2782 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2783 SmallVectorImpl<ISD::OutputArg> &Outs,
2784 const TargetLowering &TLI);
2786 } // end llvm namespace