1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/ADT/DenseMap.h"
26 #include "llvm/CodeGen/DAGCombine.h"
27 #include "llvm/CodeGen/RuntimeLibcalls.h"
28 #include "llvm/CodeGen/SelectionDAGNodes.h"
29 #include "llvm/IR/Attributes.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/InlineAsm.h"
32 #include "llvm/Support/CallSite.h"
33 #include "llvm/Target/TargetCallingConv.h"
34 #include "llvm/Target/TargetMachine.h"
43 class FunctionLoweringInfo;
44 class ImmutableCallSite;
46 class MachineBasicBlock;
47 class MachineFunction;
49 class MachineJumpTableInfo;
52 template<typename T> class SmallVectorImpl;
54 class TargetRegisterClass;
55 class TargetLibraryInfo;
56 class TargetLoweringObjectFile;
61 None, // No preference
62 Source, // Follow source order.
63 RegPressure, // Scheduling for lowest register pressure.
64 Hybrid, // Scheduling for both latency and register pressure.
65 ILP, // Scheduling for ILP in low register pressure mode.
66 VLIW // Scheduling for VLIW targets.
70 /// TargetLoweringBase - This base class for TargetLowering contains the
71 /// SelectionDAG-independent parts that can be used from the rest of CodeGen.
72 class TargetLoweringBase {
73 TargetLoweringBase(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
74 void operator=(const TargetLoweringBase&) LLVM_DELETED_FUNCTION;
77 /// LegalizeAction - This enum indicates whether operations are valid for a
78 /// target, and if not, what action should be used to make them valid.
80 Legal, // The target natively supports this operation.
81 Promote, // This operation should be executed in a larger type.
82 Expand, // Try to expand this to other ops, otherwise use a libcall.
83 Custom // Use the LowerOperation hook to implement custom lowering.
86 /// LegalizeTypeAction - This enum indicates whether a types are legal for a
87 /// target, and if not, what action should be used to make them valid.
88 enum LegalizeTypeAction {
89 TypeLegal, // The target natively supports this type.
90 TypePromoteInteger, // Replace this integer with a larger one.
91 TypeExpandInteger, // Split this integer into two of half the size.
92 TypeSoftenFloat, // Convert this float to a same size integer type.
93 TypeExpandFloat, // Split this float into two of half the size.
94 TypeScalarizeVector, // Replace this one-element vector with its element.
95 TypeSplitVector, // Split this vector into two of half the size.
96 TypeWidenVector // This vector should be widened into a larger vector.
99 /// LegalizeKind holds the legalization kind that needs to happen to EVT
100 /// in order to type-legalize it.
101 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
103 enum BooleanContent { // How the target represents true/false values.
104 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
105 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
106 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
109 enum SelectSupportKind {
110 ScalarValSelect, // The target supports scalar selects (ex: cmov).
111 ScalarCondVectorVal, // The target supports selects with a scalar condition
112 // and vector values (ex: cmov).
113 VectorMaskSelect // The target supports vector selects with a vector
114 // mask (ex: x86 blends).
117 static ISD::NodeType getExtendForContent(BooleanContent Content) {
119 case UndefinedBooleanContent:
120 // Extend by adding rubbish bits.
121 return ISD::ANY_EXTEND;
122 case ZeroOrOneBooleanContent:
123 // Extend by adding zero bits.
124 return ISD::ZERO_EXTEND;
125 case ZeroOrNegativeOneBooleanContent:
126 // Extend by copying the sign bit.
127 return ISD::SIGN_EXTEND;
129 llvm_unreachable("Invalid content kind");
132 /// NOTE: The constructor takes ownership of TLOF.
133 explicit TargetLoweringBase(const TargetMachine &TM,
134 const TargetLoweringObjectFile *TLOF);
135 virtual ~TargetLoweringBase();
138 /// \brief Initialize all of the actions to default values.
142 const TargetMachine &getTargetMachine() const { return TM; }
143 const DataLayout *getDataLayout() const { return TD; }
144 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
146 bool isBigEndian() const { return !IsLittleEndian; }
147 bool isLittleEndian() const { return IsLittleEndian; }
148 // Return the pointer type for the given address space, defaults to
149 // the pointer type from the data layout.
150 // FIXME: The default needs to be removed once all the code is updated.
151 virtual MVT getPointerTy(uint32_t AS = 0) const { return PointerTy; }
152 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const;
154 EVT getShiftAmountTy(EVT LHSTy) const;
156 /// isSelectExpensive - Return true if the select operation is expensive for
158 bool isSelectExpensive() const { return SelectIsExpensive; }
160 virtual bool isSelectSupported(SelectSupportKind kind) const { return true; }
162 /// shouldSplitVectorElementType - Return true if a vector of the given type
163 /// should be split (TypeSplitVector) instead of promoted
164 /// (TypePromoteInteger) during type legalization.
165 virtual bool shouldSplitVectorElementType(EVT VT) const { return false; }
167 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
168 /// a sequence of several shifts, adds, and multiplies for this target.
169 bool isIntDivCheap() const { return IntDivIsCheap; }
171 /// isSlowDivBypassed - Returns true if target has indicated at least one
172 /// type should be bypassed.
173 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
175 /// getBypassSlowDivTypes - Returns map of slow types for division or
176 /// remainder with corresponding fast types
177 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
178 return BypassSlowDivWidths;
181 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
183 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
185 /// isJumpExpensive() - Return true if Flow Control is an expensive operation
186 /// that should be avoided.
187 bool isJumpExpensive() const { return JumpIsExpensive; }
189 /// isPredictableSelectExpensive - Return true if selects are only cheaper
190 /// than branches if the branch is unlikely to be predicted right.
191 bool isPredictableSelectExpensive() const {
192 return PredictableSelectIsExpensive;
195 /// getSetCCResultType - Return the ValueType of the result of SETCC
196 /// operations. Also used to obtain the target's preferred type for
197 /// the condition operand of SELECT and BRCOND nodes. In the case of
198 /// BRCOND the argument passed is MVT::Other since there are no other
199 /// operands to get a type hint from.
200 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
202 /// getCmpLibcallReturnType - Return the ValueType for comparison
203 /// libcalls. Comparions libcalls include floating point comparion calls,
204 /// and Ordered/Unordered check calls on floating point numbers.
206 MVT::SimpleValueType getCmpLibcallReturnType() const;
208 /// getBooleanContents - For targets without i1 registers, this gives the
209 /// nature of the high-bits of boolean values held in types wider than i1.
210 /// "Boolean values" are special true/false values produced by nodes like
211 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
212 /// Not to be confused with general values promoted from i1.
213 /// Some cpus distinguish between vectors of boolean and scalars; the isVec
214 /// parameter selects between the two kinds. For example on X86 a scalar
215 /// boolean should be zero extended from i1, while the elements of a vector
216 /// of booleans should be sign extended from i1.
217 BooleanContent getBooleanContents(bool isVec) const {
218 return isVec ? BooleanVectorContents : BooleanContents;
221 /// getSchedulingPreference - Return target scheduling preference.
222 Sched::Preference getSchedulingPreference() const {
223 return SchedPreferenceInfo;
226 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to
227 /// different scheduling heuristics for different nodes. This function returns
228 /// the preference (or none) for the given node.
229 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
233 /// getRegClassFor - Return the register class that should be used for the
234 /// specified value type.
235 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
236 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
237 assert(RC && "This value type is not natively supported!");
241 /// getRepRegClassFor - Return the 'representative' register class for the
242 /// specified value type. The 'representative' register class is the largest
243 /// legal super-reg register class for the register class of the value type.
244 /// For example, on i386 the rep register class for i8, i16, and i32 are GR32;
245 /// while the rep register class is GR64 on x86_64.
246 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
247 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
251 /// getRepRegClassCostFor - Return the cost of the 'representative' register
252 /// class for the specified value type.
253 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
254 return RepRegClassCostForVT[VT.SimpleTy];
257 /// isTypeLegal - Return true if the target has native support for the
258 /// specified value type. This means that it has a register that directly
259 /// holds it without promotions or expansions.
260 bool isTypeLegal(EVT VT) const {
261 assert(!VT.isSimple() ||
262 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
263 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
266 class ValueTypeActionImpl {
267 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
268 /// that indicates how instruction selection should deal with the type.
269 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
272 ValueTypeActionImpl() {
273 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
276 LegalizeTypeAction getTypeAction(MVT VT) const {
277 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
280 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
281 unsigned I = VT.SimpleTy;
282 ValueTypeActions[I] = Action;
286 const ValueTypeActionImpl &getValueTypeActions() const {
287 return ValueTypeActions;
290 /// getTypeAction - Return how we should legalize values of this type, either
291 /// it is already legal (return 'Legal') or we need to promote it to a larger
292 /// type (return 'Promote'), or we need to expand it into multiple registers
293 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
294 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
295 return getTypeConversion(Context, VT).first;
297 LegalizeTypeAction getTypeAction(MVT VT) const {
298 return ValueTypeActions.getTypeAction(VT);
301 /// getTypeToTransformTo - For types supported by the target, this is an
302 /// identity function. For types that must be promoted to larger types, this
303 /// returns the larger type to promote to. For integer types that are larger
304 /// than the largest integer register, this contains one step in the expansion
305 /// to get to the smaller register. For illegal floating point types, this
306 /// returns the integer type to transform to.
307 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
308 return getTypeConversion(Context, VT).second;
311 /// getTypeToExpandTo - For types supported by the target, this is an
312 /// identity function. For types that must be expanded (i.e. integer types
313 /// that are larger than the largest integer register or illegal floating
314 /// point types), this returns the largest legal type it will be expanded to.
315 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
316 assert(!VT.isVector());
318 switch (getTypeAction(Context, VT)) {
321 case TypeExpandInteger:
322 VT = getTypeToTransformTo(Context, VT);
325 llvm_unreachable("Type is not legal nor is it to be expanded!");
330 /// getVectorTypeBreakdown - Vector types are broken down into some number of
331 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
332 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
333 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
335 /// This method returns the number of registers needed, and the VT for each
336 /// register. It also returns the VT and quantity of the intermediate values
337 /// before they are promoted/expanded.
339 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
341 unsigned &NumIntermediates,
342 MVT &RegisterVT) const;
344 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
345 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
346 /// this is the case, it returns true and store the intrinsic
347 /// information into the IntrinsicInfo that was passed to the function.
348 struct IntrinsicInfo {
349 unsigned opc; // target opcode
350 EVT memVT; // memory VT
351 const Value* ptrVal; // value representing memory location
352 int offset; // offset off of ptrVal
353 unsigned align; // alignment
354 bool vol; // is volatile?
355 bool readMem; // reads memory?
356 bool writeMem; // writes memory?
359 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
360 unsigned /*Intrinsic*/) const {
364 /// isFPImmLegal - Returns true if the target can instruction select the
365 /// specified FP immediate natively. If false, the legalizer will materialize
366 /// the FP immediate as a load from a constant pool.
367 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
371 /// isShuffleMaskLegal - Targets can use this to indicate that they only
372 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
373 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
374 /// are assumed to be legal.
375 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
380 /// canOpTrap - Returns true if the operation can trap for the value type.
381 /// VT must be a legal type. By default, we optimistically assume most
382 /// operations don't trap except for divide and remainder.
383 virtual bool canOpTrap(unsigned Op, EVT VT) const;
385 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
386 /// used by Targets can use this to indicate if there is a suitable
387 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
389 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
394 /// getOperationAction - Return how this operation should be treated: either
395 /// it is legal, needs to be promoted to a larger size, needs to be
396 /// expanded to some other code sequence, or the target has a custom expander
398 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
399 if (VT.isExtended()) return Expand;
400 // If a target-specific SDNode requires legalization, require the target
401 // to provide custom legalization for it.
402 if (Op > array_lengthof(OpActions[0])) return Custom;
403 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
404 return (LegalizeAction)OpActions[I][Op];
407 /// isOperationLegalOrCustom - Return true if the specified operation is
408 /// legal on this target or can be made legal with custom lowering. This
409 /// is used to help guide high-level lowering decisions.
410 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
411 return (VT == MVT::Other || isTypeLegal(VT)) &&
412 (getOperationAction(Op, VT) == Legal ||
413 getOperationAction(Op, VT) == Custom);
416 /// isOperationLegalOrPromote - Return true if the specified operation is
417 /// legal on this target or can be made legal using promotion. This
418 /// is used to help guide high-level lowering decisions.
419 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
420 return (VT == MVT::Other || isTypeLegal(VT)) &&
421 (getOperationAction(Op, VT) == Legal ||
422 getOperationAction(Op, VT) == Promote);
425 /// isOperationExpand - Return true if the specified operation is illegal on
426 /// this target or unlikely to be made legal with custom lowering. This is
427 /// used to help guide high-level lowering decisions.
428 bool isOperationExpand(unsigned Op, EVT VT) const {
429 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
432 /// isOperationLegal - Return true if the specified operation is legal on this
434 bool isOperationLegal(unsigned Op, EVT VT) const {
435 return (VT == MVT::Other || isTypeLegal(VT)) &&
436 getOperationAction(Op, VT) == Legal;
439 /// getLoadExtAction - Return how this load with extension should be treated:
440 /// either it is legal, needs to be promoted to a larger size, needs to be
441 /// expanded to some other code sequence, or the target has a custom expander
443 LegalizeAction getLoadExtAction(unsigned ExtType, MVT VT) const {
444 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
445 "Table isn't big enough!");
446 return (LegalizeAction)LoadExtActions[VT.SimpleTy][ExtType];
449 /// isLoadExtLegal - Return true if the specified load with extension is legal
451 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
452 return VT.isSimple() &&
453 getLoadExtAction(ExtType, VT.getSimpleVT()) == Legal;
456 /// getTruncStoreAction - Return how this store with truncation should be
457 /// treated: either it is legal, needs to be promoted to a larger size, needs
458 /// to be expanded to some other code sequence, or the target has a custom
460 LegalizeAction getTruncStoreAction(MVT ValVT, MVT MemVT) const {
461 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
462 "Table isn't big enough!");
463 return (LegalizeAction)TruncStoreActions[ValVT.SimpleTy]
467 /// isTruncStoreLegal - Return true if the specified store with truncation is
468 /// legal on this target.
469 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
470 return isTypeLegal(ValVT) && MemVT.isSimple() &&
471 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
474 /// getIndexedLoadAction - Return how the indexed load should be treated:
475 /// either it is legal, needs to be promoted to a larger size, needs to be
476 /// expanded to some other code sequence, or the target has a custom expander
479 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
480 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
481 "Table isn't big enough!");
482 unsigned Ty = (unsigned)VT.SimpleTy;
483 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
486 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
488 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
489 return VT.isSimple() &&
490 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
491 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
494 /// getIndexedStoreAction - Return how the indexed store should be treated:
495 /// either it is legal, needs to be promoted to a larger size, needs to be
496 /// expanded to some other code sequence, or the target has a custom expander
499 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
500 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT < MVT::LAST_VALUETYPE &&
501 "Table isn't big enough!");
502 unsigned Ty = (unsigned)VT.SimpleTy;
503 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
506 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
508 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
509 return VT.isSimple() &&
510 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
511 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
514 /// getCondCodeAction - Return how the condition code should be treated:
515 /// either it is legal, needs to be expanded to some other code sequence,
516 /// or the target has a custom expander for it.
518 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
519 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
520 (unsigned)VT.SimpleTy < sizeof(CondCodeActions[0])*4 &&
521 "Table isn't big enough!");
522 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit
523 /// value and the upper 27 bits index into the second dimension of the
524 /// array to select what 64bit value to use.
525 LegalizeAction Action = (LegalizeAction)
526 ((CondCodeActions[CC][VT.SimpleTy >> 5] >> (2*(VT.SimpleTy & 0x1F))) & 3);
527 assert(Action != Promote && "Can't promote condition code!");
531 /// isCondCodeLegal - Return true if the specified condition code is legal
533 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
535 getCondCodeAction(CC, VT) == Legal ||
536 getCondCodeAction(CC, VT) == Custom;
540 /// getTypeToPromoteTo - If the action for this operation is to promote, this
541 /// method returns the ValueType to promote to.
542 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
543 assert(getOperationAction(Op, VT) == Promote &&
544 "This operation isn't promoted!");
546 // See if this has an explicit type specified.
547 std::map<std::pair<unsigned, MVT::SimpleValueType>,
548 MVT::SimpleValueType>::const_iterator PTTI =
549 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
550 if (PTTI != PromoteToType.end()) return PTTI->second;
552 assert((VT.isInteger() || VT.isFloatingPoint()) &&
553 "Cannot autopromote this type, add it with AddPromotedToType.");
557 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
558 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
559 "Didn't find type to promote to!");
560 } while (!isTypeLegal(NVT) ||
561 getOperationAction(Op, NVT) == Promote);
565 /// getValueType - Return the EVT corresponding to this LLVM type.
566 /// This is fixed by the LLVM operations except for the pointer size. If
567 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
568 /// counterpart (e.g. structs), otherwise it will assert.
569 EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
570 // Lower scalar pointers to native pointer types.
571 if (Ty->isPointerTy()) return PointerTy;
573 if (Ty->isVectorTy()) {
574 VectorType *VTy = cast<VectorType>(Ty);
575 Type *Elm = VTy->getElementType();
576 // Lower vectors of pointers to native pointer types.
577 if (Elm->isPointerTy())
578 Elm = EVT(PointerTy).getTypeForEVT(Ty->getContext());
579 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
580 VTy->getNumElements());
582 return EVT::getEVT(Ty, AllowUnknown);
585 /// Return the MVT corresponding to this LLVM type. See getValueType.
586 MVT getSimpleValueType(Type *Ty, bool AllowUnknown = false) const {
587 return getValueType(Ty, AllowUnknown).getSimpleVT();
590 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
591 /// function arguments in the caller parameter area. This is the actual
592 /// alignment, not its logarithm.
593 virtual unsigned getByValTypeAlignment(Type *Ty) const;
595 /// getRegisterType - Return the type of registers that this ValueType will
596 /// eventually require.
597 MVT getRegisterType(MVT VT) const {
598 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
599 return RegisterTypeForVT[VT.SimpleTy];
602 /// getRegisterType - Return the type of registers that this ValueType will
603 /// eventually require.
604 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
606 assert((unsigned)VT.getSimpleVT().SimpleTy <
607 array_lengthof(RegisterTypeForVT));
608 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
613 unsigned NumIntermediates;
614 (void)getVectorTypeBreakdown(Context, VT, VT1,
615 NumIntermediates, RegisterVT);
618 if (VT.isInteger()) {
619 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
621 llvm_unreachable("Unsupported extended type!");
624 /// getNumRegisters - Return the number of registers that this ValueType will
625 /// eventually require. This is one for any types promoted to live in larger
626 /// registers, but may be more than one for types (like i64) that are split
627 /// into pieces. For types like i140, which are first promoted then expanded,
628 /// it is the number of registers needed to hold all the bits of the original
629 /// type. For an i140 on a 32 bit machine this means 5 registers.
630 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
632 assert((unsigned)VT.getSimpleVT().SimpleTy <
633 array_lengthof(NumRegistersForVT));
634 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
639 unsigned NumIntermediates;
640 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
642 if (VT.isInteger()) {
643 unsigned BitWidth = VT.getSizeInBits();
644 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
645 return (BitWidth + RegWidth - 1) / RegWidth;
647 llvm_unreachable("Unsupported extended type!");
650 /// ShouldShrinkFPConstant - If true, then instruction selection should
651 /// seek to shrink the FP constant of the specified type to a smaller type
652 /// in order to save space and / or reduce runtime.
653 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
655 /// hasTargetDAGCombine - If true, the target has custom DAG combine
656 /// transformations that it can perform for the specified node.
657 bool hasTargetDAGCombine(ISD::NodeType NT) const {
658 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
659 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
662 /// This function returns the maximum number of store operations permitted
663 /// to replace a call to llvm.memset. The value is set by the target at the
664 /// performance threshold for such a replacement. If OptSize is true,
665 /// return the limit for functions that have OptSize attribute.
666 /// @brief Get maximum # of store operations permitted for llvm.memset
667 unsigned getMaxStoresPerMemset(bool OptSize) const {
668 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
671 /// This function returns the maximum number of store operations permitted
672 /// to replace a call to llvm.memcpy. The value is set by the target at the
673 /// performance threshold for such a replacement. If OptSize is true,
674 /// return the limit for functions that have OptSize attribute.
675 /// @brief Get maximum # of store operations permitted for llvm.memcpy
676 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
677 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
680 /// This function returns the maximum number of store operations permitted
681 /// to replace a call to llvm.memmove. The value is set by the target at the
682 /// performance threshold for such a replacement. If OptSize is true,
683 /// return the limit for functions that have OptSize attribute.
684 /// @brief Get maximum # of store operations permitted for llvm.memmove
685 unsigned getMaxStoresPerMemmove(bool OptSize) const {
686 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
689 /// This function returns true if the target allows unaligned memory accesses.
690 /// of the specified type. If true, it also returns whether the unaligned
691 /// memory access is "fast" in the second argument by reference. This is used,
692 /// for example, in situations where an array copy/move/set is converted to a
693 /// sequence of store operations. It's use helps to ensure that such
694 /// replacements don't generate code that causes an alignment error (trap) on
695 /// the target machine.
696 /// @brief Determine if the target supports unaligned memory accesses.
697 virtual bool allowsUnalignedMemoryAccesses(EVT, bool *Fast = 0) const {
701 /// getOptimalMemOpType - Returns the target specific optimal type for load
702 /// and store operations as a result of memset, memcpy, and memmove
703 /// lowering. If DstAlign is zero that means it's safe to destination
704 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
705 /// means there isn't a need to check it against alignment requirement,
706 /// probably because the source does not need to be loaded. If 'IsMemset' is
707 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
708 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
709 /// source is constant so it does not need to be loaded.
710 /// It returns EVT::Other if the type should be determined using generic
711 /// target-independent logic.
712 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
713 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
716 bool /*MemcpyStrSrc*/,
717 MachineFunction &/*MF*/) const {
721 /// isSafeMemOpType - Returns true if it's safe to use load / store of the
722 /// specified type to expand memcpy / memset inline. This is mostly true
723 /// for all types except for some special cases. For example, on X86
724 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
725 /// also does type conversion. Note the specified type doesn't have to be
726 /// legal as the hook is used before type legalization.
727 virtual bool isSafeMemOpType(MVT VT) const {
731 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
732 /// to implement llvm.setjmp.
733 bool usesUnderscoreSetJmp() const {
734 return UseUnderscoreSetJmp;
737 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
738 /// to implement llvm.longjmp.
739 bool usesUnderscoreLongJmp() const {
740 return UseUnderscoreLongJmp;
743 /// supportJumpTables - return whether the target can generate code for
745 bool supportJumpTables() const {
746 return SupportJumpTables;
749 /// getMinimumJumpTableEntries - return integer threshold on number of
750 /// blocks to use jump tables rather than if sequence.
751 int getMinimumJumpTableEntries() const {
752 return MinimumJumpTableEntries;
755 /// getStackPointerRegisterToSaveRestore - If a physical register, this
756 /// specifies the register that llvm.savestack/llvm.restorestack should save
758 unsigned getStackPointerRegisterToSaveRestore() const {
759 return StackPointerRegisterToSaveRestore;
762 /// getExceptionPointerRegister - If a physical register, this returns
763 /// the register that receives the exception address on entry to a landing
765 unsigned getExceptionPointerRegister() const {
766 return ExceptionPointerRegister;
769 /// getExceptionSelectorRegister - If a physical register, this returns
770 /// the register that receives the exception typeid on entry to a landing
772 unsigned getExceptionSelectorRegister() const {
773 return ExceptionSelectorRegister;
776 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
777 /// set, the default is 200)
778 unsigned getJumpBufSize() const {
782 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
783 /// (if never set, the default is 0)
784 unsigned getJumpBufAlignment() const {
785 return JumpBufAlignment;
788 /// getMinStackArgumentAlignment - return the minimum stack alignment of an
790 unsigned getMinStackArgumentAlignment() const {
791 return MinStackArgumentAlignment;
794 /// getMinFunctionAlignment - return the minimum function alignment.
796 unsigned getMinFunctionAlignment() const {
797 return MinFunctionAlignment;
800 /// getPrefFunctionAlignment - return the preferred function alignment.
802 unsigned getPrefFunctionAlignment() const {
803 return PrefFunctionAlignment;
806 /// getPrefLoopAlignment - return the preferred loop alignment.
808 unsigned getPrefLoopAlignment() const {
809 return PrefLoopAlignment;
812 /// getInsertFencesFor - return whether the DAG builder should automatically
813 /// insert fences and reduce ordering for atomics.
815 bool getInsertFencesForAtomic() const {
816 return InsertFencesForAtomic;
819 /// getStackCookieLocation - Return true if the target stores stack
820 /// protector cookies at a fixed offset in some non-standard address
821 /// space, and populates the address space and offset as
823 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
824 unsigned &/*Offset*/) const {
828 /// getMaximalGlobalOffset - Returns the maximal possible offset which can be
829 /// used for loads / stores from the global.
830 virtual unsigned getMaximalGlobalOffset() const {
834 //===--------------------------------------------------------------------===//
835 /// \name Helpers for TargetTransformInfo implementations
838 /// Get the ISD node that corresponds to the Instruction class opcode.
839 int InstructionOpcodeToISD(unsigned Opcode) const;
841 /// Estimate the cost of type-legalization and the legalized type.
842 std::pair<unsigned, MVT> getTypeLegalizationCost(Type *Ty) const;
846 //===--------------------------------------------------------------------===//
847 // TargetLowering Configuration Methods - These methods should be invoked by
848 // the derived class constructor to configure this object for the target.
851 /// \brief Reset the operation actions based on target options.
852 virtual void resetOperationActions() {}
855 /// setBooleanContents - Specify how the target extends the result of a
856 /// boolean value from i1 to a wider type. See getBooleanContents.
857 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
858 /// setBooleanVectorContents - Specify how the target extends the result
859 /// of a vector boolean value from a vector of i1 to a wider type. See
860 /// getBooleanContents.
861 void setBooleanVectorContents(BooleanContent Ty) {
862 BooleanVectorContents = Ty;
865 /// setSchedulingPreference - Specify the target scheduling preference.
866 void setSchedulingPreference(Sched::Preference Pref) {
867 SchedPreferenceInfo = Pref;
870 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
871 /// use _setjmp to implement llvm.setjmp or the non _ version.
872 /// Defaults to false.
873 void setUseUnderscoreSetJmp(bool Val) {
874 UseUnderscoreSetJmp = Val;
877 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
878 /// use _longjmp to implement llvm.longjmp or the non _ version.
879 /// Defaults to false.
880 void setUseUnderscoreLongJmp(bool Val) {
881 UseUnderscoreLongJmp = Val;
884 /// setSupportJumpTables - Indicate whether the target can generate code for
886 void setSupportJumpTables(bool Val) {
887 SupportJumpTables = Val;
890 /// setMinimumJumpTableEntries - Indicate the number of blocks to generate
891 /// jump tables rather than if sequence.
892 void setMinimumJumpTableEntries(int Val) {
893 MinimumJumpTableEntries = Val;
896 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
897 /// specifies the register that llvm.savestack/llvm.restorestack should save
899 void setStackPointerRegisterToSaveRestore(unsigned R) {
900 StackPointerRegisterToSaveRestore = R;
903 /// setExceptionPointerRegister - If set to a physical register, this sets
904 /// the register that receives the exception address on entry to a landing
906 void setExceptionPointerRegister(unsigned R) {
907 ExceptionPointerRegister = R;
910 /// setExceptionSelectorRegister - If set to a physical register, this sets
911 /// the register that receives the exception typeid on entry to a landing
913 void setExceptionSelectorRegister(unsigned R) {
914 ExceptionSelectorRegister = R;
917 /// SelectIsExpensive - Tells the code generator not to expand operations
918 /// into sequences that use the select operations if possible.
919 void setSelectIsExpensive(bool isExpensive = true) {
920 SelectIsExpensive = isExpensive;
923 /// JumpIsExpensive - Tells the code generator not to expand sequence of
924 /// operations into a separate sequences that increases the amount of
926 void setJumpIsExpensive(bool isExpensive = true) {
927 JumpIsExpensive = isExpensive;
930 /// setIntDivIsCheap - Tells the code generator that integer divide is
931 /// expensive, and if possible, should be replaced by an alternate sequence
932 /// of instructions not containing an integer divide.
933 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
935 /// addBypassSlowDiv - Tells the code generator which bitwidths to bypass.
936 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
937 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
940 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
941 /// srl/add/sra for a signed divide by power of two, and let the target handle
943 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
945 /// addRegisterClass - Add the specified register class as an available
946 /// regclass for the specified value type. This indicates the selector can
947 /// handle values of that class natively.
948 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
949 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
950 AvailableRegClasses.push_back(std::make_pair(VT, RC));
951 RegClassForVT[VT.SimpleTy] = RC;
954 /// clearRegisterClasses - Remove all register classes.
955 void clearRegisterClasses() {
956 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
958 AvailableRegClasses.clear();
961 /// \brief Remove all operation actions.
962 void clearOperationActions() {
965 /// findRepresentativeClass - Return the largest legal super-reg register class
966 /// of the register class for the specified type and its associated "cost".
967 virtual std::pair<const TargetRegisterClass*, uint8_t>
968 findRepresentativeClass(MVT VT) const;
970 /// computeRegisterProperties - Once all of the register classes are added,
971 /// this allows us to compute derived properties we expose.
972 void computeRegisterProperties();
974 /// setOperationAction - Indicate that the specified operation does not work
975 /// with the specified type and indicate what to do about it.
976 void setOperationAction(unsigned Op, MVT VT,
977 LegalizeAction Action) {
978 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
979 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
982 /// setLoadExtAction - Indicate that the specified load with extension does
983 /// not work with the specified type and indicate what to do about it.
984 void setLoadExtAction(unsigned ExtType, MVT VT,
985 LegalizeAction Action) {
986 assert(ExtType < ISD::LAST_LOADEXT_TYPE && VT < MVT::LAST_VALUETYPE &&
987 "Table isn't big enough!");
988 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
991 /// setTruncStoreAction - Indicate that the specified truncating store does
992 /// not work with the specified type and indicate what to do about it.
993 void setTruncStoreAction(MVT ValVT, MVT MemVT,
994 LegalizeAction Action) {
995 assert(ValVT < MVT::LAST_VALUETYPE && MemVT < MVT::LAST_VALUETYPE &&
996 "Table isn't big enough!");
997 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1000 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1001 /// does not work with the specified type and indicate what to do abort
1002 /// it. NOTE: All indexed mode loads are initialized to Expand in
1003 /// TargetLowering.cpp
1004 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1005 LegalizeAction Action) {
1006 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1007 (unsigned)Action < 0xf && "Table isn't big enough!");
1008 // Load action are kept in the upper half.
1009 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1010 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1013 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1014 /// does not work with the specified type and indicate what to do about
1015 /// it. NOTE: All indexed mode stores are initialized to Expand in
1016 /// TargetLowering.cpp
1017 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1018 LegalizeAction Action) {
1019 assert(VT < MVT::LAST_VALUETYPE && IdxMode < ISD::LAST_INDEXED_MODE &&
1020 (unsigned)Action < 0xf && "Table isn't big enough!");
1021 // Store action are kept in the lower half.
1022 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1023 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1026 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1027 /// supported on the target and indicate what to do about it.
1028 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1029 LegalizeAction Action) {
1030 assert(VT < MVT::LAST_VALUETYPE &&
1031 (unsigned)CC < array_lengthof(CondCodeActions) &&
1032 "Table isn't big enough!");
1033 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 64bit
1034 /// value and the upper 27 bits index into the second dimension of the
1035 /// array to select what 64bit value to use.
1036 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5]
1037 &= ~(uint64_t(3UL) << (VT.SimpleTy & 0x1F)*2);
1038 CondCodeActions[(unsigned)CC][VT.SimpleTy >> 5]
1039 |= (uint64_t)Action << (VT.SimpleTy & 0x1F)*2;
1042 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1043 /// promotion code defaults to trying a larger integer/fp until it can find
1044 /// one that works. If that default is insufficient, this method can be used
1045 /// by the target to override the default.
1046 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1047 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1050 /// setTargetDAGCombine - Targets should invoke this method for each target
1051 /// independent node that they want to provide a custom DAG combiner for by
1052 /// implementing the PerformDAGCombine virtual method.
1053 void setTargetDAGCombine(ISD::NodeType NT) {
1054 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1055 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1058 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1059 /// bytes); default is 200
1060 void setJumpBufSize(unsigned Size) {
1064 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1065 /// alignment (in bytes); default is 0
1066 void setJumpBufAlignment(unsigned Align) {
1067 JumpBufAlignment = Align;
1070 /// setMinFunctionAlignment - Set the target's minimum function alignment (in
1072 void setMinFunctionAlignment(unsigned Align) {
1073 MinFunctionAlignment = Align;
1076 /// setPrefFunctionAlignment - Set the target's preferred function alignment.
1077 /// This should be set if there is a performance benefit to
1078 /// higher-than-minimum alignment (in log2(bytes))
1079 void setPrefFunctionAlignment(unsigned Align) {
1080 PrefFunctionAlignment = Align;
1083 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1084 /// alignment is zero, it means the target does not care about loop alignment.
1085 /// The alignment is specified in log2(bytes).
1086 void setPrefLoopAlignment(unsigned Align) {
1087 PrefLoopAlignment = Align;
1090 /// setMinStackArgumentAlignment - Set the minimum stack alignment of an
1091 /// argument (in log2(bytes)).
1092 void setMinStackArgumentAlignment(unsigned Align) {
1093 MinStackArgumentAlignment = Align;
1096 /// setInsertFencesForAtomic - Set if the DAG builder should
1097 /// automatically insert fences and reduce the order of atomic memory
1098 /// operations to Monotonic.
1099 void setInsertFencesForAtomic(bool fence) {
1100 InsertFencesForAtomic = fence;
1104 //===--------------------------------------------------------------------===//
1105 // Addressing mode description hooks (used by LSR etc).
1108 /// GetAddrModeArguments - CodeGenPrepare sinks address calculations into the
1109 /// same BB as Load/Store instructions reading the address. This allows as
1110 /// much computation as possible to be done in the address mode for that
1111 /// operand. This hook lets targets also pass back when this should be done
1112 /// on intrinsics which load/store.
1113 virtual bool GetAddrModeArguments(IntrinsicInst *I,
1114 SmallVectorImpl<Value*> &Ops,
1115 Type *&AccessTy) const {
1119 /// AddrMode - This represents an addressing mode of:
1120 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1121 /// If BaseGV is null, there is no BaseGV.
1122 /// If BaseOffs is zero, there is no base offset.
1123 /// If HasBaseReg is false, there is no base register.
1124 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1128 GlobalValue *BaseGV;
1132 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1135 /// isLegalAddressingMode - Return true if the addressing mode represented by
1136 /// AM is legal for this target, for a load/store of the specified type.
1137 /// The type may be VoidTy, in which case only return true if the addressing
1138 /// mode is legal for a load/store of any legal type.
1139 /// TODO: Handle pre/postinc as well.
1140 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
1142 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1143 /// icmp immediate, that is the target has icmp instructions which can compare
1144 /// a register against the immediate without having to materialize the
1145 /// immediate into a register.
1146 virtual bool isLegalICmpImmediate(int64_t) const {
1150 /// isLegalAddImmediate - Return true if the specified immediate is legal
1151 /// add immediate, that is the target has add instructions which can add
1152 /// a register with the immediate without having to materialize the
1153 /// immediate into a register.
1154 virtual bool isLegalAddImmediate(int64_t) const {
1158 /// isTruncateFree - Return true if it's free to truncate a value of
1159 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1160 /// register EAX to i16 by referencing its sub-register AX.
1161 virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1165 virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
1169 /// isZExtFree - Return true if any actual instruction that defines a
1170 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1171 /// register. This does not necessarily include registers defined in
1172 /// unknown ways, such as incoming arguments, or copies from unknown
1173 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1174 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1175 /// all instructions that define 32-bit values implicit zero-extend the
1176 /// result out to 64 bits.
1177 virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
1181 virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
1185 /// isZExtFree - Return true if zero-extending the specific node Val to type
1186 /// VT2 is free (either because it's implicitly zero-extended such as ARM
1187 /// ldrb / ldrh or because it's folded such as X86 zero-extending loads).
1188 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1189 return isZExtFree(Val.getValueType(), VT2);
1192 /// isFNegFree - Return true if an fneg operation is free to the point where
1193 /// it is never worthwhile to replace it with a bitwise operation.
1194 virtual bool isFNegFree(EVT) const {
1198 /// isFAbsFree - Return true if an fneg operation is free to the point where
1199 /// it is never worthwhile to replace it with a bitwise operation.
1200 virtual bool isFAbsFree(EVT) const {
1204 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
1205 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
1206 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
1207 /// is expanded to mul + add.
1208 virtual bool isFMAFasterThanMulAndAdd(EVT) const {
1212 /// isNarrowingProfitable - Return true if it's profitable to narrow
1213 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1214 /// from i32 to i8 but not from i32 to i16.
1215 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1219 //===--------------------------------------------------------------------===//
1220 // Runtime Library hooks
1223 /// setLibcallName - Rename the default libcall routine name for the specified
1225 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1226 LibcallRoutineNames[Call] = Name;
1229 /// getLibcallName - Get the libcall routine name for the specified libcall.
1231 const char *getLibcallName(RTLIB::Libcall Call) const {
1232 return LibcallRoutineNames[Call];
1235 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1236 /// result of the comparison libcall against zero.
1237 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1238 CmpLibcallCCs[Call] = CC;
1241 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1242 /// the comparison libcall against zero.
1243 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1244 return CmpLibcallCCs[Call];
1247 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1248 /// specified libcall.
1249 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1250 LibcallCallingConvs[Call] = CC;
1253 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1254 /// specified libcall.
1255 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1256 return LibcallCallingConvs[Call];
1260 const TargetMachine &TM;
1261 const DataLayout *TD;
1262 const TargetLoweringObjectFile &TLOF;
1264 /// PointerTy - The type to use for pointers for the default address space,
1265 /// usually i32 or i64.
1269 /// IsLittleEndian - True if this is a little endian target.
1271 bool IsLittleEndian;
1273 /// SelectIsExpensive - Tells the code generator not to expand operations
1274 /// into sequences that use the select operations if possible.
1275 bool SelectIsExpensive;
1277 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1278 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1279 /// a real cost model is in place. If we ever optimize for size, this will be
1280 /// set to true unconditionally.
1283 /// BypassSlowDivMap - Tells the code generator to bypass slow divide or
1284 /// remainder instructions. For example, BypassSlowDivWidths[32,8] tells the
1285 /// code generator to bypass 32-bit integer div/rem with an 8-bit unsigned
1286 /// integer div/rem when the operands are positive and less than 256.
1287 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1289 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1290 /// srl/add/sra for a signed divide by power of two, and let the target handle
1292 bool Pow2DivIsCheap;
1294 /// JumpIsExpensive - Tells the code generator that it shouldn't generate
1295 /// extra flow control instructions and should attempt to combine flow
1296 /// control instructions via predication.
1297 bool JumpIsExpensive;
1299 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1300 /// llvm.setjmp. Defaults to false.
1301 bool UseUnderscoreSetJmp;
1303 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1304 /// llvm.longjmp. Defaults to false.
1305 bool UseUnderscoreLongJmp;
1307 /// SupportJumpTables - Whether the target can generate code for jumptables.
1308 /// If it's not true, then each jumptable must be lowered into if-then-else's.
1309 bool SupportJumpTables;
1311 /// MinimumJumpTableEntries - Number of blocks threshold to use jump tables.
1312 int MinimumJumpTableEntries;
1314 /// BooleanContents - Information about the contents of the high-bits in
1315 /// boolean values held in a type wider than i1. See getBooleanContents.
1316 BooleanContent BooleanContents;
1317 /// BooleanVectorContents - Information about the contents of the high-bits
1318 /// in boolean vector values when the element type is wider than i1. See
1319 /// getBooleanContents.
1320 BooleanContent BooleanVectorContents;
1322 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1323 /// total cycles or lowest register usage.
1324 Sched::Preference SchedPreferenceInfo;
1326 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1327 unsigned JumpBufSize;
1329 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1331 unsigned JumpBufAlignment;
1333 /// MinStackArgumentAlignment - The minimum alignment that any argument
1334 /// on the stack needs to have.
1336 unsigned MinStackArgumentAlignment;
1338 /// MinFunctionAlignment - The minimum function alignment (used when
1339 /// optimizing for size, and to prevent explicitly provided alignment
1340 /// from leading to incorrect code).
1342 unsigned MinFunctionAlignment;
1344 /// PrefFunctionAlignment - The preferred function alignment (used when
1345 /// alignment unspecified and optimizing for speed).
1347 unsigned PrefFunctionAlignment;
1349 /// PrefLoopAlignment - The preferred loop alignment.
1351 unsigned PrefLoopAlignment;
1353 /// InsertFencesForAtomic - Whether the DAG builder should automatically
1354 /// insert fences and reduce ordering for atomics. (This will be set for
1355 /// for most architectures with weak memory ordering.)
1356 bool InsertFencesForAtomic;
1358 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1359 /// specifies the register that llvm.savestack/llvm.restorestack should save
1361 unsigned StackPointerRegisterToSaveRestore;
1363 /// ExceptionPointerRegister - If set to a physical register, this specifies
1364 /// the register that receives the exception address on entry to a landing
1366 unsigned ExceptionPointerRegister;
1368 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1369 /// the register that receives the exception typeid on entry to a landing
1371 unsigned ExceptionSelectorRegister;
1373 /// RegClassForVT - This indicates the default register class to use for
1374 /// each ValueType the target supports natively.
1375 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1376 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1377 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1379 /// RepRegClassForVT - This indicates the "representative" register class to
1380 /// use for each ValueType the target supports natively. This information is
1381 /// used by the scheduler to track register pressure. By default, the
1382 /// representative register class is the largest legal super-reg register
1383 /// class of the register class of the specified type. e.g. On x86, i8, i16,
1384 /// and i32's representative class would be GR32.
1385 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1387 /// RepRegClassCostForVT - This indicates the "cost" of the "representative"
1388 /// register class for each ValueType. The cost is used by the scheduler to
1389 /// approximate register pressure.
1390 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1392 /// TransformToType - For any value types we are promoting or expanding, this
1393 /// contains the value type that we are changing to. For Expanded types, this
1394 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1395 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1396 /// by the system, this holds the same type (e.g. i32 -> i32).
1397 MVT TransformToType[MVT::LAST_VALUETYPE];
1399 /// OpActions - For each operation and each value type, keep a LegalizeAction
1400 /// that indicates how instruction selection should deal with the operation.
1401 /// Most operations are Legal (aka, supported natively by the target), but
1402 /// operations that are not should be described. Note that operations on
1403 /// non-legal value types are not described here.
1404 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1406 /// LoadExtActions - For each load extension type and each value type,
1407 /// keep a LegalizeAction that indicates how instruction selection should deal
1408 /// with a load of a specific value type and extension type.
1409 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1411 /// TruncStoreActions - For each value type pair keep a LegalizeAction that
1412 /// indicates whether a truncating store of a specific value type and
1413 /// truncating type is legal.
1414 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1416 /// IndexedModeActions - For each indexed mode and each value type,
1417 /// keep a pair of LegalizeAction that indicates how instruction
1418 /// selection should deal with the load / store. The first dimension is the
1419 /// value_type for the reference. The second dimension represents the various
1420 /// modes for load store.
1421 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1423 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1424 /// LegalizeAction that indicates how instruction selection should
1425 /// deal with the condition code.
1426 /// Because each CC action takes up 2 bits, we need to have the array size
1427 /// be large enough to fit all of the value types. This can be done by
1428 /// dividing the MVT::LAST_VALUETYPE by 32 and adding one.
1429 uint64_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE / 32) + 1];
1431 ValueTypeActionImpl ValueTypeActions;
1435 getTypeConversion(LLVMContext &Context, EVT VT) const {
1436 // If this is a simple type, use the ComputeRegisterProp mechanism.
1437 if (VT.isSimple()) {
1438 MVT SVT = VT.getSimpleVT();
1439 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
1440 MVT NVT = TransformToType[SVT.SimpleTy];
1441 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
1445 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger)
1446 && "Promote may not follow Expand or Promote");
1448 if (LA == TypeSplitVector)
1449 return LegalizeKind(LA, EVT::getVectorVT(Context,
1450 SVT.getVectorElementType(),
1451 SVT.getVectorNumElements()/2));
1452 if (LA == TypeScalarizeVector)
1453 return LegalizeKind(LA, SVT.getVectorElementType());
1454 return LegalizeKind(LA, NVT);
1457 // Handle Extended Scalar Types.
1458 if (!VT.isVector()) {
1459 assert(VT.isInteger() && "Float types must be simple");
1460 unsigned BitSize = VT.getSizeInBits();
1461 // First promote to a power-of-two size, then expand if necessary.
1462 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
1463 EVT NVT = VT.getRoundIntegerType(Context);
1464 assert(NVT != VT && "Unable to round integer VT");
1465 LegalizeKind NextStep = getTypeConversion(Context, NVT);
1466 // Avoid multi-step promotion.
1467 if (NextStep.first == TypePromoteInteger) return NextStep;
1468 // Return rounded integer type.
1469 return LegalizeKind(TypePromoteInteger, NVT);
1472 return LegalizeKind(TypeExpandInteger,
1473 EVT::getIntegerVT(Context, VT.getSizeInBits()/2));
1476 // Handle vector types.
1477 unsigned NumElts = VT.getVectorNumElements();
1478 EVT EltVT = VT.getVectorElementType();
1480 // Vectors with only one element are always scalarized.
1482 return LegalizeKind(TypeScalarizeVector, EltVT);
1484 // Try to widen vector elements until a legal type is found.
1485 if (EltVT.isInteger()) {
1486 // Vectors with a number of elements that is not a power of two are always
1487 // widened, for example <3 x float> -> <4 x float>.
1488 if (!VT.isPow2VectorType()) {
1489 NumElts = (unsigned)NextPowerOf2(NumElts);
1490 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
1491 return LegalizeKind(TypeWidenVector, NVT);
1494 // Examine the element type.
1495 LegalizeKind LK = getTypeConversion(Context, EltVT);
1497 // If type is to be expanded, split the vector.
1498 // <4 x i140> -> <2 x i140>
1499 if (LK.first == TypeExpandInteger)
1500 return LegalizeKind(TypeSplitVector,
1501 EVT::getVectorVT(Context, EltVT, NumElts / 2));
1503 // Promote the integer element types until a legal vector type is found
1504 // or until the element integer type is too big. If a legal type was not
1505 // found, fallback to the usual mechanism of widening/splitting the
1507 EVT OldEltVT = EltVT;
1509 // Increase the bitwidth of the element to the next pow-of-two
1510 // (which is greater than 8 bits).
1511 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits()
1512 ).getRoundIntegerType(Context);
1514 // Stop trying when getting a non-simple element type.
1515 // Note that vector elements may be greater than legal vector element
1516 // types. Example: X86 XMM registers hold 64bit element on 32bit systems.
1517 if (!EltVT.isSimple()) break;
1519 // Build a new vector type and check if it is legal.
1520 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1521 // Found a legal promoted vector type.
1522 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1523 return LegalizeKind(TypePromoteInteger,
1524 EVT::getVectorVT(Context, EltVT, NumElts));
1527 // Reset the type to the unexpanded type if we did not find a legal vector
1528 // type with a promoted vector element type.
1532 // Try to widen the vector until a legal type is found.
1533 // If there is no wider legal type, split the vector.
1535 // Round up to the next power of 2.
1536 NumElts = (unsigned)NextPowerOf2(NumElts);
1538 // If there is no simple vector type with this many elements then there
1539 // cannot be a larger legal vector type. Note that this assumes that
1540 // there are no skipped intermediate vector types in the simple types.
1541 if (!EltVT.isSimple()) break;
1542 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1543 if (LargerVector == MVT()) break;
1545 // If this type is legal then widen the vector.
1546 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1547 return LegalizeKind(TypeWidenVector, LargerVector);
1550 // Widen odd vectors to next power of two.
1551 if (!VT.isPow2VectorType()) {
1552 EVT NVT = VT.getPow2VectorType(Context);
1553 return LegalizeKind(TypeWidenVector, NVT);
1556 // Vectors with illegal element types are expanded.
1557 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1558 return LegalizeKind(TypeSplitVector, NVT);
1562 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1564 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1565 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1566 /// which sets a bit in this array.
1568 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1570 /// PromoteToType - For operations that must be promoted to a specific type,
1571 /// this holds the destination type. This map should be sparse, so don't hold
1574 /// Targets add entries to this map with AddPromotedToType(..), clients access
1575 /// this with getTypeToPromoteTo(..).
1576 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1579 /// LibcallRoutineNames - Stores the name each libcall.
1581 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1583 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1584 /// of each of the comparison libcall against zero.
1585 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1587 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1589 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1592 /// When lowering \@llvm.memset this field specifies the maximum number of
1593 /// store operations that may be substituted for the call to memset. Targets
1594 /// must set this value based on the cost threshold for that target. Targets
1595 /// should assume that the memset will be done using as many of the largest
1596 /// store operations first, followed by smaller ones, if necessary, per
1597 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1598 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1599 /// store. This only applies to setting a constant array of a constant size.
1600 /// @brief Specify maximum number of store instructions per memset call.
1601 unsigned MaxStoresPerMemset;
1603 /// Maximum number of stores operations that may be substituted for the call
1604 /// to memset, used for functions with OptSize attribute.
1605 unsigned MaxStoresPerMemsetOptSize;
1607 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1608 /// store operations that may be substituted for a call to memcpy. Targets
1609 /// must set this value based on the cost threshold for that target. Targets
1610 /// should assume that the memcpy will be done using as many of the largest
1611 /// store operations first, followed by smaller ones, if necessary, per
1612 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1613 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1614 /// and one 1-byte store. This only applies to copying a constant array of
1616 /// @brief Specify maximum bytes of store instructions per memcpy call.
1617 unsigned MaxStoresPerMemcpy;
1619 /// Maximum number of store operations that may be substituted for a call
1620 /// to memcpy, used for functions with OptSize attribute.
1621 unsigned MaxStoresPerMemcpyOptSize;
1623 /// When lowering \@llvm.memmove this field specifies the maximum number of
1624 /// store instructions that may be substituted for a call to memmove. Targets
1625 /// must set this value based on the cost threshold for that target. Targets
1626 /// should assume that the memmove will be done using as many of the largest
1627 /// store operations first, followed by smaller ones, if necessary, per
1628 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1629 /// with 8-bit alignment would result in nine 1-byte stores. This only
1630 /// applies to copying a constant array of constant size.
1631 /// @brief Specify maximum bytes of store instructions per memmove call.
1632 unsigned MaxStoresPerMemmove;
1634 /// Maximum number of store instructions that may be substituted for a call
1635 /// to memmove, used for functions with OpSize attribute.
1636 unsigned MaxStoresPerMemmoveOptSize;
1638 /// PredictableSelectIsExpensive - Tells the code generator that select is
1639 /// more expensive than a branch if the branch is usually predicted right.
1640 bool PredictableSelectIsExpensive;
1643 /// isLegalRC - Return true if the value types that can be represented by the
1644 /// specified register class are all legal.
1645 bool isLegalRC(const TargetRegisterClass *RC) const;
1648 //===----------------------------------------------------------------------===//
1649 /// TargetLowering - This class defines information used to lower LLVM code to
1650 /// legal SelectionDAG operators that the target instruction selector can accept
1653 /// This class also defines callbacks that targets must implement to lower
1654 /// target-specific constructs to SelectionDAG operators.
1656 class TargetLowering : public TargetLoweringBase {
1657 TargetLowering(const TargetLowering&) LLVM_DELETED_FUNCTION;
1658 void operator=(const TargetLowering&) LLVM_DELETED_FUNCTION;
1661 /// NOTE: The constructor takes ownership of TLOF.
1662 explicit TargetLowering(const TargetMachine &TM,
1663 const TargetLoweringObjectFile *TLOF);
1665 /// getPreIndexedAddressParts - returns true by value, base pointer and
1666 /// offset pointer and addressing mode by reference if the node's address
1667 /// can be legally represented as pre-indexed load / store address.
1668 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
1669 SDValue &/*Offset*/,
1670 ISD::MemIndexedMode &/*AM*/,
1671 SelectionDAG &/*DAG*/) const {
1675 /// getPostIndexedAddressParts - returns true by value, base pointer and
1676 /// offset pointer and addressing mode by reference if this node can be
1677 /// combined with a load / store to form a post-indexed load / store.
1678 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
1679 SDValue &/*Base*/, SDValue &/*Offset*/,
1680 ISD::MemIndexedMode &/*AM*/,
1681 SelectionDAG &/*DAG*/) const {
1685 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
1686 /// current function. The returned value is a member of the
1687 /// MachineJumpTableInfo::JTEntryKind enum.
1688 virtual unsigned getJumpTableEncoding() const;
1690 virtual const MCExpr *
1691 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
1692 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
1693 MCContext &/*Ctx*/) const {
1694 llvm_unreachable("Need to implement this hook if target has custom JTIs");
1697 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
1699 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
1700 SelectionDAG &DAG) const;
1702 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
1703 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
1705 virtual const MCExpr *
1706 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
1707 unsigned JTI, MCContext &Ctx) const;
1709 /// isOffsetFoldingLegal - Return true if folding a constant offset
1710 /// with the given GlobalAddress is legal. It is frequently not legal in
1711 /// PIC relocation models.
1712 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
1714 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
1715 SDValue &Chain) const;
1717 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
1718 SDValue &NewLHS, SDValue &NewRHS,
1719 ISD::CondCode &CCCode, SDLoc DL) const;
1721 SDValue makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT,
1722 const SDValue *Ops, unsigned NumOps,
1723 bool isSigned, SDLoc dl) const;
1725 //===--------------------------------------------------------------------===//
1726 // TargetLowering Optimization Methods
1729 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
1730 /// SDValues for returning information from TargetLowering to its clients
1731 /// that want to combine
1732 struct TargetLoweringOpt {
1739 explicit TargetLoweringOpt(SelectionDAG &InDAG,
1741 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
1743 bool LegalTypes() const { return LegalTys; }
1744 bool LegalOperations() const { return LegalOps; }
1746 bool CombineTo(SDValue O, SDValue N) {
1752 /// ShrinkDemandedConstant - Check to see if the specified operand of the
1753 /// specified instruction is a constant integer. If so, check to see if
1754 /// there are any bits set in the constant that are not demanded. If so,
1755 /// shrink the constant and return true.
1756 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
1758 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
1759 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
1760 /// cast, but it could be generalized for targets with other types of
1761 /// implicit widening casts.
1762 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
1766 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
1767 /// DemandedMask bits of the result of Op are ever used downstream. If we can
1768 /// use this information to simplify Op, create a new simplified DAG node and
1769 /// return true, returning the original and new nodes in Old and New.
1770 /// Otherwise, analyze the expression and return a mask of KnownOne and
1771 /// KnownZero bits for the expression (used to simplify the caller).
1772 /// The KnownZero/One bits may only be accurate for those bits in the
1774 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
1775 APInt &KnownZero, APInt &KnownOne,
1776 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
1778 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
1779 /// Mask are known to be either zero or one and return them in the
1780 /// KnownZero/KnownOne bitsets.
1781 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
1784 const SelectionDAG &DAG,
1785 unsigned Depth = 0) const;
1787 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
1788 /// targets that want to expose additional information about sign bits to the
1790 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
1791 unsigned Depth = 0) const;
1793 struct DAGCombinerInfo {
1794 void *DC; // The DAG Combiner object.
1796 bool CalledByLegalizer;
1800 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
1801 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
1803 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
1804 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
1805 bool isAfterLegalizeVectorOps() const {
1806 return Level == AfterLegalizeDAG;
1808 CombineLevel getDAGCombineLevel() { return Level; }
1809 bool isCalledByLegalizer() const { return CalledByLegalizer; }
1811 void AddToWorklist(SDNode *N);
1812 void RemoveFromWorklist(SDNode *N);
1813 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
1815 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
1816 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
1818 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
1821 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
1822 /// and cc. If it is unable to simplify it, return a null SDValue.
1823 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1824 ISD::CondCode Cond, bool foldBooleans,
1825 DAGCombinerInfo &DCI, SDLoc dl) const;
1827 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
1828 /// node is a GlobalAddress + offset.
1830 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
1832 /// PerformDAGCombine - This method will be invoked for all target nodes and
1833 /// for any target-independent nodes that the target has registered with
1836 /// The semantics are as follows:
1838 /// SDValue.Val == 0 - No change was made
1839 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
1840 /// otherwise - N should be replaced by the returned Operand.
1842 /// In addition, methods provided by DAGCombinerInfo may be used to perform
1843 /// more complex transformations.
1845 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
1847 /// isTypeDesirableForOp - Return true if the target has native support for
1848 /// the specified value type and it is 'desirable' to use the type for the
1849 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
1850 /// instruction encodings are longer and some i16 instructions are slow.
1851 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
1852 // By default, assume all legal types are desirable.
1853 return isTypeLegal(VT);
1856 /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner
1857 /// to transform a floating point op of specified opcode to a equivalent op of
1858 /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM.
1859 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
1864 /// IsDesirableToPromoteOp - This method query the target whether it is
1865 /// beneficial for dag combiner to promote the specified node. If true, it
1866 /// should return the desired promotion type by reference.
1867 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
1871 //===--------------------------------------------------------------------===//
1872 // Lowering methods - These methods must be implemented by targets so that
1873 // the SelectionDAGBuilder code knows how to lower these.
1876 /// LowerFormalArguments - This hook must be implemented to lower the
1877 /// incoming (formal) arguments, described by the Ins array, into the
1878 /// specified DAG. The implementation should fill in the InVals array
1879 /// with legal-type argument values, and return the resulting token
1883 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
1885 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
1886 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
1887 SmallVectorImpl<SDValue> &/*InVals*/) const {
1888 llvm_unreachable("Not Implemented");
1891 struct ArgListEntry {
1900 bool isReturned : 1;
1903 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1904 isSRet(false), isNest(false), isByVal(false), isReturned(false),
1907 typedef std::vector<ArgListEntry> ArgListTy;
1909 /// CallLoweringInfo - This structure contains all information that is
1910 /// necessary for lowering calls. It is passed to TLI::LowerCallTo when the
1911 /// SelectionDAG builder needs to lower a call, and targets will see this
1912 /// struct in their LowerCall implementation.
1913 struct CallLoweringInfo {
1920 bool DoesNotReturn : 1;
1921 bool IsReturnValueUsed : 1;
1923 // IsTailCall should be modified by implementations of
1924 // TargetLowering::LowerCall that perform tail call conversions.
1927 unsigned NumFixedArgs;
1928 CallingConv::ID CallConv;
1933 ImmutableCallSite *CS;
1934 SmallVector<ISD::OutputArg, 32> Outs;
1935 SmallVector<SDValue, 32> OutVals;
1936 SmallVector<ISD::InputArg, 32> Ins;
1939 /// CallLoweringInfo - Constructs a call lowering context based on the
1940 /// ImmutableCallSite \p cs.
1941 CallLoweringInfo(SDValue chain, Type *retTy,
1942 FunctionType *FTy, bool isTailCall, SDValue callee,
1943 ArgListTy &args, SelectionDAG &dag, SDLoc dl,
1944 ImmutableCallSite &cs)
1945 : Chain(chain), RetTy(retTy), RetSExt(cs.paramHasAttr(0, Attribute::SExt)),
1946 RetZExt(cs.paramHasAttr(0, Attribute::ZExt)), IsVarArg(FTy->isVarArg()),
1947 IsInReg(cs.paramHasAttr(0, Attribute::InReg)),
1948 DoesNotReturn(cs.doesNotReturn()),
1949 IsReturnValueUsed(!cs.getInstruction()->use_empty()),
1950 IsTailCall(isTailCall), NumFixedArgs(FTy->getNumParams()),
1951 CallConv(cs.getCallingConv()), Callee(callee), Args(args), DAG(dag),
1954 /// CallLoweringInfo - Constructs a call lowering context based on the
1955 /// provided call information.
1956 CallLoweringInfo(SDValue chain, Type *retTy, bool retSExt, bool retZExt,
1957 bool isVarArg, bool isInReg, unsigned numFixedArgs,
1958 CallingConv::ID callConv, bool isTailCall,
1959 bool doesNotReturn, bool isReturnValueUsed, SDValue callee,
1960 ArgListTy &args, SelectionDAG &dag, SDLoc dl)
1961 : Chain(chain), RetTy(retTy), RetSExt(retSExt), RetZExt(retZExt),
1962 IsVarArg(isVarArg), IsInReg(isInReg), DoesNotReturn(doesNotReturn),
1963 IsReturnValueUsed(isReturnValueUsed), IsTailCall(isTailCall),
1964 NumFixedArgs(numFixedArgs), CallConv(callConv), Callee(callee),
1965 Args(args), DAG(dag), DL(dl), CS(NULL) {}
1968 /// LowerCallTo - This function lowers an abstract call to a function into an
1969 /// actual call. This returns a pair of operands. The first element is the
1970 /// return value for the function (if RetTy is not VoidTy). The second
1971 /// element is the outgoing token chain. It calls LowerCall to do the actual
1973 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
1975 /// LowerCall - This hook must be implemented to lower calls into the
1976 /// the specified DAG. The outgoing arguments to the call are described
1977 /// by the Outs array, and the values to be returned by the call are
1978 /// described by the Ins array. The implementation should fill in the
1979 /// InVals array with legal-type return values from the call, and return
1980 /// the resulting token chain value.
1982 LowerCall(CallLoweringInfo &/*CLI*/,
1983 SmallVectorImpl<SDValue> &/*InVals*/) const {
1984 llvm_unreachable("Not Implemented");
1987 /// HandleByVal - Target-specific cleanup for formal ByVal parameters.
1988 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
1990 /// CanLowerReturn - This hook should be implemented to check whether the
1991 /// return values described by the Outs array can fit into the return
1992 /// registers. If false is returned, an sret-demotion is performed.
1994 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
1995 MachineFunction &/*MF*/, bool /*isVarArg*/,
1996 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
1997 LLVMContext &/*Context*/) const
1999 // Return true by default to get preexisting behavior.
2003 /// LowerReturn - This hook must be implemented to lower outgoing
2004 /// return values, described by the Outs array, into the specified
2005 /// DAG. The implementation should return the resulting token chain
2009 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2011 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2012 const SmallVectorImpl<SDValue> &/*OutVals*/,
2013 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2014 llvm_unreachable("Not Implemented");
2017 /// isUsedByReturnOnly - Return true if result of the specified node is used
2018 /// by a return node only. It also compute and return the input chain for the
2020 /// This is used to determine whether it is possible
2021 /// to codegen a libcall as tail call at legalization time.
2022 virtual bool isUsedByReturnOnly(SDNode *, SDValue &Chain) const {
2026 /// mayBeEmittedAsTailCall - Return true if the target may be able emit the
2027 /// call instruction as a tail call. This is used by optimization passes to
2028 /// determine if it's profitable to duplicate return instructions to enable
2029 /// tailcall optimization.
2030 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2034 /// getTypeForExtArgOrReturn - Return the type that should be used to zero or
2035 /// sign extend a zeroext/signext integer argument or return value.
2036 /// FIXME: Most C calling convention requires the return type to be promoted,
2037 /// but this is not true all the time, e.g. i1 on x86-64. It is also not
2038 /// necessary for non-C calling conventions. The frontend should handle this
2039 /// and include all of the necessary information.
2040 virtual MVT getTypeForExtArgOrReturn(MVT VT,
2041 ISD::NodeType /*ExtendKind*/) const {
2042 MVT MinVT = getRegisterType(MVT::i32);
2043 return VT.bitsLT(MinVT) ? MinVT : VT;
2046 /// LowerOperationWrapper - This callback is invoked by the type legalizer
2047 /// to legalize nodes with an illegal operand type but legal result types.
2048 /// It replaces the LowerOperation callback in the type Legalizer.
2049 /// The reason we can not do away with LowerOperation entirely is that
2050 /// LegalizeDAG isn't yet ready to use this callback.
2051 /// TODO: Consider merging with ReplaceNodeResults.
2053 /// The target places new result values for the node in Results (their number
2054 /// and types must exactly match those of the original return values of
2055 /// the node), or leaves Results empty, which indicates that the node is not
2056 /// to be custom lowered after all.
2057 /// The default implementation calls LowerOperation.
2058 virtual void LowerOperationWrapper(SDNode *N,
2059 SmallVectorImpl<SDValue> &Results,
2060 SelectionDAG &DAG) const;
2062 /// LowerOperation - This callback is invoked for operations that are
2063 /// unsupported by the target, which are registered to use 'custom' lowering,
2064 /// and whose defined values are all legal.
2065 /// If the target has no operations that require custom lowering, it need not
2066 /// implement this. The default implementation of this aborts.
2067 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2069 /// ReplaceNodeResults - This callback is invoked when a node result type is
2070 /// illegal for the target, and the operation was registered to use 'custom'
2071 /// lowering for that result type. The target places new result values for
2072 /// the node in Results (their number and types must exactly match those of
2073 /// the original return values of the node), or leaves Results empty, which
2074 /// indicates that the node is not to be custom lowered after all.
2076 /// If the target has no operations that require custom lowering, it need not
2077 /// implement this. The default implementation aborts.
2078 virtual void ReplaceNodeResults(SDNode * /*N*/,
2079 SmallVectorImpl<SDValue> &/*Results*/,
2080 SelectionDAG &/*DAG*/) const {
2081 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2084 /// getTargetNodeName() - This method returns the name of a target specific
2086 virtual const char *getTargetNodeName(unsigned Opcode) const;
2088 /// createFastISel - This method returns a target specific FastISel object,
2089 /// or null if the target does not support "fast" ISel.
2090 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2091 const TargetLibraryInfo *) const {
2095 //===--------------------------------------------------------------------===//
2096 // Inline Asm Support hooks
2099 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
2100 /// call to be explicit llvm code if it wants to. This is useful for
2101 /// turning simple inline asms into LLVM intrinsics, which gives the
2102 /// compiler more information about the behavior of the code.
2103 virtual bool ExpandInlineAsm(CallInst *) const {
2107 enum ConstraintType {
2108 C_Register, // Constraint represents specific register(s).
2109 C_RegisterClass, // Constraint represents any of register(s) in class.
2110 C_Memory, // Memory constraint.
2111 C_Other, // Something else.
2112 C_Unknown // Unsupported constraint.
2115 enum ConstraintWeight {
2117 CW_Invalid = -1, // No match.
2118 CW_Okay = 0, // Acceptable.
2119 CW_Good = 1, // Good weight.
2120 CW_Better = 2, // Better weight.
2121 CW_Best = 3, // Best weight.
2123 // Well-known weights.
2124 CW_SpecificReg = CW_Okay, // Specific register operands.
2125 CW_Register = CW_Good, // Register operands.
2126 CW_Memory = CW_Better, // Memory operands.
2127 CW_Constant = CW_Best, // Constant operand.
2128 CW_Default = CW_Okay // Default or don't know type.
2131 /// AsmOperandInfo - This contains information for each constraint that we are
2133 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2134 /// ConstraintCode - This contains the actual string for the code, like "m".
2135 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
2136 /// most closely matches the operand.
2137 std::string ConstraintCode;
2139 /// ConstraintType - Information about the constraint code, e.g. Register,
2140 /// RegisterClass, Memory, Other, Unknown.
2141 TargetLowering::ConstraintType ConstraintType;
2143 /// CallOperandval - If this is the result output operand or a
2144 /// clobber, this is null, otherwise it is the incoming operand to the
2145 /// CallInst. This gets modified as the asm is processed.
2146 Value *CallOperandVal;
2148 /// ConstraintVT - The ValueType for the operand value.
2151 /// isMatchingInputConstraint - Return true of this is an input operand that
2152 /// is a matching constraint like "4".
2153 bool isMatchingInputConstraint() const;
2155 /// getMatchedOperand - If this is an input matching constraint, this method
2156 /// returns the output operand it matches.
2157 unsigned getMatchedOperand() const;
2159 /// Copy constructor for copying from an AsmOperandInfo.
2160 AsmOperandInfo(const AsmOperandInfo &info)
2161 : InlineAsm::ConstraintInfo(info),
2162 ConstraintCode(info.ConstraintCode),
2163 ConstraintType(info.ConstraintType),
2164 CallOperandVal(info.CallOperandVal),
2165 ConstraintVT(info.ConstraintVT) {
2168 /// Copy constructor for copying from a ConstraintInfo.
2169 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
2170 : InlineAsm::ConstraintInfo(info),
2171 ConstraintType(TargetLowering::C_Unknown),
2172 CallOperandVal(0), ConstraintVT(MVT::Other) {
2176 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2178 /// ParseConstraints - Split up the constraint string from the inline
2179 /// assembly value into the specific constraints and their prefixes,
2180 /// and also tie in the associated operand values.
2181 /// If this returns an empty vector, and if the constraint string itself
2182 /// isn't empty, there was an error parsing.
2183 virtual AsmOperandInfoVector ParseConstraints(ImmutableCallSite CS) const;
2185 /// Examine constraint type and operand type and determine a weight value.
2186 /// The operand object must already have been set up with the operand type.
2187 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2188 AsmOperandInfo &info, int maIndex) const;
2190 /// Examine constraint string and operand type and determine a weight value.
2191 /// The operand object must already have been set up with the operand type.
2192 virtual ConstraintWeight getSingleConstraintMatchWeight(
2193 AsmOperandInfo &info, const char *constraint) const;
2195 /// ComputeConstraintToUse - Determines the constraint code and constraint
2196 /// type to use for the specific AsmOperandInfo, setting
2197 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
2198 /// being passed in is available, it can be passed in as Op, otherwise an
2199 /// empty SDValue can be passed.
2200 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2202 SelectionDAG *DAG = 0) const;
2204 /// getConstraintType - Given a constraint, return the type of constraint it
2205 /// is for this target.
2206 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
2208 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
2209 /// {edx}), return the register number and the register class for the
2212 /// Given a register class constraint, like 'r', if this corresponds directly
2213 /// to an LLVM register class, return a register of 0 and the register class
2216 /// This should only be used for C_Register constraints. On error,
2217 /// this returns a register number of 0 and a null register class pointer..
2218 virtual std::pair<unsigned, const TargetRegisterClass*>
2219 getRegForInlineAsmConstraint(const std::string &Constraint,
2222 /// LowerXConstraint - try to replace an X constraint, which matches anything,
2223 /// with another that has more specific requirements based on the type of the
2224 /// corresponding operand. This returns null if there is no replacement to
2226 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2228 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
2229 /// vector. If it is invalid, don't add anything to Ops.
2230 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2231 std::vector<SDValue> &Ops,
2232 SelectionDAG &DAG) const;
2234 //===--------------------------------------------------------------------===//
2235 // Div utility functions
2237 SDValue BuildExactSDIV(SDValue Op1, SDValue Op2, SDLoc dl,
2238 SelectionDAG &DAG) const;
2239 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2240 std::vector<SDNode*> *Created) const;
2241 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG, bool IsAfterLegalization,
2242 std::vector<SDNode*> *Created) const;
2244 //===--------------------------------------------------------------------===//
2245 // Instruction Emitting Hooks
2248 // EmitInstrWithCustomInserter - This method should be implemented by targets
2249 // that mark instructions with the 'usesCustomInserter' flag. These
2250 // instructions are special in various ways, which require special support to
2251 // insert. The specified MachineInstr is created but not inserted into any
2252 // basic blocks, and this method is called to expand it into a sequence of
2253 // instructions, potentially also creating new basic blocks and control flow.
2254 virtual MachineBasicBlock *
2255 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2257 /// AdjustInstrPostInstrSelection - This method should be implemented by
2258 /// targets that mark instructions with the 'hasPostISelHook' flag. These
2259 /// instructions must be adjusted after instruction selection by target hooks.
2260 /// e.g. To fill in optional defs for ARM 's' setting instructions.
2262 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2265 /// GetReturnInfo - Given an LLVM IR type and return type attributes,
2266 /// compute the return value EVTs and flags, and optionally also
2267 /// the offsets, if the return value is being lowered to memory.
2268 void GetReturnInfo(Type* ReturnType, AttributeSet attr,
2269 SmallVectorImpl<ISD::OutputArg> &Outs,
2270 const TargetLowering &TLI);
2272 } // end llvm namespace