1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// This file describes how to lower LLVM code to machine code. This has two
14 /// 1. Which ValueTypes are natively supported by the target.
15 /// 2. Which operations are supported for supported ValueTypes.
16 /// 3. Cost thresholds for alternative implementations of certain operations.
18 /// In addition it has a few other components, like information about FP
21 //===----------------------------------------------------------------------===//
23 #ifndef LLVM_TARGET_TARGETLOWERING_H
24 #define LLVM_TARGET_TARGETLOWERING_H
26 #include "llvm/ADT/DenseMap.h"
27 #include "llvm/CodeGen/DAGCombine.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/CodeGen/SelectionDAGNodes.h"
30 #include "llvm/IR/Attributes.h"
31 #include "llvm/IR/CallSite.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/IRBuilder.h"
34 #include "llvm/IR/InlineAsm.h"
35 #include "llvm/IR/Instructions.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/Target/TargetCallingConv.h"
38 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class ImmutableCallSite;
50 class MachineBasicBlock;
51 class MachineFunction;
53 class MachineJumpTableInfo;
59 template<typename T> class SmallVectorImpl;
61 class TargetRegisterClass;
62 class TargetLibraryInfo;
63 class TargetLoweringObjectFile;
68 None, // No preference
69 Source, // Follow source order.
70 RegPressure, // Scheduling for lowest register pressure.
71 Hybrid, // Scheduling for both latency and register pressure.
72 ILP, // Scheduling for ILP in low register pressure mode.
73 VLIW // Scheduling for VLIW targets.
77 /// This base class for TargetLowering contains the SelectionDAG-independent
78 /// parts that can be used from the rest of CodeGen.
79 class TargetLoweringBase {
80 TargetLoweringBase(const TargetLoweringBase&) = delete;
81 void operator=(const TargetLoweringBase&) = delete;
84 /// This enum indicates whether operations are valid for a target, and if not,
85 /// what action should be used to make them valid.
87 Legal, // The target natively supports this operation.
88 Promote, // This operation should be executed in a larger type.
89 Expand, // Try to expand this to other ops, otherwise use a libcall.
90 Custom // Use the LowerOperation hook to implement custom lowering.
93 /// This enum indicates whether a types are legal for a target, and if not,
94 /// what action should be used to make them valid.
95 enum LegalizeTypeAction {
96 TypeLegal, // The target natively supports this type.
97 TypePromoteInteger, // Replace this integer with a larger one.
98 TypeExpandInteger, // Split this integer into two of half the size.
99 TypeSoftenFloat, // Convert this float to a same size integer type.
100 TypeExpandFloat, // Split this float into two of half the size.
101 TypeScalarizeVector, // Replace this one-element vector with its element.
102 TypeSplitVector, // Split this vector into two of half the size.
103 TypeWidenVector, // This vector should be widened into a larger vector.
104 TypePromoteFloat // Replace this float with a larger one.
107 /// LegalizeKind holds the legalization kind that needs to happen to EVT
108 /// in order to type-legalize it.
109 typedef std::pair<LegalizeTypeAction, EVT> LegalizeKind;
111 /// Enum that describes how the target represents true/false values.
112 enum BooleanContent {
113 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
114 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
115 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
118 /// Enum that describes what type of support for selects the target has.
119 enum SelectSupportKind {
120 ScalarValSelect, // The target supports scalar selects (ex: cmov).
121 ScalarCondVectorVal, // The target supports selects with a scalar condition
122 // and vector values (ex: cmov).
123 VectorMaskSelect // The target supports vector selects with a vector
124 // mask (ex: x86 blends).
127 /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
128 /// to, if at all. Exists because different targets have different levels of
129 /// support for these atomic instructions, and also have different options
130 /// w.r.t. what they should expand to.
131 enum class AtomicExpansionKind {
132 None, // Don't expand the instruction.
133 LLSC, // Expand the instruction into loadlinked/storeconditional; used
135 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
138 static ISD::NodeType getExtendForContent(BooleanContent Content) {
140 case UndefinedBooleanContent:
141 // Extend by adding rubbish bits.
142 return ISD::ANY_EXTEND;
143 case ZeroOrOneBooleanContent:
144 // Extend by adding zero bits.
145 return ISD::ZERO_EXTEND;
146 case ZeroOrNegativeOneBooleanContent:
147 // Extend by copying the sign bit.
148 return ISD::SIGN_EXTEND;
150 llvm_unreachable("Invalid content kind");
153 /// NOTE: The TargetMachine owns TLOF.
154 explicit TargetLoweringBase(const TargetMachine &TM);
155 virtual ~TargetLoweringBase() {}
158 /// \brief Initialize all of the actions to default values.
162 const TargetMachine &getTargetMachine() const { return TM; }
164 virtual bool useSoftFloat() const { return false; }
166 /// Return the pointer type for the given address space, defaults to
167 /// the pointer type from the data layout.
168 /// FIXME: The default needs to be removed once all the code is updated.
169 MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
170 return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
173 /// EVT is not used in-tree, but is used by out-of-tree target.
174 /// A documentation for this function would be nice...
175 virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
177 EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const;
179 /// Returns the type to be used for the index operand of:
180 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
181 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
182 virtual MVT getVectorIdxTy(const DataLayout &DL) const {
183 return getPointerTy(DL);
186 /// Return true if the select operation is expensive for this target.
187 bool isSelectExpensive() const { return SelectIsExpensive; }
189 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
193 /// Return true if multiple condition registers are available.
194 bool hasMultipleConditionRegisters() const {
195 return HasMultipleConditionRegisters;
198 /// Return true if the target has BitExtract instructions.
199 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
201 /// Return the preferred vector type legalization action.
202 virtual TargetLoweringBase::LegalizeTypeAction
203 getPreferredVectorAction(EVT VT) const {
204 // The default action for one element vectors is to scalarize
205 if (VT.getVectorNumElements() == 1)
206 return TypeScalarizeVector;
207 // The default action for other vectors is to promote
208 return TypePromoteInteger;
211 // There are two general methods for expanding a BUILD_VECTOR node:
212 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
214 // 2. Build the vector on the stack and then load it.
215 // If this function returns true, then method (1) will be used, subject to
216 // the constraint that all of the necessary shuffles are legal (as determined
217 // by isShuffleMaskLegal). If this function returns false, then method (2) is
218 // always used. The vector type, and the number of defined values, are
221 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
222 unsigned DefinedValues) const {
223 return DefinedValues < 3;
226 /// Return true if integer divide is usually cheaper than a sequence of
227 /// several shifts, adds, and multiplies for this target.
228 /// The definition of "cheaper" may depend on whether we're optimizing
229 /// for speed or for size.
230 virtual bool isIntDivCheap(EVT VT, AttributeSet Attr) const {
234 /// Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x)
235 bool isFsqrtCheap() const {
239 /// Returns true if target has indicated at least one type should be bypassed.
240 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
242 /// Returns map of slow types for division or remainder with corresponding
244 const DenseMap<unsigned int, unsigned int> &getBypassSlowDivWidths() const {
245 return BypassSlowDivWidths;
248 /// Return true if Flow Control is an expensive operation that should be
250 bool isJumpExpensive() const { return JumpIsExpensive; }
252 /// Return true if selects are only cheaper than branches if the branch is
253 /// unlikely to be predicted right.
254 bool isPredictableSelectExpensive() const {
255 return PredictableSelectIsExpensive;
258 /// isLoadBitCastBeneficial() - Return true if the following transform
260 /// fold (conv (load x)) -> (load (conv*)x)
261 /// On architectures that don't natively support some vector loads
262 /// efficiently, casting the load to a smaller vector of larger types and
263 /// loading is more efficient, however, this can be undone by optimizations in
265 virtual bool isLoadBitCastBeneficial(EVT /* Load */,
266 EVT /* Bitcast */) const {
270 /// Return true if it is expected to be cheaper to do a store of a non-zero
271 /// vector constant with the given size and type for the address space than to
272 /// store the individual scalar element constants.
273 virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
275 unsigned AddrSpace) const {
279 /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
280 virtual bool isCheapToSpeculateCttz() const {
284 /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
285 virtual bool isCheapToSpeculateCtlz() const {
289 /// \brief Return if the target supports combining a
292 /// %andResult = and %val1, #imm-with-one-bit-set;
293 /// %icmpResult = icmp %andResult, 0
294 /// br i1 %icmpResult, label %dest1, label %dest2
296 /// into a single machine instruction of a form like:
298 /// brOnBitSet %register, #bitNumber, dest
300 bool isMaskAndBranchFoldingLegal() const {
301 return MaskAndBranchFoldingIsLegal;
304 /// \brief Return true if the target wants to use the optimization that
305 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
306 /// promotedInst1(...(promotedInstN(ext(load)))).
307 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
309 /// Return true if the target can combine store(extractelement VectorTy,
311 /// \p Cost[out] gives the cost of that transformation when this is true.
312 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
313 unsigned &Cost) const {
317 /// Return true if target supports floating point exceptions.
318 bool hasFloatingPointExceptions() const {
319 return HasFloatingPointExceptions;
322 /// Return true if target always beneficiates from combining into FMA for a
323 /// given value type. This must typically return false on targets where FMA
324 /// takes more cycles to execute than FADD.
325 virtual bool enableAggressiveFMAFusion(EVT VT) const {
329 /// Return the ValueType of the result of SETCC operations.
330 virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
333 /// Return the ValueType for comparison libcalls. Comparions libcalls include
334 /// floating point comparion calls, and Ordered/Unordered check calls on
335 /// floating point numbers.
337 MVT::SimpleValueType getCmpLibcallReturnType() const;
339 /// For targets without i1 registers, this gives the nature of the high-bits
340 /// of boolean values held in types wider than i1.
342 /// "Boolean values" are special true/false values produced by nodes like
343 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
344 /// Not to be confused with general values promoted from i1. Some cpus
345 /// distinguish between vectors of boolean and scalars; the isVec parameter
346 /// selects between the two kinds. For example on X86 a scalar boolean should
347 /// be zero extended from i1, while the elements of a vector of booleans
348 /// should be sign extended from i1.
350 /// Some cpus also treat floating point types the same way as they treat
351 /// vectors instead of the way they treat scalars.
352 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
354 return BooleanVectorContents;
355 return isFloat ? BooleanFloatContents : BooleanContents;
358 BooleanContent getBooleanContents(EVT Type) const {
359 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
362 /// Return target scheduling preference.
363 Sched::Preference getSchedulingPreference() const {
364 return SchedPreferenceInfo;
367 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
368 /// for different nodes. This function returns the preference (or none) for
370 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
374 /// Return the register class that should be used for the specified value
376 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
377 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
378 assert(RC && "This value type is not natively supported!");
382 /// Return the 'representative' register class for the specified value
385 /// The 'representative' register class is the largest legal super-reg
386 /// register class for the register class of the value type. For example, on
387 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
388 /// register class is GR64 on x86_64.
389 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
390 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
394 /// Return the cost of the 'representative' register class for the specified
396 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
397 return RepRegClassCostForVT[VT.SimpleTy];
400 /// Return true if the target has native support for the specified value type.
401 /// This means that it has a register that directly holds it without
402 /// promotions or expansions.
403 bool isTypeLegal(EVT VT) const {
404 assert(!VT.isSimple() ||
405 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
406 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
409 class ValueTypeActionImpl {
410 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
411 /// that indicates how instruction selection should deal with the type.
412 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
415 ValueTypeActionImpl() {
416 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions), 0);
419 LegalizeTypeAction getTypeAction(MVT VT) const {
420 return (LegalizeTypeAction)ValueTypeActions[VT.SimpleTy];
423 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
424 unsigned I = VT.SimpleTy;
425 ValueTypeActions[I] = Action;
429 const ValueTypeActionImpl &getValueTypeActions() const {
430 return ValueTypeActions;
433 /// Return how we should legalize values of this type, either it is already
434 /// legal (return 'Legal') or we need to promote it to a larger type (return
435 /// 'Promote'), or we need to expand it into multiple registers of smaller
436 /// integer type (return 'Expand'). 'Custom' is not an option.
437 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
438 return getTypeConversion(Context, VT).first;
440 LegalizeTypeAction getTypeAction(MVT VT) const {
441 return ValueTypeActions.getTypeAction(VT);
444 /// For types supported by the target, this is an identity function. For
445 /// types that must be promoted to larger types, this returns the larger type
446 /// to promote to. For integer types that are larger than the largest integer
447 /// register, this contains one step in the expansion to get to the smaller
448 /// register. For illegal floating point types, this returns the integer type
450 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
451 return getTypeConversion(Context, VT).second;
454 /// For types supported by the target, this is an identity function. For
455 /// types that must be expanded (i.e. integer types that are larger than the
456 /// largest integer register or illegal floating point types), this returns
457 /// the largest legal type it will be expanded to.
458 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
459 assert(!VT.isVector());
461 switch (getTypeAction(Context, VT)) {
464 case TypeExpandInteger:
465 VT = getTypeToTransformTo(Context, VT);
468 llvm_unreachable("Type is not legal nor is it to be expanded!");
473 /// Vector types are broken down into some number of legal first class types.
474 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
475 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
476 /// turns into 4 EVT::i32 values with both PPC and X86.
478 /// This method returns the number of registers needed, and the VT for each
479 /// register. It also returns the VT and quantity of the intermediate values
480 /// before they are promoted/expanded.
481 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
483 unsigned &NumIntermediates,
484 MVT &RegisterVT) const;
486 struct IntrinsicInfo {
487 unsigned opc; // target opcode
488 EVT memVT; // memory VT
489 const Value* ptrVal; // value representing memory location
490 int offset; // offset off of ptrVal
491 unsigned size; // the size of the memory location
492 // (taken from memVT if zero)
493 unsigned align; // alignment
494 bool vol; // is volatile?
495 bool readMem; // reads memory?
496 bool writeMem; // writes memory?
498 IntrinsicInfo() : opc(0), ptrVal(nullptr), offset(0), size(0), align(1),
499 vol(false), readMem(false), writeMem(false) {}
502 /// Given an intrinsic, checks if on the target the intrinsic will need to map
503 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
504 /// true and store the intrinsic information into the IntrinsicInfo that was
505 /// passed to the function.
506 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
507 unsigned /*Intrinsic*/) const {
511 /// Returns true if the target can instruction select the specified FP
512 /// immediate natively. If false, the legalizer will materialize the FP
513 /// immediate as a load from a constant pool.
514 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
518 /// Targets can use this to indicate that they only support *some*
519 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
520 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
522 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
527 /// Returns true if the operation can trap for the value type.
529 /// VT must be a legal type. By default, we optimistically assume most
530 /// operations don't trap except for divide and remainder.
531 virtual bool canOpTrap(unsigned Op, EVT VT) const;
533 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
534 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
535 /// a VAND with a constant pool entry.
536 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
541 /// Return how this operation should be treated: either it is legal, needs to
542 /// be promoted to a larger size, needs to be expanded to some other code
543 /// sequence, or the target has a custom expander for it.
544 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
545 if (VT.isExtended()) return Expand;
546 // If a target-specific SDNode requires legalization, require the target
547 // to provide custom legalization for it.
548 if (Op > array_lengthof(OpActions[0])) return Custom;
549 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
550 return (LegalizeAction)OpActions[I][Op];
553 /// Return true if the specified operation is legal on this target or can be
554 /// made legal with custom lowering. This is used to help guide high-level
555 /// lowering decisions.
556 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
557 return (VT == MVT::Other || isTypeLegal(VT)) &&
558 (getOperationAction(Op, VT) == Legal ||
559 getOperationAction(Op, VT) == Custom);
562 /// Return true if the specified operation is legal on this target or can be
563 /// made legal using promotion. This is used to help guide high-level lowering
565 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
566 return (VT == MVT::Other || isTypeLegal(VT)) &&
567 (getOperationAction(Op, VT) == Legal ||
568 getOperationAction(Op, VT) == Promote);
571 /// Return true if the specified operation is illegal on this target or
572 /// unlikely to be made legal with custom lowering. This is used to help guide
573 /// high-level lowering decisions.
574 bool isOperationExpand(unsigned Op, EVT VT) const {
575 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
578 /// Return true if the specified operation is legal on this target.
579 bool isOperationLegal(unsigned Op, EVT VT) const {
580 return (VT == MVT::Other || isTypeLegal(VT)) &&
581 getOperationAction(Op, VT) == Legal;
584 /// Return how this load with extension should be treated: either it is legal,
585 /// needs to be promoted to a larger size, needs to be expanded to some other
586 /// code sequence, or the target has a custom expander for it.
587 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
589 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
590 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
591 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
592 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
593 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
594 return (LegalizeAction)LoadExtActions[ValI][MemI][ExtType];
597 /// Return true if the specified load with extension is legal on this target.
598 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
599 return ValVT.isSimple() && MemVT.isSimple() &&
600 getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
603 /// Return true if the specified load with extension is legal or custom
605 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
606 return ValVT.isSimple() && MemVT.isSimple() &&
607 (getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
608 getLoadExtAction(ExtType, ValVT, MemVT) == Custom);
611 /// Return how this store with truncation should be treated: either it is
612 /// legal, needs to be promoted to a larger size, needs to be expanded to some
613 /// other code sequence, or the target has a custom expander for it.
614 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
615 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
616 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
617 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
618 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
619 "Table isn't big enough!");
620 return (LegalizeAction)TruncStoreActions[ValI][MemI];
623 /// Return true if the specified store with truncation is legal on this
625 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
626 return isTypeLegal(ValVT) && MemVT.isSimple() &&
627 getTruncStoreAction(ValVT.getSimpleVT(), MemVT.getSimpleVT()) == Legal;
630 /// Return how the indexed load should be treated: either it is legal, needs
631 /// to be promoted to a larger size, needs to be expanded to some other code
632 /// sequence, or the target has a custom expander for it.
634 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
635 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
636 "Table isn't big enough!");
637 unsigned Ty = (unsigned)VT.SimpleTy;
638 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
641 /// Return true if the specified indexed load is legal on this target.
642 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
643 return VT.isSimple() &&
644 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
645 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
648 /// Return how the indexed store should be treated: either it is legal, needs
649 /// to be promoted to a larger size, needs to be expanded to some other code
650 /// sequence, or the target has a custom expander for it.
652 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
653 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
654 "Table isn't big enough!");
655 unsigned Ty = (unsigned)VT.SimpleTy;
656 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
659 /// Return true if the specified indexed load is legal on this target.
660 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
661 return VT.isSimple() &&
662 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
663 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
666 /// Return how the condition code should be treated: either it is legal, needs
667 /// to be expanded to some other code sequence, or the target has a custom
670 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
671 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
672 ((unsigned)VT.SimpleTy >> 4) < array_lengthof(CondCodeActions[0]) &&
673 "Table isn't big enough!");
674 // See setCondCodeAction for how this is encoded.
675 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
676 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 4];
677 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0x3);
678 assert(Action != Promote && "Can't promote condition code!");
682 /// Return true if the specified condition code is legal on this target.
683 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
685 getCondCodeAction(CC, VT) == Legal ||
686 getCondCodeAction(CC, VT) == Custom;
690 /// If the action for this operation is to promote, this method returns the
691 /// ValueType to promote to.
692 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
693 assert(getOperationAction(Op, VT) == Promote &&
694 "This operation isn't promoted!");
696 // See if this has an explicit type specified.
697 std::map<std::pair<unsigned, MVT::SimpleValueType>,
698 MVT::SimpleValueType>::const_iterator PTTI =
699 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
700 if (PTTI != PromoteToType.end()) return PTTI->second;
702 assert((VT.isInteger() || VT.isFloatingPoint()) &&
703 "Cannot autopromote this type, add it with AddPromotedToType.");
707 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
708 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
709 "Didn't find type to promote to!");
710 } while (!isTypeLegal(NVT) ||
711 getOperationAction(Op, NVT) == Promote);
715 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
716 /// operations except for the pointer size. If AllowUnknown is true, this
717 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
718 /// otherwise it will assert.
719 EVT getValueType(const DataLayout &DL, Type *Ty,
720 bool AllowUnknown = false) const {
721 // Lower scalar pointers to native pointer types.
722 if (PointerType *PTy = dyn_cast<PointerType>(Ty))
723 return getPointerTy(DL, PTy->getAddressSpace());
725 if (Ty->isVectorTy()) {
726 VectorType *VTy = cast<VectorType>(Ty);
727 Type *Elm = VTy->getElementType();
728 // Lower vectors of pointers to native pointer types.
729 if (PointerType *PT = dyn_cast<PointerType>(Elm)) {
730 EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
731 Elm = PointerTy.getTypeForEVT(Ty->getContext());
734 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
735 VTy->getNumElements());
737 return EVT::getEVT(Ty, AllowUnknown);
740 /// Return the MVT corresponding to this LLVM type. See getValueType.
741 MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
742 bool AllowUnknown = false) const {
743 return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
746 /// Return the desired alignment for ByVal or InAlloca aggregate function
747 /// arguments in the caller parameter area. This is the actual alignment, not
749 virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
751 /// Return the type of registers that this ValueType will eventually require.
752 MVT getRegisterType(MVT VT) const {
753 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
754 return RegisterTypeForVT[VT.SimpleTy];
757 /// Return the type of registers that this ValueType will eventually require.
758 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
760 assert((unsigned)VT.getSimpleVT().SimpleTy <
761 array_lengthof(RegisterTypeForVT));
762 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
767 unsigned NumIntermediates;
768 (void)getVectorTypeBreakdown(Context, VT, VT1,
769 NumIntermediates, RegisterVT);
772 if (VT.isInteger()) {
773 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
775 llvm_unreachable("Unsupported extended type!");
778 /// Return the number of registers that this ValueType will eventually
781 /// This is one for any types promoted to live in larger registers, but may be
782 /// more than one for types (like i64) that are split into pieces. For types
783 /// like i140, which are first promoted then expanded, it is the number of
784 /// registers needed to hold all the bits of the original type. For an i140
785 /// on a 32 bit machine this means 5 registers.
786 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
788 assert((unsigned)VT.getSimpleVT().SimpleTy <
789 array_lengthof(NumRegistersForVT));
790 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
795 unsigned NumIntermediates;
796 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
798 if (VT.isInteger()) {
799 unsigned BitWidth = VT.getSizeInBits();
800 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
801 return (BitWidth + RegWidth - 1) / RegWidth;
803 llvm_unreachable("Unsupported extended type!");
806 /// If true, then instruction selection should seek to shrink the FP constant
807 /// of the specified type to a smaller type in order to save space and / or
809 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
811 // Return true if it is profitable to reduce the given load node to a smaller
814 // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
815 virtual bool shouldReduceLoadWidth(SDNode *Load,
816 ISD::LoadExtType ExtTy,
821 /// When splitting a value of the specified type into parts, does the Lo
822 /// or Hi part come first? This usually follows the endianness, except
823 /// for ppcf128, where the Hi part always comes first.
824 bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
825 return DL.isBigEndian() || VT == MVT::ppcf128;
828 /// If true, the target has custom DAG combine transformations that it can
829 /// perform for the specified node.
830 bool hasTargetDAGCombine(ISD::NodeType NT) const {
831 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
832 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
835 /// \brief Get maximum # of store operations permitted for llvm.memset
837 /// This function returns the maximum number of store operations permitted
838 /// to replace a call to llvm.memset. The value is set by the target at the
839 /// performance threshold for such a replacement. If OptSize is true,
840 /// return the limit for functions that have OptSize attribute.
841 unsigned getMaxStoresPerMemset(bool OptSize) const {
842 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
845 /// \brief Get maximum # of store operations permitted for llvm.memcpy
847 /// This function returns the maximum number of store operations permitted
848 /// to replace a call to llvm.memcpy. The value is set by the target at the
849 /// performance threshold for such a replacement. If OptSize is true,
850 /// return the limit for functions that have OptSize attribute.
851 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
852 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
855 /// \brief Get maximum # of store operations permitted for llvm.memmove
857 /// This function returns the maximum number of store operations permitted
858 /// to replace a call to llvm.memmove. The value is set by the target at the
859 /// performance threshold for such a replacement. If OptSize is true,
860 /// return the limit for functions that have OptSize attribute.
861 unsigned getMaxStoresPerMemmove(bool OptSize) const {
862 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
865 /// \brief Determine if the target supports unaligned memory accesses.
867 /// This function returns true if the target allows unaligned memory accesses
868 /// of the specified type in the given address space. If true, it also returns
869 /// whether the unaligned memory access is "fast" in the last argument by
870 /// reference. This is used, for example, in situations where an array
871 /// copy/move/set is converted to a sequence of store operations. Its use
872 /// helps to ensure that such replacements don't generate code that causes an
873 /// alignment error (trap) on the target machine.
874 virtual bool allowsMisalignedMemoryAccesses(EVT,
875 unsigned AddrSpace = 0,
877 bool * /*Fast*/ = nullptr) const {
881 /// Return true if the target supports a memory access of this type for the
882 /// given address space and alignment. If the access is allowed, the optional
883 /// final parameter returns if the access is also fast (as defined by the
885 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
886 unsigned AddrSpace = 0, unsigned Alignment = 1,
887 bool *Fast = nullptr) const;
889 /// Returns the target specific optimal type for load and store operations as
890 /// a result of memset, memcpy, and memmove lowering.
892 /// If DstAlign is zero that means it's safe to destination alignment can
893 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
894 /// a need to check it against alignment requirement, probably because the
895 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
896 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
897 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
898 /// does not need to be loaded. It returns EVT::Other if the type should be
899 /// determined using generic target-independent logic.
900 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
901 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
904 bool /*MemcpyStrSrc*/,
905 MachineFunction &/*MF*/) const {
909 /// Returns true if it's safe to use load / store of the specified type to
910 /// expand memcpy / memset inline.
912 /// This is mostly true for all types except for some special cases. For
913 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
914 /// fstpl which also does type conversion. Note the specified type doesn't
915 /// have to be legal as the hook is used before type legalization.
916 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
918 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
919 bool usesUnderscoreSetJmp() const {
920 return UseUnderscoreSetJmp;
923 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
924 bool usesUnderscoreLongJmp() const {
925 return UseUnderscoreLongJmp;
928 /// Return integer threshold on number of blocks to use jump tables rather
929 /// than if sequence.
930 int getMinimumJumpTableEntries() const {
931 return MinimumJumpTableEntries;
934 /// If a physical register, this specifies the register that
935 /// llvm.savestack/llvm.restorestack should save and restore.
936 unsigned getStackPointerRegisterToSaveRestore() const {
937 return StackPointerRegisterToSaveRestore;
940 /// If a physical register, this returns the register that receives the
941 /// exception address on entry to a landing pad.
942 unsigned getExceptionPointerRegister() const {
943 return ExceptionPointerRegister;
946 /// If a physical register, this returns the register that receives the
947 /// exception typeid on entry to a landing pad.
948 unsigned getExceptionSelectorRegister() const {
949 return ExceptionSelectorRegister;
952 /// Returns the target's jmp_buf size in bytes (if never set, the default is
954 unsigned getJumpBufSize() const {
958 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
960 unsigned getJumpBufAlignment() const {
961 return JumpBufAlignment;
964 /// Return the minimum stack alignment of an argument.
965 unsigned getMinStackArgumentAlignment() const {
966 return MinStackArgumentAlignment;
969 /// Return the minimum function alignment.
970 unsigned getMinFunctionAlignment() const {
971 return MinFunctionAlignment;
974 /// Return the preferred function alignment.
975 unsigned getPrefFunctionAlignment() const {
976 return PrefFunctionAlignment;
979 /// Return the preferred loop alignment.
980 virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
981 return PrefLoopAlignment;
984 /// Return whether the DAG builder should automatically insert fences and
985 /// reduce ordering for atomics.
986 bool getInsertFencesForAtomic() const {
987 return InsertFencesForAtomic;
990 /// Return true if the target stores stack protector cookies at a fixed offset
991 /// in some non-standard address space, and populates the address space and
992 /// offset as appropriate.
993 virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
994 unsigned &/*Offset*/) const {
998 /// Return true if the target stores SafeStack pointer at a fixed offset in
999 /// some non-standard address space, and populates the address space and
1000 /// offset as appropriate.
1001 virtual bool getSafeStackPointerLocation(unsigned & /*AddressSpace*/,
1002 unsigned & /*Offset*/) const {
1006 /// Returns true if a cast between SrcAS and DestAS is a noop.
1007 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1011 /// Return true if the pointer arguments to CI should be aligned by aligning
1012 /// the object whose address is being passed. If so then MinSize is set to the
1013 /// minimum size the object must be to be aligned and PrefAlign is set to the
1014 /// preferred alignment.
1015 virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1016 unsigned & /*PrefAlign*/) const {
1020 //===--------------------------------------------------------------------===//
1021 /// \name Helpers for TargetTransformInfo implementations
1024 /// Get the ISD node that corresponds to the Instruction class opcode.
1025 int InstructionOpcodeToISD(unsigned Opcode) const;
1027 /// Estimate the cost of type-legalization and the legalized type.
1028 std::pair<int, MVT> getTypeLegalizationCost(const DataLayout &DL,
1033 //===--------------------------------------------------------------------===//
1034 /// \name Helpers for atomic expansion.
1037 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1038 /// corresponding pointee type. This may entail some non-trivial operations to
1039 /// truncate or reconstruct types that will be illegal in the backend. See
1040 /// ARMISelLowering for an example implementation.
1041 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1042 AtomicOrdering Ord) const {
1043 llvm_unreachable("Load linked unimplemented on this target");
1046 /// Perform a store-conditional operation to Addr. Return the status of the
1047 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1048 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1049 Value *Addr, AtomicOrdering Ord) const {
1050 llvm_unreachable("Store conditional unimplemented on this target");
1053 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1054 /// It is called by AtomicExpandPass before expanding an
1055 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad.
1056 /// RMW and CmpXchg set both IsStore and IsLoad to true.
1057 /// This function should either return a nullptr, or a pointer to an IR-level
1058 /// Instruction*. Even complex fence sequences can be represented by a
1059 /// single Instruction* through an intrinsic to be lowered later.
1060 /// Backends with !getInsertFencesForAtomic() should keep a no-op here.
1061 /// Backends should override this method to produce target-specific intrinsic
1062 /// for their fences.
1063 /// FIXME: Please note that the default implementation here in terms of
1064 /// IR-level fences exists for historical/compatibility reasons and is
1065 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1066 /// consistency. For example, consider the following example:
1067 /// atomic<int> x = y = 0;
1068 /// int r1, r2, r3, r4;
1079 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1080 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1081 /// IR-level fences can prevent it.
1083 virtual Instruction *emitLeadingFence(IRBuilder<> &Builder,
1084 AtomicOrdering Ord, bool IsStore,
1085 bool IsLoad) const {
1086 if (!getInsertFencesForAtomic())
1089 if (isAtLeastRelease(Ord) && IsStore)
1090 return Builder.CreateFence(Ord);
1095 virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1096 AtomicOrdering Ord, bool IsStore,
1097 bool IsLoad) const {
1098 if (!getInsertFencesForAtomic())
1101 if (isAtLeastAcquire(Ord))
1102 return Builder.CreateFence(Ord);
1108 // Emits code that executes when the comparison result in the ll/sc
1109 // expansion of a cmpxchg instruction is such that the store-conditional will
1110 // not execute. This makes it possible to balance out the load-linked with
1111 // a dedicated instruction, if desired.
1112 // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1113 // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1114 virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1116 /// Returns true if the given (atomic) store should be expanded by the
1117 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1118 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1122 /// Returns true if arguments should be sign-extended in lib calls.
1123 virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1127 /// Returns how the given (atomic) load should be expanded by the
1128 /// IR-level AtomicExpand pass.
1129 virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
1130 return AtomicExpansionKind::None;
1133 /// Returns true if the given atomic cmpxchg should be expanded by the
1134 /// IR-level AtomicExpand pass into a load-linked/store-conditional sequence
1135 /// (through emitLoadLinked() and emitStoreConditional()).
1136 virtual bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
1140 /// Returns how the IR-level AtomicExpand pass should expand the given
1141 /// AtomicRMW, if at all. Default is to never expand.
1142 virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1143 return AtomicExpansionKind::None;
1146 /// On some platforms, an AtomicRMW that never actually modifies the value
1147 /// (such as fetch_add of 0) can be turned into a fence followed by an
1148 /// atomic load. This may sound useless, but it makes it possible for the
1149 /// processor to keep the cacheline shared, dramatically improving
1150 /// performance. And such idempotent RMWs are useful for implementing some
1151 /// kinds of locks, see for example (justification + benchmarks):
1152 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1153 /// This method tries doing that transformation, returning the atomic load if
1154 /// it succeeds, and nullptr otherwise.
1155 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1156 /// another round of expansion.
1158 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1162 /// Returns true if we should normalize
1163 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1164 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1165 /// that it saves us from materializing N0 and N1 in an integer register.
1166 /// Targets that are able to perform and/or on flags should return false here.
1167 virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1169 // If a target has multiple condition registers, then it likely has logical
1170 // operations on those registers.
1171 if (hasMultipleConditionRegisters())
1173 // Only do the transform if the value won't be split into multiple
1175 LegalizeTypeAction Action = getTypeAction(Context, VT);
1176 return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1177 Action != TypeSplitVector;
1180 //===--------------------------------------------------------------------===//
1181 // TargetLowering Configuration Methods - These methods should be invoked by
1182 // the derived class constructor to configure this object for the target.
1185 /// Specify how the target extends the result of integer and floating point
1186 /// boolean values from i1 to a wider type. See getBooleanContents.
1187 void setBooleanContents(BooleanContent Ty) {
1188 BooleanContents = Ty;
1189 BooleanFloatContents = Ty;
1192 /// Specify how the target extends the result of integer and floating point
1193 /// boolean values from i1 to a wider type. See getBooleanContents.
1194 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1195 BooleanContents = IntTy;
1196 BooleanFloatContents = FloatTy;
1199 /// Specify how the target extends the result of a vector boolean value from a
1200 /// vector of i1 to a wider type. See getBooleanContents.
1201 void setBooleanVectorContents(BooleanContent Ty) {
1202 BooleanVectorContents = Ty;
1205 /// Specify the target scheduling preference.
1206 void setSchedulingPreference(Sched::Preference Pref) {
1207 SchedPreferenceInfo = Pref;
1210 /// Indicate whether this target prefers to use _setjmp to implement
1211 /// llvm.setjmp or the version without _. Defaults to false.
1212 void setUseUnderscoreSetJmp(bool Val) {
1213 UseUnderscoreSetJmp = Val;
1216 /// Indicate whether this target prefers to use _longjmp to implement
1217 /// llvm.longjmp or the version without _. Defaults to false.
1218 void setUseUnderscoreLongJmp(bool Val) {
1219 UseUnderscoreLongJmp = Val;
1222 /// Indicate the number of blocks to generate jump tables rather than if
1224 void setMinimumJumpTableEntries(int Val) {
1225 MinimumJumpTableEntries = Val;
1228 /// If set to a physical register, this specifies the register that
1229 /// llvm.savestack/llvm.restorestack should save and restore.
1230 void setStackPointerRegisterToSaveRestore(unsigned R) {
1231 StackPointerRegisterToSaveRestore = R;
1234 /// If set to a physical register, this sets the register that receives the
1235 /// exception address on entry to a landing pad.
1236 void setExceptionPointerRegister(unsigned R) {
1237 ExceptionPointerRegister = R;
1240 /// If set to a physical register, this sets the register that receives the
1241 /// exception typeid on entry to a landing pad.
1242 void setExceptionSelectorRegister(unsigned R) {
1243 ExceptionSelectorRegister = R;
1246 /// Tells the code generator not to expand operations into sequences that use
1247 /// the select operations if possible.
1248 void setSelectIsExpensive(bool isExpensive = true) {
1249 SelectIsExpensive = isExpensive;
1252 /// Tells the code generator that the target has multiple (allocatable)
1253 /// condition registers that can be used to store the results of comparisons
1254 /// for use by selects and conditional branches. With multiple condition
1255 /// registers, the code generator will not aggressively sink comparisons into
1256 /// the blocks of their users.
1257 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1258 HasMultipleConditionRegisters = hasManyRegs;
1261 /// Tells the code generator that the target has BitExtract instructions.
1262 /// The code generator will aggressively sink "shift"s into the blocks of
1263 /// their users if the users will generate "and" instructions which can be
1264 /// combined with "shift" to BitExtract instructions.
1265 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1266 HasExtractBitsInsn = hasExtractInsn;
1269 /// Tells the code generator not to expand logic operations on comparison
1270 /// predicates into separate sequences that increase the amount of flow
1272 void setJumpIsExpensive(bool isExpensive = true);
1274 /// Tells the code generator that fsqrt is cheap, and should not be replaced
1275 /// with an alternative sequence of instructions.
1276 void setFsqrtIsCheap(bool isCheap = true) { FsqrtIsCheap = isCheap; }
1278 /// Tells the code generator that this target supports floating point
1279 /// exceptions and cares about preserving floating point exception behavior.
1280 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1281 HasFloatingPointExceptions = FPExceptions;
1284 /// Tells the code generator which bitwidths to bypass.
1285 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1286 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1289 /// Add the specified register class as an available regclass for the
1290 /// specified value type. This indicates the selector can handle values of
1291 /// that class natively.
1292 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1293 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1294 AvailableRegClasses.push_back(std::make_pair(VT, RC));
1295 RegClassForVT[VT.SimpleTy] = RC;
1298 /// Remove all register classes.
1299 void clearRegisterClasses() {
1300 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE * sizeof(TargetRegisterClass*));
1302 AvailableRegClasses.clear();
1305 /// \brief Remove all operation actions.
1306 void clearOperationActions() {
1309 /// Return the largest legal super-reg register class of the register class
1310 /// for the specified type and its associated "cost".
1311 virtual std::pair<const TargetRegisterClass *, uint8_t>
1312 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1314 /// Once all of the register classes are added, this allows us to compute
1315 /// derived properties we expose.
1316 void computeRegisterProperties(const TargetRegisterInfo *TRI);
1318 /// Indicate that the specified operation does not work with the specified
1319 /// type and indicate what to do about it.
1320 void setOperationAction(unsigned Op, MVT VT,
1321 LegalizeAction Action) {
1322 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1323 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
1326 /// Indicate that the specified load with extension does not work with the
1327 /// specified type and indicate what to do about it.
1328 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1329 LegalizeAction Action) {
1330 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1331 MemVT.isValid() && "Table isn't big enough!");
1332 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy][ExtType] = (uint8_t)Action;
1335 /// Indicate that the specified truncating store does not work with the
1336 /// specified type and indicate what to do about it.
1337 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1338 LegalizeAction Action) {
1339 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1340 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1343 /// Indicate that the specified indexed load does or does not work with the
1344 /// specified type and indicate what to do abort it.
1346 /// NOTE: All indexed mode loads are initialized to Expand in
1347 /// TargetLowering.cpp
1348 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1349 LegalizeAction Action) {
1350 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1351 (unsigned)Action < 0xf && "Table isn't big enough!");
1352 // Load action are kept in the upper half.
1353 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1354 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1357 /// Indicate that the specified indexed store does or does not work with the
1358 /// specified type and indicate what to do about it.
1360 /// NOTE: All indexed mode stores are initialized to Expand in
1361 /// TargetLowering.cpp
1362 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1363 LegalizeAction Action) {
1364 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1365 (unsigned)Action < 0xf && "Table isn't big enough!");
1366 // Store action are kept in the lower half.
1367 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1368 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1371 /// Indicate that the specified condition code is or isn't supported on the
1372 /// target and indicate what to do about it.
1373 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1374 LegalizeAction Action) {
1375 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1376 "Table isn't big enough!");
1377 /// The lower 5 bits of the SimpleTy index into Nth 2bit set from the 32-bit
1378 /// value and the upper 27 bits index into the second dimension of the array
1379 /// to select what 32-bit value to use.
1380 uint32_t Shift = 2 * (VT.SimpleTy & 0xF);
1381 CondCodeActions[CC][VT.SimpleTy >> 4] &= ~((uint32_t)0x3 << Shift);
1382 CondCodeActions[CC][VT.SimpleTy >> 4] |= (uint32_t)Action << Shift;
1385 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1386 /// to trying a larger integer/fp until it can find one that works. If that
1387 /// default is insufficient, this method can be used by the target to override
1389 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1390 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1393 /// Targets should invoke this method for each target independent node that
1394 /// they want to provide a custom DAG combiner for by implementing the
1395 /// PerformDAGCombine virtual method.
1396 void setTargetDAGCombine(ISD::NodeType NT) {
1397 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1398 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1401 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1402 void setJumpBufSize(unsigned Size) {
1406 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1408 void setJumpBufAlignment(unsigned Align) {
1409 JumpBufAlignment = Align;
1412 /// Set the target's minimum function alignment (in log2(bytes))
1413 void setMinFunctionAlignment(unsigned Align) {
1414 MinFunctionAlignment = Align;
1417 /// Set the target's preferred function alignment. This should be set if
1418 /// there is a performance benefit to higher-than-minimum alignment (in
1420 void setPrefFunctionAlignment(unsigned Align) {
1421 PrefFunctionAlignment = Align;
1424 /// Set the target's preferred loop alignment. Default alignment is zero, it
1425 /// means the target does not care about loop alignment. The alignment is
1426 /// specified in log2(bytes). The target may also override
1427 /// getPrefLoopAlignment to provide per-loop values.
1428 void setPrefLoopAlignment(unsigned Align) {
1429 PrefLoopAlignment = Align;
1432 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1433 void setMinStackArgumentAlignment(unsigned Align) {
1434 MinStackArgumentAlignment = Align;
1437 /// Set if the DAG builder should automatically insert fences and reduce the
1438 /// order of atomic memory operations to Monotonic.
1439 void setInsertFencesForAtomic(bool fence) {
1440 InsertFencesForAtomic = fence;
1444 //===--------------------------------------------------------------------===//
1445 // Addressing mode description hooks (used by LSR etc).
1448 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1449 /// instructions reading the address. This allows as much computation as
1450 /// possible to be done in the address mode for that operand. This hook lets
1451 /// targets also pass back when this should be done on intrinsics which
1453 virtual bool GetAddrModeArguments(IntrinsicInst * /*I*/,
1454 SmallVectorImpl<Value*> &/*Ops*/,
1455 Type *&/*AccessTy*/,
1456 unsigned AddrSpace = 0) const {
1460 /// This represents an addressing mode of:
1461 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1462 /// If BaseGV is null, there is no BaseGV.
1463 /// If BaseOffs is zero, there is no base offset.
1464 /// If HasBaseReg is false, there is no base register.
1465 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1468 GlobalValue *BaseGV;
1472 AddrMode() : BaseGV(nullptr), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1475 /// Return true if the addressing mode represented by AM is legal for this
1476 /// target, for a load/store of the specified type.
1478 /// The type may be VoidTy, in which case only return true if the addressing
1479 /// mode is legal for a load/store of any legal type. TODO: Handle
1480 /// pre/postinc as well.
1482 /// If the address space cannot be determined, it will be -1.
1484 /// TODO: Remove default argument
1485 virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1486 Type *Ty, unsigned AddrSpace) const;
1488 /// \brief Return the cost of the scaling factor used in the addressing mode
1489 /// represented by AM for this target, for a load/store of the specified type.
1491 /// If the AM is supported, the return value must be >= 0.
1492 /// If the AM is not supported, it returns a negative value.
1493 /// TODO: Handle pre/postinc as well.
1494 /// TODO: Remove default argument
1495 virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
1496 Type *Ty, unsigned AS = 0) const {
1497 // Default: assume that any scaling factor used in a legal AM is free.
1498 if (isLegalAddressingMode(DL, AM, Ty, AS))
1503 /// Return true if the specified immediate is legal icmp immediate, that is
1504 /// the target has icmp instructions which can compare a register against the
1505 /// immediate without having to materialize the immediate into a register.
1506 virtual bool isLegalICmpImmediate(int64_t) const {
1510 /// Return true if the specified immediate is legal add immediate, that is the
1511 /// target has add instructions which can add a register with the immediate
1512 /// without having to materialize the immediate into a register.
1513 virtual bool isLegalAddImmediate(int64_t) const {
1517 /// Return true if it's significantly cheaper to shift a vector by a uniform
1518 /// scalar than by an amount which will vary across each lane. On x86, for
1519 /// example, there is a "psllw" instruction for the former case, but no simple
1520 /// instruction for a general "a << b" operation on vectors.
1521 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1525 /// Return true if it's free to truncate a value of type FromTy to type
1526 /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1527 /// by referencing its sub-register AX.
1528 /// Targets must return false when FromTy <= ToTy.
1529 virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
1533 /// Return true if a truncation from FromTy to ToTy is permitted when deciding
1534 /// whether a call is in tail position. Typically this means that both results
1535 /// would be assigned to the same register or stack slot, but it could mean
1536 /// the target performs adequate checks of its own before proceeding with the
1537 /// tail call. Targets must return false when FromTy <= ToTy.
1538 virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
1542 virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
1546 virtual bool isProfitableToHoist(Instruction *I) const { return true; }
1548 /// Return true if the extension represented by \p I is free.
1549 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
1550 /// this method can use the context provided by \p I to decide
1551 /// whether or not \p I is free.
1552 /// This method extends the behavior of the is[Z|FP]ExtFree family.
1553 /// In other words, if is[Z|FP]Free returns true, then this method
1554 /// returns true as well. The converse is not true.
1555 /// The target can perform the adequate checks by overriding isExtFreeImpl.
1556 /// \pre \p I must be a sign, zero, or fp extension.
1557 bool isExtFree(const Instruction *I) const {
1558 switch (I->getOpcode()) {
1559 case Instruction::FPExt:
1560 if (isFPExtFree(EVT::getEVT(I->getType())))
1563 case Instruction::ZExt:
1564 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
1567 case Instruction::SExt:
1570 llvm_unreachable("Instruction is not an extension");
1572 return isExtFreeImpl(I);
1575 /// Return true if any actual instruction that defines a value of type FromTy
1576 /// implicitly zero-extends the value to ToTy in the result register.
1578 /// The function should return true when it is likely that the truncate can
1579 /// be freely folded with an instruction defining a value of FromTy. If
1580 /// the defining instruction is unknown (because you're looking at a
1581 /// function argument, PHI, etc.) then the target may require an
1582 /// explicit truncate, which is not necessarily free, but this function
1583 /// does not deal with those cases.
1584 /// Targets must return false when FromTy >= ToTy.
1585 virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
1589 virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
1593 /// Return true if the target supplies and combines to a paired load
1594 /// two loaded values of type LoadedType next to each other in memory.
1595 /// RequiredAlignment gives the minimal alignment constraints that must be met
1596 /// to be able to select this paired load.
1598 /// This information is *not* used to generate actual paired loads, but it is
1599 /// used to generate a sequence of loads that is easier to combine into a
1601 /// For instance, something like this:
1602 /// a = load i64* addr
1603 /// b = trunc i64 a to i32
1604 /// c = lshr i64 a, 32
1605 /// d = trunc i64 c to i32
1606 /// will be optimized into:
1607 /// b = load i32* addr1
1608 /// d = load i32* addr2
1609 /// Where addr1 = addr2 +/- sizeof(i32).
1611 /// In other words, unless the target performs a post-isel load combining,
1612 /// this information should not be provided because it will generate more
1614 virtual bool hasPairedLoad(Type * /*LoadedType*/,
1615 unsigned & /*RequiredAligment*/) const {
1619 virtual bool hasPairedLoad(EVT /*LoadedType*/,
1620 unsigned & /*RequiredAligment*/) const {
1624 /// \brief Get the maximum supported factor for interleaved memory accesses.
1625 /// Default to be the minimum interleave factor: 2.
1626 virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
1628 /// \brief Lower an interleaved load to target specific intrinsics. Return
1629 /// true on success.
1631 /// \p LI is the vector load instruction.
1632 /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
1633 /// \p Indices is the corresponding indices for each shufflevector.
1634 /// \p Factor is the interleave factor.
1635 virtual bool lowerInterleavedLoad(LoadInst *LI,
1636 ArrayRef<ShuffleVectorInst *> Shuffles,
1637 ArrayRef<unsigned> Indices,
1638 unsigned Factor) const {
1642 /// \brief Lower an interleaved store to target specific intrinsics. Return
1643 /// true on success.
1645 /// \p SI is the vector store instruction.
1646 /// \p SVI is the shufflevector to RE-interleave the stored vector.
1647 /// \p Factor is the interleave factor.
1648 virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
1649 unsigned Factor) const {
1653 /// Return true if zero-extending the specific node Val to type VT2 is free
1654 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
1655 /// because it's folded such as X86 zero-extending loads).
1656 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
1657 return isZExtFree(Val.getValueType(), VT2);
1660 /// Return true if an fpext operation is free (for instance, because
1661 /// single-precision floating-point numbers are implicitly extended to
1662 /// double-precision).
1663 virtual bool isFPExtFree(EVT VT) const {
1664 assert(VT.isFloatingPoint());
1668 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
1669 /// extend node) is profitable.
1670 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
1672 /// Return true if an fneg operation is free to the point where it is never
1673 /// worthwhile to replace it with a bitwise operation.
1674 virtual bool isFNegFree(EVT VT) const {
1675 assert(VT.isFloatingPoint());
1679 /// Return true if an fabs operation is free to the point where it is never
1680 /// worthwhile to replace it with a bitwise operation.
1681 virtual bool isFAbsFree(EVT VT) const {
1682 assert(VT.isFloatingPoint());
1686 /// Return true if an FMA operation is faster than a pair of fmul and fadd
1687 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
1688 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
1690 /// NOTE: This may be called before legalization on types for which FMAs are
1691 /// not legal, but should return true if those types will eventually legalize
1692 /// to types that support FMAs. After legalization, it will only be called on
1693 /// types that support FMAs (via Legal or Custom actions)
1694 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
1698 /// Return true if it's profitable to narrow operations of type VT1 to
1699 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
1701 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
1705 /// \brief Return true if it is beneficial to convert a load of a constant to
1706 /// just the constant itself.
1707 /// On some targets it might be more efficient to use a combination of
1708 /// arithmetic instructions to materialize the constant instead of loading it
1709 /// from a constant pool.
1710 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
1715 /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
1716 /// with this index. This is needed because EXTRACT_SUBVECTOR usually
1717 /// has custom lowering that depends on the index of the first element,
1718 /// and only the target knows which lowering is cheap.
1719 virtual bool isExtractSubvectorCheap(EVT ResVT, unsigned Index) const {
1723 //===--------------------------------------------------------------------===//
1724 // Runtime Library hooks
1727 /// Rename the default libcall routine name for the specified libcall.
1728 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1729 LibcallRoutineNames[Call] = Name;
1732 /// Get the libcall routine name for the specified libcall.
1733 const char *getLibcallName(RTLIB::Libcall Call) const {
1734 return LibcallRoutineNames[Call];
1737 /// Override the default CondCode to be used to test the result of the
1738 /// comparison libcall against zero.
1739 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1740 CmpLibcallCCs[Call] = CC;
1743 /// Get the CondCode that's to be used to test the result of the comparison
1744 /// libcall against zero.
1745 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1746 return CmpLibcallCCs[Call];
1749 /// Set the CallingConv that should be used for the specified libcall.
1750 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1751 LibcallCallingConvs[Call] = CC;
1754 /// Get the CallingConv that should be used for the specified libcall.
1755 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1756 return LibcallCallingConvs[Call];
1760 const TargetMachine &TM;
1762 /// Tells the code generator not to expand operations into sequences that use
1763 /// the select operations if possible.
1764 bool SelectIsExpensive;
1766 /// Tells the code generator that the target has multiple (allocatable)
1767 /// condition registers that can be used to store the results of comparisons
1768 /// for use by selects and conditional branches. With multiple condition
1769 /// registers, the code generator will not aggressively sink comparisons into
1770 /// the blocks of their users.
1771 bool HasMultipleConditionRegisters;
1773 /// Tells the code generator that the target has BitExtract instructions.
1774 /// The code generator will aggressively sink "shift"s into the blocks of
1775 /// their users if the users will generate "and" instructions which can be
1776 /// combined with "shift" to BitExtract instructions.
1777 bool HasExtractBitsInsn;
1779 // Don't expand fsqrt with an approximation based on the inverse sqrt.
1782 /// Tells the code generator to bypass slow divide or remainder
1783 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
1784 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
1785 /// div/rem when the operands are positive and less than 256.
1786 DenseMap <unsigned int, unsigned int> BypassSlowDivWidths;
1788 /// Tells the code generator that it shouldn't generate extra flow control
1789 /// instructions and should attempt to combine flow control instructions via
1791 bool JumpIsExpensive;
1793 /// Whether the target supports or cares about preserving floating point
1794 /// exception behavior.
1795 bool HasFloatingPointExceptions;
1797 /// This target prefers to use _setjmp to implement llvm.setjmp.
1799 /// Defaults to false.
1800 bool UseUnderscoreSetJmp;
1802 /// This target prefers to use _longjmp to implement llvm.longjmp.
1804 /// Defaults to false.
1805 bool UseUnderscoreLongJmp;
1807 /// Number of blocks threshold to use jump tables.
1808 int MinimumJumpTableEntries;
1810 /// Information about the contents of the high-bits in boolean values held in
1811 /// a type wider than i1. See getBooleanContents.
1812 BooleanContent BooleanContents;
1814 /// Information about the contents of the high-bits in boolean values held in
1815 /// a type wider than i1. See getBooleanContents.
1816 BooleanContent BooleanFloatContents;
1818 /// Information about the contents of the high-bits in boolean vector values
1819 /// when the element type is wider than i1. See getBooleanContents.
1820 BooleanContent BooleanVectorContents;
1822 /// The target scheduling preference: shortest possible total cycles or lowest
1824 Sched::Preference SchedPreferenceInfo;
1826 /// The size, in bytes, of the target's jmp_buf buffers
1827 unsigned JumpBufSize;
1829 /// The alignment, in bytes, of the target's jmp_buf buffers
1830 unsigned JumpBufAlignment;
1832 /// The minimum alignment that any argument on the stack needs to have.
1833 unsigned MinStackArgumentAlignment;
1835 /// The minimum function alignment (used when optimizing for size, and to
1836 /// prevent explicitly provided alignment from leading to incorrect code).
1837 unsigned MinFunctionAlignment;
1839 /// The preferred function alignment (used when alignment unspecified and
1840 /// optimizing for speed).
1841 unsigned PrefFunctionAlignment;
1843 /// The preferred loop alignment.
1844 unsigned PrefLoopAlignment;
1846 /// Whether the DAG builder should automatically insert fences and reduce
1847 /// ordering for atomics. (This will be set for for most architectures with
1848 /// weak memory ordering.)
1849 bool InsertFencesForAtomic;
1851 /// If set to a physical register, this specifies the register that
1852 /// llvm.savestack/llvm.restorestack should save and restore.
1853 unsigned StackPointerRegisterToSaveRestore;
1855 /// If set to a physical register, this specifies the register that receives
1856 /// the exception address on entry to a landing pad.
1857 unsigned ExceptionPointerRegister;
1859 /// If set to a physical register, this specifies the register that receives
1860 /// the exception typeid on entry to a landing pad.
1861 unsigned ExceptionSelectorRegister;
1863 /// This indicates the default register class to use for each ValueType the
1864 /// target supports natively.
1865 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1866 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1867 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1869 /// This indicates the "representative" register class to use for each
1870 /// ValueType the target supports natively. This information is used by the
1871 /// scheduler to track register pressure. By default, the representative
1872 /// register class is the largest legal super-reg register class of the
1873 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
1874 /// representative class would be GR32.
1875 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
1877 /// This indicates the "cost" of the "representative" register class for each
1878 /// ValueType. The cost is used by the scheduler to approximate register
1880 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
1882 /// For any value types we are promoting or expanding, this contains the value
1883 /// type that we are changing to. For Expanded types, this contains one step
1884 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
1885 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
1886 /// the same type (e.g. i32 -> i32).
1887 MVT TransformToType[MVT::LAST_VALUETYPE];
1889 /// For each operation and each value type, keep a LegalizeAction that
1890 /// indicates how instruction selection should deal with the operation. Most
1891 /// operations are Legal (aka, supported natively by the target), but
1892 /// operations that are not should be described. Note that operations on
1893 /// non-legal value types are not described here.
1894 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1896 /// For each load extension type and each value type, keep a LegalizeAction
1897 /// that indicates how instruction selection should deal with a load of a
1898 /// specific value type and extension type.
1899 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE]
1900 [ISD::LAST_LOADEXT_TYPE];
1902 /// For each value type pair keep a LegalizeAction that indicates whether a
1903 /// truncating store of a specific value type and truncating type is legal.
1904 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1906 /// For each indexed mode and each value type, keep a pair of LegalizeAction
1907 /// that indicates how instruction selection should deal with the load /
1910 /// The first dimension is the value_type for the reference. The second
1911 /// dimension represents the various modes for load store.
1912 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1914 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
1915 /// indicates how instruction selection should deal with the condition code.
1917 /// Because each CC action takes up 2 bits, we need to have the array size be
1918 /// large enough to fit all of the value types. This can be done by rounding
1919 /// up the MVT::LAST_VALUETYPE value to the next multiple of 16.
1920 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 15) / 16];
1922 ValueTypeActionImpl ValueTypeActions;
1925 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
1928 std::vector<std::pair<MVT, const TargetRegisterClass*> > AvailableRegClasses;
1930 /// Targets can specify ISD nodes that they would like PerformDAGCombine
1931 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
1934 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1936 /// For operations that must be promoted to a specific type, this holds the
1937 /// destination type. This map should be sparse, so don't hold it as an
1940 /// Targets add entries to this map with AddPromotedToType(..), clients access
1941 /// this with getTypeToPromoteTo(..).
1942 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1945 /// Stores the name each libcall.
1946 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1948 /// The ISD::CondCode that should be used to test the result of each of the
1949 /// comparison libcall against zero.
1950 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1952 /// Stores the CallingConv that should be used for each libcall.
1953 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1956 /// Return true if the extension represented by \p I is free.
1957 /// \pre \p I is a sign, zero, or fp extension and
1958 /// is[Z|FP]ExtFree of the related types is not true.
1959 virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
1961 /// \brief Specify maximum number of store instructions per memset call.
1963 /// When lowering \@llvm.memset this field specifies the maximum number of
1964 /// store operations that may be substituted for the call to memset. Targets
1965 /// must set this value based on the cost threshold for that target. Targets
1966 /// should assume that the memset will be done using as many of the largest
1967 /// store operations first, followed by smaller ones, if necessary, per
1968 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1969 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1970 /// store. This only applies to setting a constant array of a constant size.
1971 unsigned MaxStoresPerMemset;
1973 /// Maximum number of stores operations that may be substituted for the call
1974 /// to memset, used for functions with OptSize attribute.
1975 unsigned MaxStoresPerMemsetOptSize;
1977 /// \brief Specify maximum bytes of store instructions per memcpy call.
1979 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1980 /// store operations that may be substituted for a call to memcpy. Targets
1981 /// must set this value based on the cost threshold for that target. Targets
1982 /// should assume that the memcpy will be done using as many of the largest
1983 /// store operations first, followed by smaller ones, if necessary, per
1984 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1985 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1986 /// and one 1-byte store. This only applies to copying a constant array of
1988 unsigned MaxStoresPerMemcpy;
1990 /// Maximum number of store operations that may be substituted for a call to
1991 /// memcpy, used for functions with OptSize attribute.
1992 unsigned MaxStoresPerMemcpyOptSize;
1994 /// \brief Specify maximum bytes of store instructions per memmove call.
1996 /// When lowering \@llvm.memmove this field specifies the maximum number of
1997 /// store instructions that may be substituted for a call to memmove. Targets
1998 /// must set this value based on the cost threshold for that target. Targets
1999 /// should assume that the memmove will be done using as many of the largest
2000 /// store operations first, followed by smaller ones, if necessary, per
2001 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2002 /// with 8-bit alignment would result in nine 1-byte stores. This only
2003 /// applies to copying a constant array of constant size.
2004 unsigned MaxStoresPerMemmove;
2006 /// Maximum number of store instructions that may be substituted for a call to
2007 /// memmove, used for functions with OptSize attribute.
2008 unsigned MaxStoresPerMemmoveOptSize;
2010 /// Tells the code generator that select is more expensive than a branch if
2011 /// the branch is usually predicted right.
2012 bool PredictableSelectIsExpensive;
2014 /// MaskAndBranchFoldingIsLegal - Indicates if the target supports folding
2015 /// a mask of a single bit, a compare, and a branch into a single instruction.
2016 bool MaskAndBranchFoldingIsLegal;
2018 /// \see enableExtLdPromotion.
2019 bool EnableExtLdPromotion;
2022 /// Return true if the value types that can be represented by the specified
2023 /// register class are all legal.
2024 bool isLegalRC(const TargetRegisterClass *RC) const;
2026 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2027 /// sequence of memory operands that is recognized by PrologEpilogInserter.
2028 MachineBasicBlock *emitPatchPoint(MachineInstr *MI,
2029 MachineBasicBlock *MBB) const;
2032 /// This class defines information used to lower LLVM code to legal SelectionDAG
2033 /// operators that the target instruction selector can accept natively.
2035 /// This class also defines callbacks that targets must implement to lower
2036 /// target-specific constructs to SelectionDAG operators.
2037 class TargetLowering : public TargetLoweringBase {
2038 TargetLowering(const TargetLowering&) = delete;
2039 void operator=(const TargetLowering&) = delete;
2042 /// NOTE: The TargetMachine owns TLOF.
2043 explicit TargetLowering(const TargetMachine &TM);
2045 /// Returns true by value, base pointer and offset pointer and addressing mode
2046 /// by reference if the node's address can be legally represented as
2047 /// pre-indexed load / store address.
2048 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2049 SDValue &/*Offset*/,
2050 ISD::MemIndexedMode &/*AM*/,
2051 SelectionDAG &/*DAG*/) const {
2055 /// Returns true by value, base pointer and offset pointer and addressing mode
2056 /// by reference if this node can be combined with a load / store to form a
2057 /// post-indexed load / store.
2058 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2060 SDValue &/*Offset*/,
2061 ISD::MemIndexedMode &/*AM*/,
2062 SelectionDAG &/*DAG*/) const {
2066 /// Return the entry encoding for a jump table in the current function. The
2067 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2068 virtual unsigned getJumpTableEncoding() const;
2070 virtual const MCExpr *
2071 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2072 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2073 MCContext &/*Ctx*/) const {
2074 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2077 /// Returns relocation base for the given PIC jumptable.
2078 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2079 SelectionDAG &DAG) const;
2081 /// This returns the relocation base for the given PIC jumptable, the same as
2082 /// getPICJumpTableRelocBase, but as an MCExpr.
2083 virtual const MCExpr *
2084 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2085 unsigned JTI, MCContext &Ctx) const;
2087 /// Return true if folding a constant offset with the given GlobalAddress is
2088 /// legal. It is frequently not legal in PIC relocation models.
2089 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2091 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2092 SDValue &Chain) const;
2094 void softenSetCCOperands(SelectionDAG &DAG, EVT VT,
2095 SDValue &NewLHS, SDValue &NewRHS,
2096 ISD::CondCode &CCCode, SDLoc DL) const;
2098 /// Returns a pair of (return value, chain).
2099 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2100 std::pair<SDValue, SDValue> makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2101 EVT RetVT, const SDValue *Ops,
2102 unsigned NumOps, bool isSigned,
2103 SDLoc dl, bool doesNotReturn = false,
2104 bool isReturnValueUsed = true) const;
2106 //===--------------------------------------------------------------------===//
2107 // TargetLowering Optimization Methods
2110 /// A convenience struct that encapsulates a DAG, and two SDValues for
2111 /// returning information from TargetLowering to its clients that want to
2113 struct TargetLoweringOpt {
2120 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2122 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2124 bool LegalTypes() const { return LegalTys; }
2125 bool LegalOperations() const { return LegalOps; }
2127 bool CombineTo(SDValue O, SDValue N) {
2133 /// Check to see if the specified operand of the specified instruction is a
2134 /// constant integer. If so, check to see if there are any bits set in the
2135 /// constant that are not demanded. If so, shrink the constant and return
2137 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
2139 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2140 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2141 /// generalized for targets with other types of implicit widening casts.
2142 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2146 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2147 /// result of Op are ever used downstream. If we can use this information to
2148 /// simplify Op, create a new simplified DAG node and return true, returning
2149 /// the original and new nodes in Old and New. Otherwise, analyze the
2150 /// expression and return a mask of KnownOne and KnownZero bits for the
2151 /// expression (used to simplify the caller). The KnownZero/One bits may only
2152 /// be accurate for those bits in the DemandedMask.
2153 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2154 APInt &KnownZero, APInt &KnownOne,
2155 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
2157 /// Determine which of the bits specified in Mask are known to be either zero
2158 /// or one and return them in the KnownZero/KnownOne bitsets.
2159 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2162 const SelectionDAG &DAG,
2163 unsigned Depth = 0) const;
2165 /// This method can be implemented by targets that want to expose additional
2166 /// information about sign bits to the DAG Combiner.
2167 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2168 const SelectionDAG &DAG,
2169 unsigned Depth = 0) const;
2171 struct DAGCombinerInfo {
2172 void *DC; // The DAG Combiner object.
2174 bool CalledByLegalizer;
2178 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2179 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2181 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2182 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2183 bool isAfterLegalizeVectorOps() const {
2184 return Level == AfterLegalizeDAG;
2186 CombineLevel getDAGCombineLevel() { return Level; }
2187 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2189 void AddToWorklist(SDNode *N);
2190 void RemoveFromWorklist(SDNode *N);
2191 SDValue CombineTo(SDNode *N, ArrayRef<SDValue> To, bool AddTo = true);
2192 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2193 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2195 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2198 /// Return if the N is a constant or constant vector equal to the true value
2199 /// from getBooleanContents().
2200 bool isConstTrueVal(const SDNode *N) const;
2202 /// Return if the N is a constant or constant vector equal to the false value
2203 /// from getBooleanContents().
2204 bool isConstFalseVal(const SDNode *N) const;
2206 /// Try to simplify a setcc built with the specified operands and cc. If it is
2207 /// unable to simplify it, return a null SDValue.
2208 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
2209 ISD::CondCode Cond, bool foldBooleans,
2210 DAGCombinerInfo &DCI, SDLoc dl) const;
2212 /// Returns true (and the GlobalValue and the offset) if the node is a
2213 /// GlobalAddress + offset.
2215 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2217 /// This method will be invoked for all target nodes and for any
2218 /// target-independent nodes that the target has registered with invoke it
2221 /// The semantics are as follows:
2223 /// SDValue.Val == 0 - No change was made
2224 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2225 /// otherwise - N should be replaced by the returned Operand.
2227 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2228 /// more complex transformations.
2230 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2232 /// Return true if it is profitable to move a following shift through this
2233 // node, adjusting any immediate operands as necessary to preserve semantics.
2234 // This transformation may not be desirable if it disrupts a particularly
2235 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2236 // By default, it returns true.
2237 virtual bool isDesirableToCommuteWithShift(const SDNode *N /*Op*/) const {
2241 /// Return true if the target has native support for the specified value type
2242 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2243 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2244 /// and some i16 instructions are slow.
2245 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2246 // By default, assume all legal types are desirable.
2247 return isTypeLegal(VT);
2250 /// Return true if it is profitable for dag combiner to transform a floating
2251 /// point op of specified opcode to a equivalent op of an integer
2252 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2253 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2258 /// This method query the target whether it is beneficial for dag combiner to
2259 /// promote the specified node. If true, it should return the desired
2260 /// promotion type by reference.
2261 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2265 //===--------------------------------------------------------------------===//
2266 // Lowering methods - These methods must be implemented by targets so that
2267 // the SelectionDAGBuilder code knows how to lower these.
2270 /// This hook must be implemented to lower the incoming (formal) arguments,
2271 /// described by the Ins array, into the specified DAG. The implementation
2272 /// should fill in the InVals array with legal-type argument values, and
2273 /// return the resulting token chain value.
2276 LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2278 const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
2279 SDLoc /*dl*/, SelectionDAG &/*DAG*/,
2280 SmallVectorImpl<SDValue> &/*InVals*/) const {
2281 llvm_unreachable("Not Implemented");
2284 struct ArgListEntry {
2293 bool isInAlloca : 1;
2294 bool isReturned : 1;
2297 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
2298 isSRet(false), isNest(false), isByVal(false), isInAlloca(false),
2299 isReturned(false), Alignment(0) { }
2301 void setAttributes(ImmutableCallSite *CS, unsigned AttrIdx);
2303 typedef std::vector<ArgListEntry> ArgListTy;
2305 /// This structure contains all information that is necessary for lowering
2306 /// calls. It is passed to TLI::LowerCallTo when the SelectionDAG builder
2307 /// needs to lower a call, and targets will see this struct in their LowerCall
2309 struct CallLoweringInfo {
2316 bool DoesNotReturn : 1;
2317 bool IsReturnValueUsed : 1;
2319 // IsTailCall should be modified by implementations of
2320 // TargetLowering::LowerCall that perform tail call conversions.
2323 unsigned NumFixedArgs;
2324 CallingConv::ID CallConv;
2329 ImmutableCallSite *CS;
2331 SmallVector<ISD::OutputArg, 32> Outs;
2332 SmallVector<SDValue, 32> OutVals;
2333 SmallVector<ISD::InputArg, 32> Ins;
2335 CallLoweringInfo(SelectionDAG &DAG)
2336 : RetTy(nullptr), RetSExt(false), RetZExt(false), IsVarArg(false),
2337 IsInReg(false), DoesNotReturn(false), IsReturnValueUsed(true),
2338 IsTailCall(false), NumFixedArgs(-1), CallConv(CallingConv::C),
2339 DAG(DAG), CS(nullptr), IsPatchPoint(false) {}
2341 CallLoweringInfo &setDebugLoc(SDLoc dl) {
2346 CallLoweringInfo &setChain(SDValue InChain) {
2351 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultType,
2352 SDValue Target, ArgListTy &&ArgsList,
2353 unsigned FixedArgs = -1) {
2358 (FixedArgs == static_cast<unsigned>(-1) ? Args.size() : FixedArgs);
2359 Args = std::move(ArgsList);
2363 CallLoweringInfo &setCallee(Type *ResultType, FunctionType *FTy,
2364 SDValue Target, ArgListTy &&ArgsList,
2365 ImmutableCallSite &Call) {
2368 IsInReg = Call.paramHasAttr(0, Attribute::InReg);
2369 DoesNotReturn = Call.doesNotReturn();
2370 IsVarArg = FTy->isVarArg();
2371 IsReturnValueUsed = !Call.getInstruction()->use_empty();
2372 RetSExt = Call.paramHasAttr(0, Attribute::SExt);
2373 RetZExt = Call.paramHasAttr(0, Attribute::ZExt);
2377 CallConv = Call.getCallingConv();
2378 NumFixedArgs = FTy->getNumParams();
2379 Args = std::move(ArgsList);
2386 CallLoweringInfo &setInRegister(bool Value = true) {
2391 CallLoweringInfo &setNoReturn(bool Value = true) {
2392 DoesNotReturn = Value;
2396 CallLoweringInfo &setVarArg(bool Value = true) {
2401 CallLoweringInfo &setTailCall(bool Value = true) {
2406 CallLoweringInfo &setDiscardResult(bool Value = true) {
2407 IsReturnValueUsed = !Value;
2411 CallLoweringInfo &setSExtResult(bool Value = true) {
2416 CallLoweringInfo &setZExtResult(bool Value = true) {
2421 CallLoweringInfo &setIsPatchPoint(bool Value = true) {
2422 IsPatchPoint = Value;
2426 ArgListTy &getArgs() {
2432 /// This function lowers an abstract call to a function into an actual call.
2433 /// This returns a pair of operands. The first element is the return value
2434 /// for the function (if RetTy is not VoidTy). The second element is the
2435 /// outgoing token chain. It calls LowerCall to do the actual lowering.
2436 std::pair<SDValue, SDValue> LowerCallTo(CallLoweringInfo &CLI) const;
2438 /// This hook must be implemented to lower calls into the specified
2439 /// DAG. The outgoing arguments to the call are described by the Outs array,
2440 /// and the values to be returned by the call are described by the Ins
2441 /// array. The implementation should fill in the InVals array with legal-type
2442 /// return values from the call, and return the resulting token chain value.
2444 LowerCall(CallLoweringInfo &/*CLI*/,
2445 SmallVectorImpl<SDValue> &/*InVals*/) const {
2446 llvm_unreachable("Not Implemented");
2449 /// Target-specific cleanup for formal ByVal parameters.
2450 virtual void HandleByVal(CCState *, unsigned &, unsigned) const {}
2452 /// This hook should be implemented to check whether the return values
2453 /// described by the Outs array can fit into the return registers. If false
2454 /// is returned, an sret-demotion is performed.
2455 virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
2456 MachineFunction &/*MF*/, bool /*isVarArg*/,
2457 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2458 LLVMContext &/*Context*/) const
2460 // Return true by default to get preexisting behavior.
2464 /// This hook must be implemented to lower outgoing return values, described
2465 /// by the Outs array, into the specified DAG. The implementation should
2466 /// return the resulting token chain value.
2468 LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
2470 const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
2471 const SmallVectorImpl<SDValue> &/*OutVals*/,
2472 SDLoc /*dl*/, SelectionDAG &/*DAG*/) const {
2473 llvm_unreachable("Not Implemented");
2476 /// Return true if result of the specified node is used by a return node
2477 /// only. It also compute and return the input chain for the tail call.
2479 /// This is used to determine whether it is possible to codegen a libcall as
2480 /// tail call at legalization time.
2481 virtual bool isUsedByReturnOnly(SDNode *, SDValue &/*Chain*/) const {
2485 /// Return true if the target may be able emit the call instruction as a tail
2486 /// call. This is used by optimization passes to determine if it's profitable
2487 /// to duplicate return instructions to enable tailcall optimization.
2488 virtual bool mayBeEmittedAsTailCall(CallInst *) const {
2492 /// Return the builtin name for the __builtin___clear_cache intrinsic
2493 /// Default is to invoke the clear cache library call
2494 virtual const char * getClearCacheBuiltinName() const {
2495 return "__clear_cache";
2498 /// Return the register ID of the name passed in. Used by named register
2499 /// global variables extension. There is no target-independent behaviour
2500 /// so the default action is to bail.
2501 virtual unsigned getRegisterByName(const char* RegName, EVT VT,
2502 SelectionDAG &DAG) const {
2503 report_fatal_error("Named registers not implemented for this target");
2506 /// Return the type that should be used to zero or sign extend a
2507 /// zeroext/signext integer argument or return value. FIXME: Most C calling
2508 /// convention requires the return type to be promoted, but this is not true
2509 /// all the time, e.g. i1 on x86-64. It is also not necessary for non-C
2510 /// calling conventions. The frontend should handle this and include all of
2511 /// the necessary information.
2512 virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
2513 ISD::NodeType /*ExtendKind*/) const {
2514 EVT MinVT = getRegisterType(Context, MVT::i32);
2515 return VT.bitsLT(MinVT) ? MinVT : VT;
2518 /// For some targets, an LLVM struct type must be broken down into multiple
2519 /// simple types, but the calling convention specifies that the entire struct
2520 /// must be passed in a block of consecutive registers.
2522 functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv,
2523 bool isVarArg) const {
2527 /// Returns a 0 terminated array of registers that can be safely used as
2528 /// scratch registers.
2529 virtual const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const {
2533 /// This callback is used to prepare for a volatile or atomic load.
2534 /// It takes a chain node as input and returns the chain for the load itself.
2536 /// Having a callback like this is necessary for targets like SystemZ,
2537 /// which allows a CPU to reuse the result of a previous load indefinitely,
2538 /// even if a cache-coherent store is performed by another CPU. The default
2539 /// implementation does nothing.
2540 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
2541 SelectionDAG &DAG) const {
2545 /// This callback is invoked by the type legalizer to legalize nodes with an
2546 /// illegal operand type but legal result types. It replaces the
2547 /// LowerOperation callback in the type Legalizer. The reason we can not do
2548 /// away with LowerOperation entirely is that LegalizeDAG isn't yet ready to
2549 /// use this callback.
2551 /// TODO: Consider merging with ReplaceNodeResults.
2553 /// The target places new result values for the node in Results (their number
2554 /// and types must exactly match those of the original return values of
2555 /// the node), or leaves Results empty, which indicates that the node is not
2556 /// to be custom lowered after all.
2557 /// The default implementation calls LowerOperation.
2558 virtual void LowerOperationWrapper(SDNode *N,
2559 SmallVectorImpl<SDValue> &Results,
2560 SelectionDAG &DAG) const;
2562 /// This callback is invoked for operations that are unsupported by the
2563 /// target, which are registered to use 'custom' lowering, and whose defined
2564 /// values are all legal. If the target has no operations that require custom
2565 /// lowering, it need not implement this. The default implementation of this
2567 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
2569 /// This callback is invoked when a node result type is illegal for the
2570 /// target, and the operation was registered to use 'custom' lowering for that
2571 /// result type. The target places new result values for the node in Results
2572 /// (their number and types must exactly match those of the original return
2573 /// values of the node), or leaves Results empty, which indicates that the
2574 /// node is not to be custom lowered after all.
2576 /// If the target has no operations that require custom lowering, it need not
2577 /// implement this. The default implementation aborts.
2578 virtual void ReplaceNodeResults(SDNode * /*N*/,
2579 SmallVectorImpl<SDValue> &/*Results*/,
2580 SelectionDAG &/*DAG*/) const {
2581 llvm_unreachable("ReplaceNodeResults not implemented for this target!");
2584 /// This method returns the name of a target specific DAG node.
2585 virtual const char *getTargetNodeName(unsigned Opcode) const;
2587 /// This method returns a target specific FastISel object, or null if the
2588 /// target does not support "fast" ISel.
2589 virtual FastISel *createFastISel(FunctionLoweringInfo &,
2590 const TargetLibraryInfo *) const {
2595 bool verifyReturnAddressArgumentIsConstant(SDValue Op,
2596 SelectionDAG &DAG) const;
2598 //===--------------------------------------------------------------------===//
2599 // Inline Asm Support hooks
2602 /// This hook allows the target to expand an inline asm call to be explicit
2603 /// llvm code if it wants to. This is useful for turning simple inline asms
2604 /// into LLVM intrinsics, which gives the compiler more information about the
2605 /// behavior of the code.
2606 virtual bool ExpandInlineAsm(CallInst *) const {
2610 enum ConstraintType {
2611 C_Register, // Constraint represents specific register(s).
2612 C_RegisterClass, // Constraint represents any of register(s) in class.
2613 C_Memory, // Memory constraint.
2614 C_Other, // Something else.
2615 C_Unknown // Unsupported constraint.
2618 enum ConstraintWeight {
2620 CW_Invalid = -1, // No match.
2621 CW_Okay = 0, // Acceptable.
2622 CW_Good = 1, // Good weight.
2623 CW_Better = 2, // Better weight.
2624 CW_Best = 3, // Best weight.
2626 // Well-known weights.
2627 CW_SpecificReg = CW_Okay, // Specific register operands.
2628 CW_Register = CW_Good, // Register operands.
2629 CW_Memory = CW_Better, // Memory operands.
2630 CW_Constant = CW_Best, // Constant operand.
2631 CW_Default = CW_Okay // Default or don't know type.
2634 /// This contains information for each constraint that we are lowering.
2635 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
2636 /// This contains the actual string for the code, like "m". TargetLowering
2637 /// picks the 'best' code from ConstraintInfo::Codes that most closely
2638 /// matches the operand.
2639 std::string ConstraintCode;
2641 /// Information about the constraint code, e.g. Register, RegisterClass,
2642 /// Memory, Other, Unknown.
2643 TargetLowering::ConstraintType ConstraintType;
2645 /// If this is the result output operand or a clobber, this is null,
2646 /// otherwise it is the incoming operand to the CallInst. This gets
2647 /// modified as the asm is processed.
2648 Value *CallOperandVal;
2650 /// The ValueType for the operand value.
2653 /// Return true of this is an input operand that is a matching constraint
2655 bool isMatchingInputConstraint() const;
2657 /// If this is an input matching constraint, this method returns the output
2658 /// operand it matches.
2659 unsigned getMatchedOperand() const;
2661 /// Copy constructor for copying from a ConstraintInfo.
2662 AsmOperandInfo(InlineAsm::ConstraintInfo Info)
2663 : InlineAsm::ConstraintInfo(std::move(Info)),
2664 ConstraintType(TargetLowering::C_Unknown), CallOperandVal(nullptr),
2665 ConstraintVT(MVT::Other) {}
2668 typedef std::vector<AsmOperandInfo> AsmOperandInfoVector;
2670 /// Split up the constraint string from the inline assembly value into the
2671 /// specific constraints and their prefixes, and also tie in the associated
2672 /// operand values. If this returns an empty vector, and if the constraint
2673 /// string itself isn't empty, there was an error parsing.
2674 virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL,
2675 const TargetRegisterInfo *TRI,
2676 ImmutableCallSite CS) const;
2678 /// Examine constraint type and operand type and determine a weight value.
2679 /// The operand object must already have been set up with the operand type.
2680 virtual ConstraintWeight getMultipleConstraintMatchWeight(
2681 AsmOperandInfo &info, int maIndex) const;
2683 /// Examine constraint string and operand type and determine a weight value.
2684 /// The operand object must already have been set up with the operand type.
2685 virtual ConstraintWeight getSingleConstraintMatchWeight(
2686 AsmOperandInfo &info, const char *constraint) const;
2688 /// Determines the constraint code and constraint type to use for the specific
2689 /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType.
2690 /// If the actual operand being passed in is available, it can be passed in as
2691 /// Op, otherwise an empty SDValue can be passed.
2692 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
2694 SelectionDAG *DAG = nullptr) const;
2696 /// Given a constraint, return the type of constraint it is for this target.
2697 virtual ConstraintType getConstraintType(StringRef Constraint) const;
2699 /// Given a physical register constraint (e.g. {edx}), return the register
2700 /// number and the register class for the register.
2702 /// Given a register class constraint, like 'r', if this corresponds directly
2703 /// to an LLVM register class, return a register of 0 and the register class
2706 /// This should only be used for C_Register constraints. On error, this
2707 /// returns a register number of 0 and a null register class pointer.
2708 virtual std::pair<unsigned, const TargetRegisterClass *>
2709 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
2710 StringRef Constraint, MVT VT) const;
2712 virtual unsigned getInlineAsmMemConstraint(StringRef ConstraintCode) const {
2713 if (ConstraintCode == "i")
2714 return InlineAsm::Constraint_i;
2715 else if (ConstraintCode == "m")
2716 return InlineAsm::Constraint_m;
2717 return InlineAsm::Constraint_Unknown;
2720 /// Try to replace an X constraint, which matches anything, with another that
2721 /// has more specific requirements based on the type of the corresponding
2722 /// operand. This returns null if there is no replacement to make.
2723 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
2725 /// Lower the specified operand into the Ops vector. If it is invalid, don't
2726 /// add anything to Ops.
2727 virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
2728 std::vector<SDValue> &Ops,
2729 SelectionDAG &DAG) const;
2731 //===--------------------------------------------------------------------===//
2732 // Div utility functions
2734 SDValue BuildSDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2735 bool IsAfterLegalization,
2736 std::vector<SDNode *> *Created) const;
2737 SDValue BuildUDIV(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
2738 bool IsAfterLegalization,
2739 std::vector<SDNode *> *Created) const;
2741 /// Targets may override this function to provide custom SDIV lowering for
2742 /// power-of-2 denominators. If the target returns an empty SDValue, LLVM
2743 /// assumes SDIV is expensive and replaces it with a series of other integer
2745 virtual SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor,
2747 std::vector<SDNode *> *Created) const;
2749 /// Indicate whether this target prefers to combine FDIVs with the same
2750 /// divisor. If the transform should never be done, return zero. If the
2751 /// transform should be done, return the minimum number of divisor uses
2752 /// that must exist.
2753 virtual unsigned combineRepeatedFPDivisors() const {
2757 /// Hooks for building estimates in place of slower divisions and square
2760 /// Return a reciprocal square root estimate value for the input operand.
2761 /// The RefinementSteps output is the number of Newton-Raphson refinement
2762 /// iterations required to generate a sufficient (though not necessarily
2763 /// IEEE-754 compliant) estimate for the value type.
2764 /// The boolean UseOneConstNR output is used to select a Newton-Raphson
2765 /// algorithm implementation that uses one constant or two constants.
2766 /// A target may choose to implement its own refinement within this function.
2767 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2768 /// any further refinement of the estimate.
2769 /// An empty SDValue return means no estimate sequence can be created.
2770 virtual SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2771 unsigned &RefinementSteps,
2772 bool &UseOneConstNR) const {
2776 /// Return a reciprocal estimate value for the input operand.
2777 /// The RefinementSteps output is the number of Newton-Raphson refinement
2778 /// iterations required to generate a sufficient (though not necessarily
2779 /// IEEE-754 compliant) estimate for the value type.
2780 /// A target may choose to implement its own refinement within this function.
2781 /// If that's true, then return '0' as the number of RefinementSteps to avoid
2782 /// any further refinement of the estimate.
2783 /// An empty SDValue return means no estimate sequence can be created.
2784 virtual SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
2785 unsigned &RefinementSteps) const {
2789 //===--------------------------------------------------------------------===//
2790 // Legalization utility functions
2793 /// Expand a MUL into two nodes. One that computes the high bits of
2794 /// the result and one that computes the low bits.
2795 /// \param HiLoVT The value type to use for the Lo and Hi nodes.
2796 /// \param LL Low bits of the LHS of the MUL. You can use this parameter
2797 /// if you want to control how low bits are extracted from the LHS.
2798 /// \param LH High bits of the LHS of the MUL. See LL for meaning.
2799 /// \param RL Low bits of the RHS of the MUL. See LL for meaning
2800 /// \param RH High bits of the RHS of the MUL. See LL for meaning.
2801 /// \returns true if the node has been expanded. false if it has not
2802 bool expandMUL(SDNode *N, SDValue &Lo, SDValue &Hi, EVT HiLoVT,
2803 SelectionDAG &DAG, SDValue LL = SDValue(),
2804 SDValue LH = SDValue(), SDValue RL = SDValue(),
2805 SDValue RH = SDValue()) const;
2807 /// Expand float(f32) to SINT(i64) conversion
2808 /// \param N Node to expand
2809 /// \param Result output after conversion
2810 /// \returns True, if the expansion was successful, false otherwise
2811 bool expandFP_TO_SINT(SDNode *N, SDValue &Result, SelectionDAG &DAG) const;
2813 //===--------------------------------------------------------------------===//
2814 // Instruction Emitting Hooks
2817 /// This method should be implemented by targets that mark instructions with
2818 /// the 'usesCustomInserter' flag. These instructions are special in various
2819 /// ways, which require special support to insert. The specified MachineInstr
2820 /// is created but not inserted into any basic blocks, and this method is
2821 /// called to expand it into a sequence of instructions, potentially also
2822 /// creating new basic blocks and control flow.
2823 /// As long as the returned basic block is different (i.e., we created a new
2824 /// one), the custom inserter is free to modify the rest of \p MBB.
2825 virtual MachineBasicBlock *
2826 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
2828 /// This method should be implemented by targets that mark instructions with
2829 /// the 'hasPostISelHook' flag. These instructions must be adjusted after
2830 /// instruction selection by target hooks. e.g. To fill in optional defs for
2831 /// ARM 's' setting instructions.
2833 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
2835 /// If this function returns true, SelectionDAGBuilder emits a
2836 /// LOAD_STACK_GUARD node when it is lowering Intrinsic::stackprotector.
2837 virtual bool useLoadStackGuardNode() const {
2841 /// Lower TLS global address SDNode for target independent emulated TLS model.
2842 virtual SDValue LowerToTLSEmulatedModel(const GlobalAddressSDNode *GA,
2843 SelectionDAG &DAG) const;
2846 /// Given an LLVM IR type and return type attributes, compute the return value
2847 /// EVTs and flags, and optionally also the offsets, if the return value is
2848 /// being lowered to memory.
2849 void GetReturnInfo(Type *ReturnType, AttributeSet attr,
2850 SmallVectorImpl<ISD::OutputArg> &Outs,
2851 const TargetLowering &TLI, const DataLayout &DL);
2853 } // end llvm namespace