1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/Type.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/Support/DataTypes.h"
36 class TargetRegisterClass;
40 class MachineBasicBlock;
43 //===----------------------------------------------------------------------===//
44 /// TargetLowering - This class defines information used to lower LLVM code to
45 /// legal SelectionDAG operators that the target instruction selector can accept
48 /// This class also defines callbacks that targets must implement to lower
49 /// target-specific constructs to SelectionDAG operators.
51 class TargetLowering {
53 /// LegalizeAction - This enum indicates whether operations are valid for a
54 /// target, and if not, what action should be used to make them valid.
56 Legal, // The target natively supports this operation.
57 Promote, // This operation should be executed in a larger type.
58 Expand, // Try to expand this to other ops, otherwise use a libcall.
59 Custom // Use the LowerOperation hook to implement custom lowering.
62 enum OutOfRangeShiftAmount {
63 Undefined, // Oversized shift amounts are undefined (default).
64 Mask, // Shift amounts are auto masked (anded) to value size.
65 Extend // Oversized shift pulls in zeros or sign bits.
68 enum SetCCResultValue {
69 UndefinedSetCCResult, // SetCC returns a garbage/unknown extend.
70 ZeroOrOneSetCCResult, // SetCC returns a zero extended result.
71 ZeroOrNegativeOneSetCCResult // SetCC returns a sign extended result.
74 enum SchedPreference {
75 SchedulingForLatency, // Scheduling for shortest total latency.
76 SchedulingForRegPressure // Scheduling for lowest register pressure.
79 TargetLowering(TargetMachine &TM);
80 virtual ~TargetLowering();
82 TargetMachine &getTargetMachine() const { return TM; }
83 const TargetData &getTargetData() const { return TD; }
85 bool isLittleEndian() const { return IsLittleEndian; }
86 MVT::ValueType getPointerTy() const { return PointerTy; }
87 MVT::ValueType getShiftAmountTy() const { return ShiftAmountTy; }
88 OutOfRangeShiftAmount getShiftAmountFlavor() const {return ShiftAmtHandling; }
90 /// isSetCCExpensive - Return true if the setcc operation is expensive for
92 bool isSetCCExpensive() const { return SetCCIsExpensive; }
94 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
95 /// a sequence of several shifts, adds, and multiplies for this target.
96 bool isIntDivCheap() const { return IntDivIsCheap; }
98 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
100 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
102 /// getSetCCResultTy - Return the ValueType of the result of setcc operations.
104 MVT::ValueType getSetCCResultTy() const { return SetCCResultTy; }
106 /// getSetCCResultContents - For targets without boolean registers, this flag
107 /// returns information about the contents of the high-bits in the setcc
109 SetCCResultValue getSetCCResultContents() const { return SetCCResultContents;}
111 /// getSchedulingPreference - Return target scheduling preference.
112 SchedPreference getSchedulingPreference() const {
113 return SchedPreferenceInfo;
116 /// getRegClassFor - Return the register class that should be used for the
117 /// specified value type. This may only be called on legal types.
118 TargetRegisterClass *getRegClassFor(MVT::ValueType VT) const {
119 TargetRegisterClass *RC = RegClassForVT[VT];
120 assert(RC && "This value type is not natively supported!");
124 /// isTypeLegal - Return true if the target has native support for the
125 /// specified value type. This means that it has a register that directly
126 /// holds it without promotions or expansions.
127 bool isTypeLegal(MVT::ValueType VT) const {
128 return RegClassForVT[VT] != 0;
131 class ValueTypeActionImpl {
132 /// ValueTypeActions - This is a bitvector that contains two bits for each
133 /// value type, where the two bits correspond to the LegalizeAction enum.
134 /// This can be queried with "getTypeAction(VT)".
135 uint32_t ValueTypeActions[2];
137 ValueTypeActionImpl() {
138 ValueTypeActions[0] = ValueTypeActions[1] = 0;
140 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
141 ValueTypeActions[0] = RHS.ValueTypeActions[0];
142 ValueTypeActions[1] = RHS.ValueTypeActions[1];
145 LegalizeAction getTypeAction(MVT::ValueType VT) const {
146 return (LegalizeAction)((ValueTypeActions[VT>>4] >> ((2*VT) & 31)) & 3);
148 void setTypeAction(MVT::ValueType VT, LegalizeAction Action) {
149 assert(unsigned(VT >> 4) <
150 sizeof(ValueTypeActions)/sizeof(ValueTypeActions[0]));
151 ValueTypeActions[VT>>4] |= Action << ((VT*2) & 31);
155 const ValueTypeActionImpl &getValueTypeActions() const {
156 return ValueTypeActions;
159 /// getTypeAction - Return how we should legalize values of this type, either
160 /// it is already legal (return 'Legal') or we need to promote it to a larger
161 /// type (return 'Promote'), or we need to expand it into multiple registers
162 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
163 LegalizeAction getTypeAction(MVT::ValueType VT) const {
164 return ValueTypeActions.getTypeAction(VT);
167 /// getTypeToTransformTo - For types supported by the target, this is an
168 /// identity function. For types that must be promoted to larger types, this
169 /// returns the larger type to promote to. For types that are larger than the
170 /// largest integer register, this contains one step in the expansion to get
171 /// to the smaller register.
172 MVT::ValueType getTypeToTransformTo(MVT::ValueType VT) const {
173 return TransformToType[VT];
176 typedef std::vector<double>::const_iterator legal_fpimm_iterator;
177 legal_fpimm_iterator legal_fpimm_begin() const {
178 return LegalFPImmediates.begin();
180 legal_fpimm_iterator legal_fpimm_end() const {
181 return LegalFPImmediates.end();
184 /// getOperationAction - Return how this operation should be treated: either
185 /// it is legal, needs to be promoted to a larger size, needs to be
186 /// expanded to some other code sequence, or the target has a custom expander
188 LegalizeAction getOperationAction(unsigned Op, MVT::ValueType VT) const {
189 return (LegalizeAction)((OpActions[Op] >> (2*VT)) & 3);
192 /// isOperationLegal - Return true if the specified operation is legal on this
194 bool isOperationLegal(unsigned Op, MVT::ValueType VT) const {
195 return getOperationAction(Op, VT) == Legal ||
196 getOperationAction(Op, VT) == Custom;
200 /// isVectorShuffleLegal - Return true if a vector shuffle is legal with the
201 /// specified mask and type. Targets can specify exactly which masks they
202 /// support and the code generator is tasked with not creating illegal masks.
203 bool isShuffleLegal(MVT::ValueType VT, SDOperand Mask) const {
204 return isOperationLegal(ISD::VECTOR_SHUFFLE, VT) &&
205 isShuffleMaskLegal(Mask, VT);
208 /// getTypeToPromoteTo - If the action for this operation is to promote, this
209 /// method returns the ValueType to promote to.
210 MVT::ValueType getTypeToPromoteTo(unsigned Op, MVT::ValueType VT) const {
211 assert(getOperationAction(Op, VT) == Promote &&
212 "This operation isn't promoted!");
213 MVT::ValueType NVT = VT;
215 NVT = (MVT::ValueType)(NVT+1);
216 assert(MVT::isInteger(NVT) == MVT::isInteger(VT) && NVT != MVT::isVoid &&
217 "Didn't find type to promote to!");
218 } while (!isTypeLegal(NVT) ||
219 getOperationAction(Op, NVT) == Promote);
223 /// getValueType - Return the MVT::ValueType corresponding to this LLVM type.
224 /// This is fixed by the LLVM operations except for the pointer size.
225 MVT::ValueType getValueType(const Type *Ty) const {
226 switch (Ty->getTypeID()) {
227 default: assert(0 && "Unknown type!");
228 case Type::VoidTyID: return MVT::isVoid;
229 case Type::BoolTyID: return MVT::i1;
230 case Type::UByteTyID:
231 case Type::SByteTyID: return MVT::i8;
232 case Type::ShortTyID:
233 case Type::UShortTyID: return MVT::i16;
235 case Type::UIntTyID: return MVT::i32;
237 case Type::ULongTyID: return MVT::i64;
238 case Type::FloatTyID: return MVT::f32;
239 case Type::DoubleTyID: return MVT::f64;
240 case Type::PointerTyID: return PointerTy;
241 case Type::PackedTyID: return MVT::Vector;
245 /// getNumElements - Return the number of registers that this ValueType will
246 /// eventually require. This is always one for all non-integer types, is
247 /// one for any types promoted to live in larger registers, but may be more
248 /// than one for types (like i64) that are split into pieces.
249 unsigned getNumElements(MVT::ValueType VT) const {
250 return NumElementsForVT[VT];
253 /// hasTargetDAGCombine - If true, the target has custom DAG combine
254 /// transformations that it can perform for the specified node.
255 bool hasTargetDAGCombine(ISD::NodeType NT) const {
256 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
259 /// This function returns the maximum number of store operations permitted
260 /// to replace a call to llvm.memset. The value is set by the target at the
261 /// performance threshold for such a replacement.
262 /// @brief Get maximum # of store operations permitted for llvm.memset
263 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
265 /// This function returns the maximum number of store operations permitted
266 /// to replace a call to llvm.memcpy. The value is set by the target at the
267 /// performance threshold for such a replacement.
268 /// @brief Get maximum # of store operations permitted for llvm.memcpy
269 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
271 /// This function returns the maximum number of store operations permitted
272 /// to replace a call to llvm.memmove. The value is set by the target at the
273 /// performance threshold for such a replacement.
274 /// @brief Get maximum # of store operations permitted for llvm.memmove
275 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
277 /// This function returns true if the target allows unaligned memory accesses.
278 /// This is used, for example, in situations where an array copy/move/set is
279 /// converted to a sequence of store operations. It's use helps to ensure that
280 /// such replacements don't generate code that causes an alignment error
281 /// (trap) on the target machine.
282 /// @brief Determine if the target supports unaligned memory accesses.
283 bool allowsUnalignedMemoryAccesses() const {
284 return allowUnalignedMemoryAccesses;
287 /// usesUnderscoreSetJmpLongJmp - Determine if we should use _setjmp or setjmp
288 /// to implement llvm.setjmp.
289 bool usesUnderscoreSetJmpLongJmp() const {
290 return UseUnderscoreSetJmpLongJmp;
293 /// getStackPointerRegisterToSaveRestore - If a physical register, this
294 /// specifies the register that llvm.savestack/llvm.restorestack should save
296 unsigned getStackPointerRegisterToSaveRestore() const {
297 return StackPointerRegisterToSaveRestore;
300 //===--------------------------------------------------------------------===//
301 // TargetLowering Optimization Methods
304 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
305 /// SDOperands for returning information from TargetLowering to its clients
306 /// that want to combine
307 struct TargetLoweringOpt {
312 TargetLoweringOpt(SelectionDAG &InDAG) : DAG(InDAG) {}
314 bool CombineTo(SDOperand O, SDOperand N) {
320 /// ShrinkDemandedConstant - Check to see if the specified operand of the
321 /// specified instruction is a constant integer. If so, check to see if there
322 /// are any bits set in the constant that are not demanded. If so, shrink the
323 /// constant and return true.
324 bool ShrinkDemandedConstant(SDOperand Op, uint64_t Demanded);
327 /// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We
328 /// use this predicate to simplify operations downstream. Op and Mask are
329 /// known to be the same type.
330 bool MaskedValueIsZero(SDOperand Op, uint64_t Mask, unsigned Depth = 0)
333 /// ComputeMaskedBits - Determine which of the bits specified in Mask are
334 /// known to be either zero or one and return them in the KnownZero/KnownOne
335 /// bitsets. This code only analyzes bits in Mask, in order to short-circuit
336 /// processing. Targets can implement the computeMaskedBitsForTargetNode
337 /// method, to allow target nodes to be understood.
338 void ComputeMaskedBits(SDOperand Op, uint64_t Mask, uint64_t &KnownZero,
339 uint64_t &KnownOne, unsigned Depth = 0) const;
341 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
342 /// DemandedMask bits of the result of Op are ever used downstream. If we can
343 /// use this information to simplify Op, create a new simplified DAG node and
344 /// return true, returning the original and new nodes in Old and New.
345 /// Otherwise, analyze the expression and return a mask of KnownOne and
346 /// KnownZero bits for the expression (used to simplify the caller).
347 /// The KnownZero/One bits may only be accurate for those bits in the
349 bool SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
350 uint64_t &KnownZero, uint64_t &KnownOne,
351 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
353 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
354 /// Mask are known to be either zero or one and return them in the
355 /// KnownZero/KnownOne bitsets.
356 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
360 unsigned Depth = 0) const;
362 struct DAGCombinerInfo {
363 void *DC; // The DAG Combiner object.
368 DAGCombinerInfo(SelectionDAG &dag, bool bl, void *dc)
369 : DC(dc), BeforeLegalize(bl), DAG(dag) {}
371 bool isBeforeLegalize() const { return BeforeLegalize; }
373 void AddToWorklist(SDNode *N);
374 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To);
375 SDOperand CombineTo(SDNode *N, SDOperand Res);
376 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1);
379 /// PerformDAGCombine - This method will be invoked for all target nodes and
380 /// for any target-independent nodes that the target has registered with
383 /// The semantics are as follows:
385 /// SDOperand.Val == 0 - No change was made
386 /// SDOperand.Val == N - N was replaced, is dead, and is already handled.
387 /// otherwise - N should be replaced by the returned Operand.
389 /// In addition, methods provided by DAGCombinerInfo may be used to perform
390 /// more complex transformations.
392 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
394 //===--------------------------------------------------------------------===//
395 // TargetLowering Configuration Methods - These methods should be invoked by
396 // the derived class constructor to configure this object for the target.
401 /// setShiftAmountType - Describe the type that should be used for shift
402 /// amounts. This type defaults to the pointer type.
403 void setShiftAmountType(MVT::ValueType VT) { ShiftAmountTy = VT; }
405 /// setSetCCResultType - Describe the type that shoudl be used as the result
406 /// of a setcc operation. This defaults to the pointer type.
407 void setSetCCResultType(MVT::ValueType VT) { SetCCResultTy = VT; }
409 /// setSetCCResultContents - Specify how the target extends the result of a
410 /// setcc operation in a register.
411 void setSetCCResultContents(SetCCResultValue Ty) { SetCCResultContents = Ty; }
413 /// setSchedulingPreference - Specify the target scheduling preference.
414 void setSchedulingPreference(SchedPreference Pref) {
415 SchedPreferenceInfo = Pref;
418 /// setShiftAmountFlavor - Describe how the target handles out of range shift
420 void setShiftAmountFlavor(OutOfRangeShiftAmount OORSA) {
421 ShiftAmtHandling = OORSA;
424 /// setUseUnderscoreSetJmpLongJmp - Indicate whether this target prefers to
425 /// use _setjmp and _longjmp to or implement llvm.setjmp/llvm.longjmp or
426 /// the non _ versions. Defaults to false.
427 void setUseUnderscoreSetJmpLongJmp(bool Val) {
428 UseUnderscoreSetJmpLongJmp = Val;
431 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
432 /// specifies the register that llvm.savestack/llvm.restorestack should save
434 void setStackPointerRegisterToSaveRestore(unsigned R) {
435 StackPointerRegisterToSaveRestore = R;
438 /// setSetCCIxExpensive - This is a short term hack for targets that codegen
439 /// setcc as a conditional branch. This encourages the code generator to fold
440 /// setcc operations into other operations if possible.
441 void setSetCCIsExpensive() { SetCCIsExpensive = true; }
443 /// setIntDivIsCheap - Tells the code generator that integer divide is
444 /// expensive, and if possible, should be replaced by an alternate sequence
445 /// of instructions not containing an integer divide.
446 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
448 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
449 /// srl/add/sra for a signed divide by power of two, and let the target handle
451 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
453 /// addRegisterClass - Add the specified register class as an available
454 /// regclass for the specified value type. This indicates the selector can
455 /// handle values of that class natively.
456 void addRegisterClass(MVT::ValueType VT, TargetRegisterClass *RC) {
457 AvailableRegClasses.push_back(std::make_pair(VT, RC));
458 RegClassForVT[VT] = RC;
461 /// computeRegisterProperties - Once all of the register classes are added,
462 /// this allows us to compute derived properties we expose.
463 void computeRegisterProperties();
465 /// setOperationAction - Indicate that the specified operation does not work
466 /// with the specified type and indicate what to do about it.
467 void setOperationAction(unsigned Op, MVT::ValueType VT,
468 LegalizeAction Action) {
469 assert(VT < 32 && Op < sizeof(OpActions)/sizeof(OpActions[0]) &&
470 "Table isn't big enough!");
471 OpActions[Op] &= ~(3ULL << VT*2);
472 OpActions[Op] |= (uint64_t)Action << VT*2;
475 /// addLegalFPImmediate - Indicate that this target can instruction select
476 /// the specified FP immediate natively.
477 void addLegalFPImmediate(double Imm) {
478 LegalFPImmediates.push_back(Imm);
481 /// setTargetDAGCombine - Targets should invoke this method for each target
482 /// independent node that they want to provide a custom DAG combiner for by
483 /// implementing the PerformDAGCombine virtual method.
484 void setTargetDAGCombine(ISD::NodeType NT) {
485 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
488 /// isShuffleMaskLegal - Targets can use this to indicate that they only
489 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
490 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
491 /// are assumed to be legal.
492 virtual bool isShuffleMaskLegal(SDOperand Mask, MVT::ValueType VT) const {
498 //===--------------------------------------------------------------------===//
499 // Lowering methods - These methods must be implemented by targets so that
500 // the SelectionDAGLowering code knows how to lower these.
503 /// LowerArguments - This hook must be implemented to indicate how we should
504 /// lower the arguments for the specified function, into the specified DAG.
505 virtual std::vector<SDOperand>
506 LowerArguments(Function &F, SelectionDAG &DAG) = 0;
508 /// LowerCallTo - This hook lowers an abstract call to a function into an
509 /// actual call. This returns a pair of operands. The first element is the
510 /// return value for the function (if RetTy is not VoidTy). The second
511 /// element is the outgoing token chain.
512 typedef std::vector<std::pair<SDOperand, const Type*> > ArgListTy;
513 virtual std::pair<SDOperand, SDOperand>
514 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
515 unsigned CallingConv, bool isTailCall, SDOperand Callee,
516 ArgListTy &Args, SelectionDAG &DAG) = 0;
518 /// LowerFrameReturnAddress - This hook lowers a call to llvm.returnaddress or
519 /// llvm.frameaddress (depending on the value of the first argument). The
520 /// return values are the result pointer and the resultant token chain. If
521 /// not implemented, both of these intrinsics will return null.
522 virtual std::pair<SDOperand, SDOperand>
523 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
526 /// LowerOperation - This callback is invoked for operations that are
527 /// unsupported by the target, which are registered to use 'custom' lowering,
528 /// and whose defined values are all legal.
529 /// If the target has no operations that require custom lowering, it need not
530 /// implement this. The default implementation of this aborts.
531 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
533 /// CustomPromoteOperation - This callback is invoked for operations that are
534 /// unsupported by the target, are registered to use 'custom' lowering, and
535 /// whose type needs to be promoted.
536 virtual SDOperand CustomPromoteOperation(SDOperand Op, SelectionDAG &DAG);
538 /// getTargetNodeName() - This method returns the name of a target specific
540 virtual const char *getTargetNodeName(unsigned Opcode) const;
542 //===--------------------------------------------------------------------===//
543 // Inline Asm Support hooks
546 enum ConstraintType {
547 C_Register, // Constraint represents a single register.
548 C_RegisterClass, // Constraint represents one or more registers.
549 C_Memory, // Memory constraint.
550 C_Other, // Something else.
551 C_Unknown // Unsupported constraint.
554 /// getConstraintType - Given a constraint letter, return the type of
555 /// constraint it is for this target.
556 virtual ConstraintType getConstraintType(char ConstraintLetter) const;
559 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
560 /// return a list of registers that can be used to satisfy the constraint.
561 /// This should only be used for C_RegisterClass constraints.
562 virtual std::vector<unsigned>
563 getRegClassForInlineAsmConstraint(const std::string &Constraint,
564 MVT::ValueType VT) const;
566 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
567 /// {edx}), return the register number and the register class for the
568 /// register. This should only be used for C_Register constraints. On error,
569 /// this returns a register number of 0.
570 virtual std::pair<unsigned, const TargetRegisterClass*>
571 getRegForInlineAsmConstraint(const std::string &Constraint,
572 MVT::ValueType VT) const;
575 /// isOperandValidForConstraint - Return true if the specified SDOperand is
576 /// valid for the specified target constraint letter.
577 virtual bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
579 //===--------------------------------------------------------------------===//
583 // InsertAtEndOfBasicBlock - This method should be implemented by targets that
584 // mark instructions with the 'usesCustomDAGSchedInserter' flag. These
585 // instructions are special in various ways, which require special support to
586 // insert. The specified MachineInstr is created but not inserted into any
587 // basic blocks, and the scheduler passes ownership of it to this method.
588 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
589 MachineBasicBlock *MBB);
591 //===--------------------------------------------------------------------===//
592 // Loop Strength Reduction hooks
595 /// isLegalAddressImmediate - Return true if the integer value or GlobalValue
596 /// can be used as the offset of the target addressing mode.
597 virtual bool isLegalAddressImmediate(int64_t V) const;
598 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
600 typedef std::vector<unsigned>::const_iterator legal_am_scale_iterator;
601 legal_am_scale_iterator legal_am_scale_begin() const {
602 return LegalAddressScales.begin();
604 legal_am_scale_iterator legal_am_scale_end() const {
605 return LegalAddressScales.end();
609 /// addLegalAddressScale - Add a integer (> 1) value which can be used as
610 /// scale in the target addressing mode. Note: the ordering matters so the
611 /// least efficient ones should be entered first.
612 void addLegalAddressScale(unsigned Scale) {
613 LegalAddressScales.push_back(Scale);
617 std::vector<unsigned> LegalAddressScales;
621 const TargetData &TD;
623 /// IsLittleEndian - True if this is a little endian target.
627 /// PointerTy - The type to use for pointers, usually i32 or i64.
629 MVT::ValueType PointerTy;
631 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
633 MVT::ValueType ShiftAmountTy;
635 OutOfRangeShiftAmount ShiftAmtHandling;
637 /// SetCCIsExpensive - This is a short term hack for targets that codegen
638 /// setcc as a conditional branch. This encourages the code generator to fold
639 /// setcc operations into other operations if possible.
640 bool SetCCIsExpensive;
642 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
643 /// constants into a sequence of muls, adds, and shifts. This is a hack until
644 /// a real cost model is in place. If we ever optimize for size, this will be
645 /// set to true unconditionally.
648 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
649 /// srl/add/sra for a signed divide by power of two, and let the target handle
653 /// SetCCResultTy - The type that SetCC operations use. This defaults to the
655 MVT::ValueType SetCCResultTy;
657 /// SetCCResultContents - Information about the contents of the high-bits in
658 /// the result of a setcc comparison operation.
659 SetCCResultValue SetCCResultContents;
661 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
662 /// total cycles or lowest register usage.
663 SchedPreference SchedPreferenceInfo;
665 /// UseUnderscoreSetJmpLongJmp - This target prefers to use _setjmp and
666 /// _longjmp to implement llvm.setjmp/llvm.longjmp. Defaults to false.
667 bool UseUnderscoreSetJmpLongJmp;
669 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
670 /// specifies the register that llvm.savestack/llvm.restorestack should save
672 unsigned StackPointerRegisterToSaveRestore;
674 /// RegClassForVT - This indicates the default register class to use for
675 /// each ValueType the target supports natively.
676 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
677 unsigned char NumElementsForVT[MVT::LAST_VALUETYPE];
679 /// TransformToType - For any value types we are promoting or expanding, this
680 /// contains the value type that we are changing to. For Expanded types, this
681 /// contains one step of the expand (e.g. i64 -> i32), even if there are
682 /// multiple steps required (e.g. i64 -> i16). For types natively supported
683 /// by the system, this holds the same type (e.g. i32 -> i32).
684 MVT::ValueType TransformToType[MVT::LAST_VALUETYPE];
686 /// OpActions - For each operation and each value type, keep a LegalizeAction
687 /// that indicates how instruction selection should deal with the operation.
688 /// Most operations are Legal (aka, supported natively by the target), but
689 /// operations that are not should be described. Note that operations on
690 /// non-legal value types are not described here.
691 uint64_t OpActions[156];
693 ValueTypeActionImpl ValueTypeActions;
695 std::vector<double> LegalFPImmediates;
697 std::vector<std::pair<MVT::ValueType,
698 TargetRegisterClass*> > AvailableRegClasses;
700 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
701 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
702 /// which sets a bit in this array.
703 unsigned char TargetDAGCombineArray[156/(sizeof(unsigned char)*8)];
706 /// When lowering %llvm.memset this field specifies the maximum number of
707 /// store operations that may be substituted for the call to memset. Targets
708 /// must set this value based on the cost threshold for that target. Targets
709 /// should assume that the memset will be done using as many of the largest
710 /// store operations first, followed by smaller ones, if necessary, per
711 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
712 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
713 /// store. This only applies to setting a constant array of a constant size.
714 /// @brief Specify maximum number of store instructions per memset call.
715 unsigned maxStoresPerMemset;
717 /// When lowering %llvm.memcpy this field specifies the maximum number of
718 /// store operations that may be substituted for a call to memcpy. Targets
719 /// must set this value based on the cost threshold for that target. Targets
720 /// should assume that the memcpy will be done using as many of the largest
721 /// store operations first, followed by smaller ones, if necessary, per
722 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
723 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
724 /// and one 1-byte store. This only applies to copying a constant array of
726 /// @brief Specify maximum bytes of store instructions per memcpy call.
727 unsigned maxStoresPerMemcpy;
729 /// When lowering %llvm.memmove this field specifies the maximum number of
730 /// store instructions that may be substituted for a call to memmove. Targets
731 /// must set this value based on the cost threshold for that target. Targets
732 /// should assume that the memmove will be done using as many of the largest
733 /// store operations first, followed by smaller ones, if necessary, per
734 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
735 /// with 8-bit alignment would result in nine 1-byte stores. This only
736 /// applies to copying a constant array of constant size.
737 /// @brief Specify maximum bytes of store instructions per memmove call.
738 unsigned maxStoresPerMemmove;
740 /// This field specifies whether the target machine permits unaligned memory
741 /// accesses. This is used, for example, to determine the size of store
742 /// operations when copying small arrays and other similar tasks.
743 /// @brief Indicate whether the target permits unaligned memory accesses.
744 bool allowUnalignedMemoryAccesses;
746 } // end llvm namespace