1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/CodeGen/SelectionDAGNodes.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/ADT/APFloat.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/STLExtras.h"
34 #include "llvm/Support/DebugLoc.h"
35 #include "llvm/Target/TargetMachine.h"
45 class MachineBasicBlock;
46 class MachineFunction;
47 class MachineFrameInfo;
49 class MachineJumpTableInfo;
57 class TargetRegisterClass;
58 class TargetLoweringObjectFile;
61 // FIXME: should this be here?
70 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
73 //===----------------------------------------------------------------------===//
74 /// TargetLowering - This class defines information used to lower LLVM code to
75 /// legal SelectionDAG operators that the target instruction selector can accept
78 /// This class also defines callbacks that targets must implement to lower
79 /// target-specific constructs to SelectionDAG operators.
81 class TargetLowering {
82 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
83 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
85 /// LegalizeAction - This enum indicates whether operations are valid for a
86 /// target, and if not, what action should be used to make them valid.
88 Legal, // The target natively supports this operation.
89 Promote, // This operation should be executed in a larger type.
90 Expand, // Try to expand this to other ops, otherwise use a libcall.
91 Custom // Use the LowerOperation hook to implement custom lowering.
94 enum BooleanContent { // How the target represents true/false values.
95 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
96 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
97 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
100 /// NOTE: The constructor takes ownership of TLOF.
101 explicit TargetLowering(const TargetMachine &TM,
102 const TargetLoweringObjectFile *TLOF);
103 virtual ~TargetLowering();
105 const TargetMachine &getTargetMachine() const { return TM; }
106 const TargetData *getTargetData() const { return TD; }
107 const TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
109 bool isBigEndian() const { return !IsLittleEndian; }
110 bool isLittleEndian() const { return IsLittleEndian; }
111 MVT getPointerTy() const { return PointerTy; }
112 MVT getShiftAmountTy() const { return ShiftAmountTy; }
114 /// isSelectExpensive - Return true if the select operation is expensive for
116 bool isSelectExpensive() const { return SelectIsExpensive; }
118 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
119 /// a sequence of several shifts, adds, and multiplies for this target.
120 bool isIntDivCheap() const { return IntDivIsCheap; }
122 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
124 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
126 /// getSetCCResultType - Return the ValueType of the result of SETCC
127 /// operations. Also used to obtain the target's preferred type for
128 /// the condition operand of SELECT and BRCOND nodes. In the case of
129 /// BRCOND the argument passed is MVT::Other since there are no other
130 /// operands to get a type hint from.
132 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
134 /// getCmpLibcallReturnType - Return the ValueType for comparison
135 /// libcalls. Comparions libcalls include floating point comparion calls,
136 /// and Ordered/Unordered check calls on floating point numbers.
138 MVT::SimpleValueType getCmpLibcallReturnType() const;
140 /// getBooleanContents - For targets without i1 registers, this gives the
141 /// nature of the high-bits of boolean values held in types wider than i1.
142 /// "Boolean values" are special true/false values produced by nodes like
143 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
144 /// Not to be confused with general values promoted from i1.
145 BooleanContent getBooleanContents() const { return BooleanContents;}
147 /// getSchedulingPreference - Return target scheduling preference.
148 Sched::Preference getSchedulingPreference() const {
149 return SchedPreferenceInfo;
152 /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to
153 /// different scheduling heuristics for different nodes. This function returns
154 /// the preference (or none) for the given node.
155 virtual Sched::Preference getSchedulingPreference(SDNode *N) const {
159 /// getRegClassFor - Return the register class that should be used for the
160 /// specified value type.
161 virtual TargetRegisterClass *getRegClassFor(EVT VT) const {
162 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
163 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
164 assert(RC && "This value type is not natively supported!");
168 /// isTypeLegal - Return true if the target has native support for the
169 /// specified value type. This means that it has a register that directly
170 /// holds it without promotions or expansions.
171 bool isTypeLegal(EVT VT) const {
172 assert(!VT.isSimple() ||
173 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
174 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
177 /// isTypeSynthesizable - Return true if it's OK for the compiler to create
178 /// new operations of this type. All Legal types are synthesizable except
179 /// MMX vector types on X86. Non-Legal types are not synthesizable.
180 bool isTypeSynthesizable(EVT VT) const {
181 return isTypeLegal(VT) && Synthesizable[VT.getSimpleVT().SimpleTy];
184 class ValueTypeActionImpl {
185 /// ValueTypeActions - For each value type, keep a LegalizeAction enum
186 /// that indicates how instruction selection should deal with the type.
187 uint8_t ValueTypeActions[MVT::LAST_VALUETYPE];
189 ValueTypeActionImpl() {
190 std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0);
192 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
193 if (VT.isExtended()) {
195 return VT.isPow2VectorType() ? Expand : Promote;
198 // First promote to a power-of-two size, then expand if necessary.
199 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote;
200 assert(0 && "Unsupported extended type!");
203 unsigned I = VT.getSimpleVT().SimpleTy;
204 return (LegalizeAction)ValueTypeActions[I];
206 void setTypeAction(EVT VT, LegalizeAction Action) {
207 unsigned I = VT.getSimpleVT().SimpleTy;
208 ValueTypeActions[I] = Action;
212 const ValueTypeActionImpl &getValueTypeActions() const {
213 return ValueTypeActions;
216 /// getTypeAction - Return how we should legalize values of this type, either
217 /// it is already legal (return 'Legal') or we need to promote it to a larger
218 /// type (return 'Promote'), or we need to expand it into multiple registers
219 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
220 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
221 return ValueTypeActions.getTypeAction(Context, VT);
224 /// getTypeToTransformTo - For types supported by the target, this is an
225 /// identity function. For types that must be promoted to larger types, this
226 /// returns the larger type to promote to. For integer types that are larger
227 /// than the largest integer register, this contains one step in the expansion
228 /// to get to the smaller register. For illegal floating point types, this
229 /// returns the integer type to transform to.
230 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
232 assert((unsigned)VT.getSimpleVT().SimpleTy <
233 array_lengthof(TransformToType));
234 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
235 assert(getTypeAction(Context, NVT) != Promote &&
236 "Promote may not follow Expand or Promote");
241 EVT NVT = VT.getPow2VectorType(Context);
243 // Vector length is a power of 2 - split to half the size.
244 unsigned NumElts = VT.getVectorNumElements();
245 EVT EltVT = VT.getVectorElementType();
246 return (NumElts == 1) ?
247 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
249 // Promote to a power of two size, avoiding multi-step promotion.
250 return getTypeAction(Context, NVT) == Promote ?
251 getTypeToTransformTo(Context, NVT) : NVT;
252 } else if (VT.isInteger()) {
253 EVT NVT = VT.getRoundIntegerType(Context);
255 // Size is a power of two - expand to half the size.
256 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
258 // Promote to a power of two size, avoiding multi-step promotion.
259 return getTypeAction(Context, NVT) == Promote ?
260 getTypeToTransformTo(Context, NVT) : NVT;
262 assert(0 && "Unsupported extended type!");
263 return MVT(MVT::Other); // Not reached
266 /// getTypeToExpandTo - For types supported by the target, this is an
267 /// identity function. For types that must be expanded (i.e. integer types
268 /// that are larger than the largest integer register or illegal floating
269 /// point types), this returns the largest legal type it will be expanded to.
270 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
271 assert(!VT.isVector());
273 switch (getTypeAction(Context, VT)) {
277 VT = getTypeToTransformTo(Context, VT);
280 assert(false && "Type is not legal nor is it to be expanded!");
287 /// getVectorTypeBreakdown - Vector types are broken down into some number of
288 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
289 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
290 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
292 /// This method returns the number of registers needed, and the VT for each
293 /// register. It also returns the VT and quantity of the intermediate values
294 /// before they are promoted/expanded.
296 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
298 unsigned &NumIntermediates,
299 EVT &RegisterVT) const;
301 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
302 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
303 /// this is the case, it returns true and store the intrinsic
304 /// information into the IntrinsicInfo that was passed to the function.
305 struct IntrinsicInfo {
306 unsigned opc; // target opcode
307 EVT memVT; // memory VT
308 const Value* ptrVal; // value representing memory location
309 int offset; // offset off of ptrVal
310 unsigned align; // alignment
311 bool vol; // is volatile?
312 bool readMem; // reads memory?
313 bool writeMem; // writes memory?
316 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
317 const CallInst &I, unsigned Intrinsic) const {
321 /// isFPImmLegal - Returns true if the target can instruction select the
322 /// specified FP immediate natively. If false, the legalizer will materialize
323 /// the FP immediate as a load from a constant pool.
324 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
328 /// isShuffleMaskLegal - Targets can use this to indicate that they only
329 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
330 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
331 /// are assumed to be legal.
332 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
337 /// canOpTrap - Returns true if the operation can trap for the value type.
338 /// VT must be a legal type. By default, we optimistically assume most
339 /// operations don't trap except for divide and remainder.
340 virtual bool canOpTrap(unsigned Op, EVT VT) const;
342 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
343 /// used by Targets can use this to indicate if there is a suitable
344 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
346 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
351 /// getOperationAction - Return how this operation should be treated: either
352 /// it is legal, needs to be promoted to a larger size, needs to be
353 /// expanded to some other code sequence, or the target has a custom expander
355 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
356 if (VT.isExtended()) return Expand;
357 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
358 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
359 return (LegalizeAction)OpActions[I][Op];
362 /// isOperationLegalOrCustom - Return true if the specified operation is
363 /// legal on this target or can be made legal with custom lowering. This
364 /// is used to help guide high-level lowering decisions.
365 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
366 return (VT == MVT::Other || isTypeLegal(VT)) &&
367 (getOperationAction(Op, VT) == Legal ||
368 getOperationAction(Op, VT) == Custom);
371 /// isOperationLegal - Return true if the specified operation is legal on this
373 bool isOperationLegal(unsigned Op, EVT VT) const {
374 return (VT == MVT::Other || isTypeLegal(VT)) &&
375 getOperationAction(Op, VT) == Legal;
378 /// getLoadExtAction - Return how this load with extension should be treated:
379 /// either it is legal, needs to be promoted to a larger size, needs to be
380 /// expanded to some other code sequence, or the target has a custom expander
382 LegalizeAction getLoadExtAction(unsigned ExtType, EVT VT) const {
383 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
384 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
385 "Table isn't big enough!");
386 return (LegalizeAction)LoadExtActions[VT.getSimpleVT().SimpleTy][ExtType];
389 /// isLoadExtLegal - Return true if the specified load with extension is legal
391 bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
392 return VT.isSimple() &&
393 (getLoadExtAction(ExtType, VT) == Legal ||
394 getLoadExtAction(ExtType, VT) == Custom);
397 /// getTruncStoreAction - Return how this store with truncation should be
398 /// treated: either it is legal, needs to be promoted to a larger size, needs
399 /// to be expanded to some other code sequence, or the target has a custom
401 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
402 assert((unsigned)ValVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
403 (unsigned)MemVT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
404 "Table isn't big enough!");
405 return (LegalizeAction)TruncStoreActions[ValVT.getSimpleVT().SimpleTy]
406 [MemVT.getSimpleVT().SimpleTy];
409 /// isTruncStoreLegal - Return true if the specified store with truncation is
410 /// legal on this target.
411 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
412 return isTypeLegal(ValVT) && MemVT.isSimple() &&
413 (getTruncStoreAction(ValVT, MemVT) == Legal ||
414 getTruncStoreAction(ValVT, MemVT) == Custom);
417 /// getIndexedLoadAction - Return how the indexed load should be treated:
418 /// either it is legal, needs to be promoted to a larger size, needs to be
419 /// expanded to some other code sequence, or the target has a custom expander
422 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
423 assert( IdxMode < ISD::LAST_INDEXED_MODE &&
424 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
425 "Table isn't big enough!");
426 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
427 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
430 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
432 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
433 return VT.isSimple() &&
434 (getIndexedLoadAction(IdxMode, VT) == Legal ||
435 getIndexedLoadAction(IdxMode, VT) == Custom);
438 /// getIndexedStoreAction - Return how the indexed store should be treated:
439 /// either it is legal, needs to be promoted to a larger size, needs to be
440 /// expanded to some other code sequence, or the target has a custom expander
443 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
444 assert( IdxMode < ISD::LAST_INDEXED_MODE &&
445 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
446 "Table isn't big enough!");
447 unsigned Ty = (unsigned)VT.getSimpleVT().SimpleTy;
448 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
451 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
453 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
454 return VT.isSimple() &&
455 (getIndexedStoreAction(IdxMode, VT) == Legal ||
456 getIndexedStoreAction(IdxMode, VT) == Custom);
459 /// getCondCodeAction - Return how the condition code should be treated:
460 /// either it is legal, needs to be expanded to some other code sequence,
461 /// or the target has a custom expander for it.
463 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
464 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
465 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
466 "Table isn't big enough!");
467 LegalizeAction Action = (LegalizeAction)
468 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
469 assert(Action != Promote && "Can't promote condition code!");
473 /// isCondCodeLegal - Return true if the specified condition code is legal
475 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
476 return getCondCodeAction(CC, VT) == Legal ||
477 getCondCodeAction(CC, VT) == Custom;
481 /// getTypeToPromoteTo - If the action for this operation is to promote, this
482 /// method returns the ValueType to promote to.
483 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
484 assert(getOperationAction(Op, VT) == Promote &&
485 "This operation isn't promoted!");
487 // See if this has an explicit type specified.
488 std::map<std::pair<unsigned, MVT::SimpleValueType>,
489 MVT::SimpleValueType>::const_iterator PTTI =
490 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
491 if (PTTI != PromoteToType.end()) return PTTI->second;
493 assert((VT.isInteger() || VT.isFloatingPoint()) &&
494 "Cannot autopromote this type, add it with AddPromotedToType.");
498 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
499 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
500 "Didn't find type to promote to!");
501 } while (!isTypeLegal(NVT) ||
502 getOperationAction(Op, NVT) == Promote);
506 /// getValueType - Return the EVT corresponding to this LLVM type.
507 /// This is fixed by the LLVM operations except for the pointer size. If
508 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
509 /// counterpart (e.g. structs), otherwise it will assert.
510 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
511 EVT VT = EVT::getEVT(Ty, AllowUnknown);
512 return VT == MVT::iPTR ? PointerTy : VT;
515 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
516 /// function arguments in the caller parameter area. This is the actual
517 /// alignment, not its logarithm.
518 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
520 /// getRegisterType - Return the type of registers that this ValueType will
521 /// eventually require.
522 EVT getRegisterType(MVT VT) const {
523 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
524 return RegisterTypeForVT[VT.SimpleTy];
527 /// getRegisterType - Return the type of registers that this ValueType will
528 /// eventually require.
529 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
531 assert((unsigned)VT.getSimpleVT().SimpleTy <
532 array_lengthof(RegisterTypeForVT));
533 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
537 unsigned NumIntermediates;
538 (void)getVectorTypeBreakdown(Context, VT, VT1,
539 NumIntermediates, RegisterVT);
542 if (VT.isInteger()) {
543 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
545 assert(0 && "Unsupported extended type!");
546 return EVT(MVT::Other); // Not reached
549 /// getNumRegisters - Return the number of registers that this ValueType will
550 /// eventually require. This is one for any types promoted to live in larger
551 /// registers, but may be more than one for types (like i64) that are split
552 /// into pieces. For types like i140, which are first promoted then expanded,
553 /// it is the number of registers needed to hold all the bits of the original
554 /// type. For an i140 on a 32 bit machine this means 5 registers.
555 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
557 assert((unsigned)VT.getSimpleVT().SimpleTy <
558 array_lengthof(NumRegistersForVT));
559 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
563 unsigned NumIntermediates;
564 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
566 if (VT.isInteger()) {
567 unsigned BitWidth = VT.getSizeInBits();
568 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
569 return (BitWidth + RegWidth - 1) / RegWidth;
571 assert(0 && "Unsupported extended type!");
572 return 0; // Not reached
575 /// ShouldShrinkFPConstant - If true, then instruction selection should
576 /// seek to shrink the FP constant of the specified type to a smaller type
577 /// in order to save space and / or reduce runtime.
578 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
580 /// hasTargetDAGCombine - If true, the target has custom DAG combine
581 /// transformations that it can perform for the specified node.
582 bool hasTargetDAGCombine(ISD::NodeType NT) const {
583 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
584 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
587 /// This function returns the maximum number of store operations permitted
588 /// to replace a call to llvm.memset. The value is set by the target at the
589 /// performance threshold for such a replacement.
590 /// @brief Get maximum # of store operations permitted for llvm.memset
591 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
593 /// This function returns the maximum number of store operations permitted
594 /// to replace a call to llvm.memcpy. The value is set by the target at the
595 /// performance threshold for such a replacement.
596 /// @brief Get maximum # of store operations permitted for llvm.memcpy
597 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
599 /// This function returns the maximum number of store operations permitted
600 /// to replace a call to llvm.memmove. The value is set by the target at the
601 /// performance threshold for such a replacement.
602 /// @brief Get maximum # of store operations permitted for llvm.memmove
603 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
605 /// This function returns true if the target allows unaligned memory accesses.
606 /// of the specified type. This is used, for example, in situations where an
607 /// array copy/move/set is converted to a sequence of store operations. It's
608 /// use helps to ensure that such replacements don't generate code that causes
609 /// an alignment error (trap) on the target machine.
610 /// @brief Determine if the target supports unaligned memory accesses.
611 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
615 /// This function returns true if the target would benefit from code placement
617 /// @brief Determine if the target should perform code placement optimization.
618 bool shouldOptimizeCodePlacement() const {
619 return benefitFromCodePlacementOpt;
622 /// getOptimalMemOpType - Returns the target specific optimal type for load
623 /// and store operations as a result of memset, memcpy, and memmove
624 /// lowering. If DstAlign is zero that means it's safe to destination
625 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
626 /// means there isn't a need to check it against alignment requirement,
627 /// probably because the source does not need to be loaded. If
628 /// 'NonScalarIntSafe' is true, that means it's safe to return a
629 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
630 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
631 /// constant so it does not need to be loaded.
632 /// It returns EVT::Other if the type should be determined using generic
633 /// target-independent logic.
634 virtual EVT getOptimalMemOpType(uint64_t Size,
635 unsigned DstAlign, unsigned SrcAlign,
636 bool NonScalarIntSafe, bool MemcpyStrSrc,
637 MachineFunction &MF) const {
641 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
642 /// to implement llvm.setjmp.
643 bool usesUnderscoreSetJmp() const {
644 return UseUnderscoreSetJmp;
647 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
648 /// to implement llvm.longjmp.
649 bool usesUnderscoreLongJmp() const {
650 return UseUnderscoreLongJmp;
653 /// getStackPointerRegisterToSaveRestore - If a physical register, this
654 /// specifies the register that llvm.savestack/llvm.restorestack should save
656 unsigned getStackPointerRegisterToSaveRestore() const {
657 return StackPointerRegisterToSaveRestore;
660 /// getExceptionAddressRegister - If a physical register, this returns
661 /// the register that receives the exception address on entry to a landing
663 unsigned getExceptionAddressRegister() const {
664 return ExceptionPointerRegister;
667 /// getExceptionSelectorRegister - If a physical register, this returns
668 /// the register that receives the exception typeid on entry to a landing
670 unsigned getExceptionSelectorRegister() const {
671 return ExceptionSelectorRegister;
674 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
675 /// set, the default is 200)
676 unsigned getJumpBufSize() const {
680 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
681 /// (if never set, the default is 0)
682 unsigned getJumpBufAlignment() const {
683 return JumpBufAlignment;
686 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
687 /// limit. Any block whose size is greater should not be predicated.
688 unsigned getIfCvtBlockSizeLimit() const {
689 return IfCvtBlockSizeLimit;
692 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
693 /// block to be considered for duplication. Any block whose size is greater
694 /// should not be duplicated to facilitate its predication.
695 unsigned getIfCvtDupBlockSizeLimit() const {
696 return IfCvtDupBlockSizeLimit;
699 /// getPrefLoopAlignment - return the preferred loop alignment.
701 unsigned getPrefLoopAlignment() const {
702 return PrefLoopAlignment;
705 /// getShouldFoldAtomicFences - return whether the combiner should fold
706 /// fence MEMBARRIER instructions into the atomic intrinsic instructions.
708 bool getShouldFoldAtomicFences() const {
709 return ShouldFoldAtomicFences;
712 /// getPreIndexedAddressParts - returns true by value, base pointer and
713 /// offset pointer and addressing mode by reference if the node's address
714 /// can be legally represented as pre-indexed load / store address.
715 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
717 ISD::MemIndexedMode &AM,
718 SelectionDAG &DAG) const {
722 /// getPostIndexedAddressParts - returns true by value, base pointer and
723 /// offset pointer and addressing mode by reference if this node can be
724 /// combined with a load / store to form a post-indexed load / store.
725 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
726 SDValue &Base, SDValue &Offset,
727 ISD::MemIndexedMode &AM,
728 SelectionDAG &DAG) const {
732 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
733 /// current function. The returned value is a member of the
734 /// MachineJumpTableInfo::JTEntryKind enum.
735 virtual unsigned getJumpTableEncoding() const;
737 virtual const MCExpr *
738 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
739 const MachineBasicBlock *MBB, unsigned uid,
740 MCContext &Ctx) const {
741 assert(0 && "Need to implement this hook if target has custom JTIs");
745 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
747 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
748 SelectionDAG &DAG) const;
750 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
751 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
753 virtual const MCExpr *
754 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
755 unsigned JTI, MCContext &Ctx) const;
757 /// isOffsetFoldingLegal - Return true if folding a constant offset
758 /// with the given GlobalAddress is legal. It is frequently not legal in
759 /// PIC relocation models.
760 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
762 /// getFunctionAlignment - Return the Log2 alignment of this function.
763 virtual unsigned getFunctionAlignment(const Function *) const = 0;
765 //===--------------------------------------------------------------------===//
766 // TargetLowering Optimization Methods
769 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
770 /// SDValues for returning information from TargetLowering to its clients
771 /// that want to combine
772 struct TargetLoweringOpt {
780 explicit TargetLoweringOpt(SelectionDAG &InDAG,
782 bool Shrink = false) :
783 DAG(InDAG), LegalTys(LT), LegalOps(LO), ShrinkOps(Shrink) {}
785 bool LegalTypes() const { return LegalTys; }
786 bool LegalOperations() const { return LegalOps; }
788 bool CombineTo(SDValue O, SDValue N) {
794 /// ShrinkDemandedConstant - Check to see if the specified operand of the
795 /// specified instruction is a constant integer. If so, check to see if
796 /// there are any bits set in the constant that are not demanded. If so,
797 /// shrink the constant and return true.
798 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
800 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
801 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
802 /// cast, but it could be generalized for targets with other types of
803 /// implicit widening casts.
804 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
808 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
809 /// DemandedMask bits of the result of Op are ever used downstream. If we can
810 /// use this information to simplify Op, create a new simplified DAG node and
811 /// return true, returning the original and new nodes in Old and New.
812 /// Otherwise, analyze the expression and return a mask of KnownOne and
813 /// KnownZero bits for the expression (used to simplify the caller).
814 /// The KnownZero/One bits may only be accurate for those bits in the
816 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
817 APInt &KnownZero, APInt &KnownOne,
818 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
820 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
821 /// Mask are known to be either zero or one and return them in the
822 /// KnownZero/KnownOne bitsets.
823 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
827 const SelectionDAG &DAG,
828 unsigned Depth = 0) const;
830 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
831 /// targets that want to expose additional information about sign bits to the
833 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
834 unsigned Depth = 0) const;
836 struct DAGCombinerInfo {
837 void *DC; // The DAG Combiner object.
839 bool BeforeLegalizeOps;
840 bool CalledByLegalizer;
844 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
845 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
846 CalledByLegalizer(cl), DAG(dag) {}
848 bool isBeforeLegalize() const { return BeforeLegalize; }
849 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
850 bool isCalledByLegalizer() const { return CalledByLegalizer; }
852 void AddToWorklist(SDNode *N);
853 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
855 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
856 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
858 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
861 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
862 /// and cc. If it is unable to simplify it, return a null SDValue.
863 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
864 ISD::CondCode Cond, bool foldBooleans,
865 DAGCombinerInfo &DCI, DebugLoc dl) const;
867 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
868 /// node is a GlobalAddress + offset.
870 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
872 /// PerformDAGCombine - This method will be invoked for all target nodes and
873 /// for any target-independent nodes that the target has registered with
876 /// The semantics are as follows:
878 /// SDValue.Val == 0 - No change was made
879 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
880 /// otherwise - N should be replaced by the returned Operand.
882 /// In addition, methods provided by DAGCombinerInfo may be used to perform
883 /// more complex transformations.
885 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
887 /// isTypeDesirableForOp - Return true if the target has native support for
888 /// the specified value type and it is 'desirable' to use the type for the
889 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
890 /// instruction encodings are longer and some i16 instructions are slow.
891 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const {
892 // By default, assume all legal types are desirable.
893 return isTypeLegal(VT);
896 /// IsDesirableToPromoteOp - This method query the target whether it is
897 /// beneficial for dag combiner to promote the specified node. If true, it
898 /// should return the desired promotion type by reference.
899 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
903 //===--------------------------------------------------------------------===//
904 // TargetLowering Configuration Methods - These methods should be invoked by
905 // the derived class constructor to configure this object for the target.
909 /// setShiftAmountType - Describe the type that should be used for shift
910 /// amounts. This type defaults to the pointer type.
911 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
913 /// setBooleanContents - Specify how the target extends the result of a
914 /// boolean value from i1 to a wider type. See getBooleanContents.
915 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
917 /// setSchedulingPreference - Specify the target scheduling preference.
918 void setSchedulingPreference(Sched::Preference Pref) {
919 SchedPreferenceInfo = Pref;
922 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
923 /// use _setjmp to implement llvm.setjmp or the non _ version.
924 /// Defaults to false.
925 void setUseUnderscoreSetJmp(bool Val) {
926 UseUnderscoreSetJmp = Val;
929 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
930 /// use _longjmp to implement llvm.longjmp or the non _ version.
931 /// Defaults to false.
932 void setUseUnderscoreLongJmp(bool Val) {
933 UseUnderscoreLongJmp = Val;
936 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
937 /// specifies the register that llvm.savestack/llvm.restorestack should save
939 void setStackPointerRegisterToSaveRestore(unsigned R) {
940 StackPointerRegisterToSaveRestore = R;
943 /// setExceptionPointerRegister - If set to a physical register, this sets
944 /// the register that receives the exception address on entry to a landing
946 void setExceptionPointerRegister(unsigned R) {
947 ExceptionPointerRegister = R;
950 /// setExceptionSelectorRegister - If set to a physical register, this sets
951 /// the register that receives the exception typeid on entry to a landing
953 void setExceptionSelectorRegister(unsigned R) {
954 ExceptionSelectorRegister = R;
957 /// SelectIsExpensive - Tells the code generator not to expand operations
958 /// into sequences that use the select operations if possible.
959 void setSelectIsExpensive() { SelectIsExpensive = true; }
961 /// setIntDivIsCheap - Tells the code generator that integer divide is
962 /// expensive, and if possible, should be replaced by an alternate sequence
963 /// of instructions not containing an integer divide.
964 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
966 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
967 /// srl/add/sra for a signed divide by power of two, and let the target handle
969 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
971 /// addRegisterClass - Add the specified register class as an available
972 /// regclass for the specified value type. This indicates the selector can
973 /// handle values of that class natively.
974 void addRegisterClass(EVT VT, TargetRegisterClass *RC,
975 bool isSynthesizable = true) {
976 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
977 AvailableRegClasses.push_back(std::make_pair(VT, RC));
978 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
979 Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable;
982 /// computeRegisterProperties - Once all of the register classes are added,
983 /// this allows us to compute derived properties we expose.
984 void computeRegisterProperties();
986 /// setOperationAction - Indicate that the specified operation does not work
987 /// with the specified type and indicate what to do about it.
988 void setOperationAction(unsigned Op, MVT VT,
989 LegalizeAction Action) {
990 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
991 OpActions[(unsigned)VT.SimpleTy][Op] = (uint8_t)Action;
994 /// setLoadExtAction - Indicate that the specified load with extension does
995 /// not work with the specified type and indicate what to do about it.
996 void setLoadExtAction(unsigned ExtType, MVT VT,
997 LegalizeAction Action) {
998 assert(ExtType < ISD::LAST_LOADEXT_TYPE &&
999 (unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1000 "Table isn't big enough!");
1001 LoadExtActions[VT.SimpleTy][ExtType] = (uint8_t)Action;
1004 /// setTruncStoreAction - Indicate that the specified truncating store does
1005 /// not work with the specified type and indicate what to do about it.
1006 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1007 LegalizeAction Action) {
1008 assert((unsigned)ValVT.SimpleTy < MVT::LAST_VALUETYPE &&
1009 (unsigned)MemVT.SimpleTy < MVT::LAST_VALUETYPE &&
1010 "Table isn't big enough!");
1011 TruncStoreActions[ValVT.SimpleTy][MemVT.SimpleTy] = (uint8_t)Action;
1014 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1015 /// does not work with the specified type and indicate what to do abort
1016 /// it. NOTE: All indexed mode loads are initialized to Expand in
1017 /// TargetLowering.cpp
1018 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1019 LegalizeAction Action) {
1020 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1021 IdxMode < ISD::LAST_INDEXED_MODE &&
1022 (unsigned)Action < 0xf &&
1023 "Table isn't big enough!");
1024 // Load action are kept in the upper half.
1025 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1026 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1029 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1030 /// does not work with the specified type and indicate what to do about
1031 /// it. NOTE: All indexed mode stores are initialized to Expand in
1032 /// TargetLowering.cpp
1033 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1034 LegalizeAction Action) {
1035 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1036 IdxMode < ISD::LAST_INDEXED_MODE &&
1037 (unsigned)Action < 0xf &&
1038 "Table isn't big enough!");
1039 // Store action are kept in the lower half.
1040 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1041 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1044 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1045 /// supported on the target and indicate what to do about it.
1046 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1047 LegalizeAction Action) {
1048 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1049 (unsigned)CC < array_lengthof(CondCodeActions) &&
1050 "Table isn't big enough!");
1051 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1052 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1055 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1056 /// promotion code defaults to trying a larger integer/fp until it can find
1057 /// one that works. If that default is insufficient, this method can be used
1058 /// by the target to override the default.
1059 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1060 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1063 /// setTargetDAGCombine - Targets should invoke this method for each target
1064 /// independent node that they want to provide a custom DAG combiner for by
1065 /// implementing the PerformDAGCombine virtual method.
1066 void setTargetDAGCombine(ISD::NodeType NT) {
1067 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1068 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1071 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1072 /// bytes); default is 200
1073 void setJumpBufSize(unsigned Size) {
1077 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1078 /// alignment (in bytes); default is 0
1079 void setJumpBufAlignment(unsigned Align) {
1080 JumpBufAlignment = Align;
1083 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1084 /// limit (in number of instructions); default is 2.
1085 void setIfCvtBlockSizeLimit(unsigned Limit) {
1086 IfCvtBlockSizeLimit = Limit;
1089 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1090 /// of instructions) to be considered for code duplication during
1091 /// if-conversion; default is 2.
1092 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1093 IfCvtDupBlockSizeLimit = Limit;
1096 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1097 /// alignment is zero, it means the target does not care about loop alignment.
1098 void setPrefLoopAlignment(unsigned Align) {
1099 PrefLoopAlignment = Align;
1102 /// setShouldFoldAtomicFences - Set if the target's implementation of the
1103 /// atomic operation intrinsics includes locking. Default is false.
1104 void setShouldFoldAtomicFences(bool fold) {
1105 ShouldFoldAtomicFences = fold;
1109 //===--------------------------------------------------------------------===//
1110 // Lowering methods - These methods must be implemented by targets so that
1111 // the SelectionDAGLowering code knows how to lower these.
1114 /// LowerFormalArguments - This hook must be implemented to lower the
1115 /// incoming (formal) arguments, described by the Ins array, into the
1116 /// specified DAG. The implementation should fill in the InVals array
1117 /// with legal-type argument values, and return the resulting token
1121 LowerFormalArguments(SDValue Chain,
1122 CallingConv::ID CallConv, bool isVarArg,
1123 const SmallVectorImpl<ISD::InputArg> &Ins,
1124 DebugLoc dl, SelectionDAG &DAG,
1125 SmallVectorImpl<SDValue> &InVals) const {
1126 assert(0 && "Not Implemented");
1127 return SDValue(); // this is here to silence compiler errors
1130 /// LowerCallTo - This function lowers an abstract call to a function into an
1131 /// actual call. This returns a pair of operands. The first element is the
1132 /// return value for the function (if RetTy is not VoidTy). The second
1133 /// element is the outgoing token chain. It calls LowerCall to do the actual
1135 struct ArgListEntry {
1146 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1147 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1149 typedef std::vector<ArgListEntry> ArgListTy;
1150 std::pair<SDValue, SDValue>
1151 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1152 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1153 CallingConv::ID CallConv, bool isTailCall,
1154 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
1155 SelectionDAG &DAG, DebugLoc dl) const;
1157 /// LowerCall - This hook must be implemented to lower calls into the
1158 /// the specified DAG. The outgoing arguments to the call are described
1159 /// by the Outs array, and the values to be returned by the call are
1160 /// described by the Ins array. The implementation should fill in the
1161 /// InVals array with legal-type return values from the call, and return
1162 /// the resulting token chain value.
1164 LowerCall(SDValue Chain, SDValue Callee,
1165 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
1166 const SmallVectorImpl<ISD::OutputArg> &Outs,
1167 const SmallVectorImpl<ISD::InputArg> &Ins,
1168 DebugLoc dl, SelectionDAG &DAG,
1169 SmallVectorImpl<SDValue> &InVals) const {
1170 assert(0 && "Not Implemented");
1171 return SDValue(); // this is here to silence compiler errors
1174 /// CanLowerReturn - This hook should be implemented to check whether the
1175 /// return values described by the Outs array can fit into the return
1176 /// registers. If false is returned, an sret-demotion is performed.
1178 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1179 const SmallVectorImpl<EVT> &OutTys,
1180 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1181 SelectionDAG &DAG) const
1183 // Return true by default to get preexisting behavior.
1187 /// LowerReturn - This hook must be implemented to lower outgoing
1188 /// return values, described by the Outs array, into the specified
1189 /// DAG. The implementation should return the resulting token chain
1193 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1194 const SmallVectorImpl<ISD::OutputArg> &Outs,
1195 DebugLoc dl, SelectionDAG &DAG) const {
1196 assert(0 && "Not Implemented");
1197 return SDValue(); // this is here to silence compiler errors
1200 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1201 /// to legalize nodes with an illegal operand type but legal result types.
1202 /// It replaces the LowerOperation callback in the type Legalizer.
1203 /// The reason we can not do away with LowerOperation entirely is that
1204 /// LegalizeDAG isn't yet ready to use this callback.
1205 /// TODO: Consider merging with ReplaceNodeResults.
1207 /// The target places new result values for the node in Results (their number
1208 /// and types must exactly match those of the original return values of
1209 /// the node), or leaves Results empty, which indicates that the node is not
1210 /// to be custom lowered after all.
1211 /// The default implementation calls LowerOperation.
1212 virtual void LowerOperationWrapper(SDNode *N,
1213 SmallVectorImpl<SDValue> &Results,
1214 SelectionDAG &DAG) const;
1216 /// LowerOperation - This callback is invoked for operations that are
1217 /// unsupported by the target, which are registered to use 'custom' lowering,
1218 /// and whose defined values are all legal.
1219 /// If the target has no operations that require custom lowering, it need not
1220 /// implement this. The default implementation of this aborts.
1221 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
1223 /// ReplaceNodeResults - This callback is invoked when a node result type is
1224 /// illegal for the target, and the operation was registered to use 'custom'
1225 /// lowering for that result type. The target places new result values for
1226 /// the node in Results (their number and types must exactly match those of
1227 /// the original return values of the node), or leaves Results empty, which
1228 /// indicates that the node is not to be custom lowered after all.
1230 /// If the target has no operations that require custom lowering, it need not
1231 /// implement this. The default implementation aborts.
1232 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1233 SelectionDAG &DAG) const {
1234 assert(0 && "ReplaceNodeResults not implemented for this target!");
1237 /// getTargetNodeName() - This method returns the name of a target specific
1239 virtual const char *getTargetNodeName(unsigned Opcode) const;
1241 /// createFastISel - This method returns a target specific FastISel object,
1242 /// or null if the target does not support "fast" ISel.
1244 createFastISel(MachineFunction &,
1245 DenseMap<const Value *, unsigned> &,
1246 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1247 DenseMap<const AllocaInst *, int> &,
1248 std::vector<std::pair<MachineInstr*, unsigned> > &
1250 , SmallSet<const Instruction *, 8> &CatchInfoLost
1256 //===--------------------------------------------------------------------===//
1257 // Inline Asm Support hooks
1260 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1261 /// call to be explicit llvm code if it wants to. This is useful for
1262 /// turning simple inline asms into LLVM intrinsics, which gives the
1263 /// compiler more information about the behavior of the code.
1264 virtual bool ExpandInlineAsm(CallInst *CI) const {
1268 enum ConstraintType {
1269 C_Register, // Constraint represents specific register(s).
1270 C_RegisterClass, // Constraint represents any of register(s) in class.
1271 C_Memory, // Memory constraint.
1272 C_Other, // Something else.
1273 C_Unknown // Unsupported constraint.
1276 /// AsmOperandInfo - This contains information for each constraint that we are
1278 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1279 /// ConstraintCode - This contains the actual string for the code, like "m".
1280 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1281 /// most closely matches the operand.
1282 std::string ConstraintCode;
1284 /// ConstraintType - Information about the constraint code, e.g. Register,
1285 /// RegisterClass, Memory, Other, Unknown.
1286 TargetLowering::ConstraintType ConstraintType;
1288 /// CallOperandval - If this is the result output operand or a
1289 /// clobber, this is null, otherwise it is the incoming operand to the
1290 /// CallInst. This gets modified as the asm is processed.
1291 Value *CallOperandVal;
1293 /// ConstraintVT - The ValueType for the operand value.
1296 /// isMatchingInputConstraint - Return true of this is an input operand that
1297 /// is a matching constraint like "4".
1298 bool isMatchingInputConstraint() const;
1300 /// getMatchedOperand - If this is an input matching constraint, this method
1301 /// returns the output operand it matches.
1302 unsigned getMatchedOperand() const;
1304 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1305 : InlineAsm::ConstraintInfo(info),
1306 ConstraintType(TargetLowering::C_Unknown),
1307 CallOperandVal(0), ConstraintVT(MVT::Other) {
1311 /// ComputeConstraintToUse - Determines the constraint code and constraint
1312 /// type to use for the specific AsmOperandInfo, setting
1313 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1314 /// being passed in is available, it can be passed in as Op, otherwise an
1315 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1316 /// constraint of the inline asm instruction being processed is 'm'.
1317 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1320 SelectionDAG *DAG = 0) const;
1322 /// getConstraintType - Given a constraint, return the type of constraint it
1323 /// is for this target.
1324 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1326 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1327 /// return a list of registers that can be used to satisfy the constraint.
1328 /// This should only be used for C_RegisterClass constraints.
1329 virtual std::vector<unsigned>
1330 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1333 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1334 /// {edx}), return the register number and the register class for the
1337 /// Given a register class constraint, like 'r', if this corresponds directly
1338 /// to an LLVM register class, return a register of 0 and the register class
1341 /// This should only be used for C_Register constraints. On error,
1342 /// this returns a register number of 0 and a null register class pointer..
1343 virtual std::pair<unsigned, const TargetRegisterClass*>
1344 getRegForInlineAsmConstraint(const std::string &Constraint,
1347 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1348 /// with another that has more specific requirements based on the type of the
1349 /// corresponding operand. This returns null if there is no replacement to
1351 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1353 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1354 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1355 /// it means one of the asm constraint of the inline asm instruction being
1356 /// processed is 'm'.
1357 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1359 std::vector<SDValue> &Ops,
1360 SelectionDAG &DAG) const;
1362 //===--------------------------------------------------------------------===//
1363 // Instruction Emitting Hooks
1366 // EmitInstrWithCustomInserter - This method should be implemented by targets
1367 // that mark instructions with the 'usesCustomInserter' flag. These
1368 // instructions are special in various ways, which require special support to
1369 // insert. The specified MachineInstr is created but not inserted into any
1370 // basic blocks, and this method is called to expand it into a sequence of
1371 // instructions, potentially also creating new basic blocks and control flow.
1372 virtual MachineBasicBlock *
1373 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
1375 //===--------------------------------------------------------------------===//
1376 // Addressing mode description hooks (used by LSR etc).
1379 /// AddrMode - This represents an addressing mode of:
1380 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1381 /// If BaseGV is null, there is no BaseGV.
1382 /// If BaseOffs is zero, there is no base offset.
1383 /// If HasBaseReg is false, there is no base register.
1384 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1388 GlobalValue *BaseGV;
1392 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1395 /// isLegalAddressingMode - Return true if the addressing mode represented by
1396 /// AM is legal for this target, for a load/store of the specified type.
1397 /// The type may be VoidTy, in which case only return true if the addressing
1398 /// mode is legal for a load/store of any legal type.
1399 /// TODO: Handle pre/postinc as well.
1400 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1402 /// isTruncateFree - Return true if it's free to truncate a value of
1403 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1404 /// register EAX to i16 by referencing its sub-register AX.
1405 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1409 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1413 /// isZExtFree - Return true if any actual instruction that defines a
1414 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1415 /// register. This does not necessarily include registers defined in
1416 /// unknown ways, such as incoming arguments, or copies from unknown
1417 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1418 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1419 /// all instructions that define 32-bit values implicit zero-extend the
1420 /// result out to 64 bits.
1421 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1425 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1429 /// isNarrowingProfitable - Return true if it's profitable to narrow
1430 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1431 /// from i32 to i8 but not from i32 to i16.
1432 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1436 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1437 /// icmp immediate, that is the target has icmp instructions which can compare
1438 /// a register against the immediate without having to materialize the
1439 /// immediate into a register.
1440 virtual bool isLegalICmpImmediate(int64_t Imm) const {
1444 //===--------------------------------------------------------------------===//
1445 // Div utility functions
1447 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1448 std::vector<SDNode*>* Created) const;
1449 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1450 std::vector<SDNode*>* Created) const;
1453 //===--------------------------------------------------------------------===//
1454 // Runtime Library hooks
1457 /// setLibcallName - Rename the default libcall routine name for the specified
1459 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1460 LibcallRoutineNames[Call] = Name;
1463 /// getLibcallName - Get the libcall routine name for the specified libcall.
1465 const char *getLibcallName(RTLIB::Libcall Call) const {
1466 return LibcallRoutineNames[Call];
1469 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1470 /// result of the comparison libcall against zero.
1471 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1472 CmpLibcallCCs[Call] = CC;
1475 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1476 /// the comparison libcall against zero.
1477 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1478 return CmpLibcallCCs[Call];
1481 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1482 /// specified libcall.
1483 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1484 LibcallCallingConvs[Call] = CC;
1487 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1488 /// specified libcall.
1489 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1490 return LibcallCallingConvs[Call];
1494 const TargetMachine &TM;
1495 const TargetData *TD;
1496 const TargetLoweringObjectFile &TLOF;
1498 /// PointerTy - The type to use for pointers, usually i32 or i64.
1502 /// IsLittleEndian - True if this is a little endian target.
1504 bool IsLittleEndian;
1506 /// SelectIsExpensive - Tells the code generator not to expand operations
1507 /// into sequences that use the select operations if possible.
1508 bool SelectIsExpensive;
1510 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1511 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1512 /// a real cost model is in place. If we ever optimize for size, this will be
1513 /// set to true unconditionally.
1516 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1517 /// srl/add/sra for a signed divide by power of two, and let the target handle
1519 bool Pow2DivIsCheap;
1521 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1522 /// llvm.setjmp. Defaults to false.
1523 bool UseUnderscoreSetJmp;
1525 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1526 /// llvm.longjmp. Defaults to false.
1527 bool UseUnderscoreLongJmp;
1529 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1533 /// BooleanContents - Information about the contents of the high-bits in
1534 /// boolean values held in a type wider than i1. See getBooleanContents.
1535 BooleanContent BooleanContents;
1537 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1538 /// total cycles or lowest register usage.
1539 Sched::Preference SchedPreferenceInfo;
1541 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1542 unsigned JumpBufSize;
1544 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1546 unsigned JumpBufAlignment;
1548 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1550 unsigned IfCvtBlockSizeLimit;
1552 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1553 /// duplicated during if-conversion.
1554 unsigned IfCvtDupBlockSizeLimit;
1556 /// PrefLoopAlignment - The perferred loop alignment.
1558 unsigned PrefLoopAlignment;
1560 /// ShouldFoldAtomicFences - Whether fencing MEMBARRIER instructions should
1561 /// be folded into the enclosed atomic intrinsic instruction by the
1563 bool ShouldFoldAtomicFences;
1565 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1566 /// specifies the register that llvm.savestack/llvm.restorestack should save
1568 unsigned StackPointerRegisterToSaveRestore;
1570 /// ExceptionPointerRegister - If set to a physical register, this specifies
1571 /// the register that receives the exception address on entry to a landing
1573 unsigned ExceptionPointerRegister;
1575 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1576 /// the register that receives the exception typeid on entry to a landing
1578 unsigned ExceptionSelectorRegister;
1580 /// RegClassForVT - This indicates the default register class to use for
1581 /// each ValueType the target supports natively.
1582 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1583 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1584 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1586 /// Synthesizable indicates whether it is OK for the compiler to create new
1587 /// operations using this type. All Legal types are Synthesizable except
1588 /// MMX types on X86. Non-Legal types are not Synthesizable.
1589 bool Synthesizable[MVT::LAST_VALUETYPE];
1591 /// TransformToType - For any value types we are promoting or expanding, this
1592 /// contains the value type that we are changing to. For Expanded types, this
1593 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1594 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1595 /// by the system, this holds the same type (e.g. i32 -> i32).
1596 EVT TransformToType[MVT::LAST_VALUETYPE];
1598 /// OpActions - For each operation and each value type, keep a LegalizeAction
1599 /// that indicates how instruction selection should deal with the operation.
1600 /// Most operations are Legal (aka, supported natively by the target), but
1601 /// operations that are not should be described. Note that operations on
1602 /// non-legal value types are not described here.
1603 uint8_t OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
1605 /// LoadExtActions - For each load extension type and each value type,
1606 /// keep a LegalizeAction that indicates how instruction selection should deal
1607 /// with a load of a specific value type and extension type.
1608 uint8_t LoadExtActions[MVT::LAST_VALUETYPE][ISD::LAST_LOADEXT_TYPE];
1610 /// TruncStoreActions - For each value type pair keep a LegalizeAction that
1611 /// indicates whether a truncating store of a specific value type and
1612 /// truncating type is legal.
1613 uint8_t TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
1615 /// IndexedModeActions - For each indexed mode and each value type,
1616 /// keep a pair of LegalizeAction that indicates how instruction
1617 /// selection should deal with the load / store. The first dimension is the
1618 /// value_type for the reference. The second dimension represents the various
1619 /// modes for load store.
1620 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
1622 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1623 /// LegalizeAction that indicates how instruction selection should
1624 /// deal with the condition code.
1625 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1627 ValueTypeActionImpl ValueTypeActions;
1629 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1631 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1632 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1633 /// which sets a bit in this array.
1635 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1637 /// PromoteToType - For operations that must be promoted to a specific type,
1638 /// this holds the destination type. This map should be sparse, so don't hold
1641 /// Targets add entries to this map with AddPromotedToType(..), clients access
1642 /// this with getTypeToPromoteTo(..).
1643 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1646 /// LibcallRoutineNames - Stores the name each libcall.
1648 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1650 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1651 /// of each of the comparison libcall against zero.
1652 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1654 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1656 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1659 /// When lowering \@llvm.memset this field specifies the maximum number of
1660 /// store operations that may be substituted for the call to memset. Targets
1661 /// must set this value based on the cost threshold for that target. Targets
1662 /// should assume that the memset will be done using as many of the largest
1663 /// store operations first, followed by smaller ones, if necessary, per
1664 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1665 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1666 /// store. This only applies to setting a constant array of a constant size.
1667 /// @brief Specify maximum number of store instructions per memset call.
1668 unsigned maxStoresPerMemset;
1670 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1671 /// store operations that may be substituted for a call to memcpy. Targets
1672 /// must set this value based on the cost threshold for that target. Targets
1673 /// should assume that the memcpy will be done using as many of the largest
1674 /// store operations first, followed by smaller ones, if necessary, per
1675 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1676 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1677 /// and one 1-byte store. This only applies to copying a constant array of
1679 /// @brief Specify maximum bytes of store instructions per memcpy call.
1680 unsigned maxStoresPerMemcpy;
1682 /// When lowering \@llvm.memmove this field specifies the maximum number of
1683 /// store instructions that may be substituted for a call to memmove. Targets
1684 /// must set this value based on the cost threshold for that target. Targets
1685 /// should assume that the memmove will be done using as many of the largest
1686 /// store operations first, followed by smaller ones, if necessary, per
1687 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1688 /// with 8-bit alignment would result in nine 1-byte stores. This only
1689 /// applies to copying a constant array of constant size.
1690 /// @brief Specify maximum bytes of store instructions per memmove call.
1691 unsigned maxStoresPerMemmove;
1693 /// This field specifies whether the target can benefit from code placement
1695 bool benefitFromCodePlacementOpt;
1697 } // end llvm namespace