1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/CodeGen/SelectionDAGNodes.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/ADT/APFloat.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/STLExtras.h"
34 #include "llvm/Support/DebugLoc.h"
35 #include "llvm/Target/TargetMachine.h"
45 class MachineBasicBlock;
46 class MachineFunction;
47 class MachineFrameInfo;
49 class MachineJumpTableInfo;
50 class MachineModuleInfo;
59 class TargetRegisterClass;
60 class TargetSubtarget;
61 class TargetLoweringObjectFile;
64 // FIXME: should this be here?
73 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
76 //===----------------------------------------------------------------------===//
77 /// TargetLowering - This class defines information used to lower LLVM code to
78 /// legal SelectionDAG operators that the target instruction selector can accept
81 /// This class also defines callbacks that targets must implement to lower
82 /// target-specific constructs to SelectionDAG operators.
84 class TargetLowering {
85 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
86 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
88 /// LegalizeAction - This enum indicates whether operations are valid for a
89 /// target, and if not, what action should be used to make them valid.
91 Legal, // The target natively supports this operation.
92 Promote, // This operation should be executed in a larger type.
93 Expand, // Try to expand this to other ops, otherwise use a libcall.
94 Custom // Use the LowerOperation hook to implement custom lowering.
97 enum BooleanContent { // How the target represents true/false values.
98 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
99 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
100 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
103 enum SchedPreference {
104 SchedulingForLatency, // Scheduling for shortest total latency.
105 SchedulingForRegPressure // Scheduling for lowest register pressure.
108 /// NOTE: The constructor takes ownership of TLOF.
109 explicit TargetLowering(TargetMachine &TM, TargetLoweringObjectFile *TLOF);
110 virtual ~TargetLowering();
112 TargetMachine &getTargetMachine() const { return TM; }
113 const TargetData *getTargetData() const { return TD; }
114 TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
116 bool isBigEndian() const { return !IsLittleEndian; }
117 bool isLittleEndian() const { return IsLittleEndian; }
118 MVT getPointerTy() const { return PointerTy; }
119 MVT getShiftAmountTy() const { return ShiftAmountTy; }
121 /// isSelectExpensive - Return true if the select operation is expensive for
123 bool isSelectExpensive() const { return SelectIsExpensive; }
125 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
126 /// a sequence of several shifts, adds, and multiplies for this target.
127 bool isIntDivCheap() const { return IntDivIsCheap; }
129 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
131 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
133 /// getSetCCResultType - Return the ValueType of the result of SETCC
134 /// operations. Also used to obtain the target's preferred type for
135 /// the condition operand of SELECT and BRCOND nodes. In the case of
136 /// BRCOND the argument passed is MVT::Other since there are no other
137 /// operands to get a type hint from.
139 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
141 /// getCmpLibcallReturnType - Return the ValueType for comparison
142 /// libcalls. Comparions libcalls include floating point comparion calls,
143 /// and Ordered/Unordered check calls on floating point numbers.
145 MVT::SimpleValueType getCmpLibcallReturnType() const;
147 /// getBooleanContents - For targets without i1 registers, this gives the
148 /// nature of the high-bits of boolean values held in types wider than i1.
149 /// "Boolean values" are special true/false values produced by nodes like
150 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
151 /// Not to be confused with general values promoted from i1.
152 BooleanContent getBooleanContents() const { return BooleanContents;}
154 /// getSchedulingPreference - Return target scheduling preference.
155 SchedPreference getSchedulingPreference() const {
156 return SchedPreferenceInfo;
159 /// getRegClassFor - Return the register class that should be used for the
160 /// specified value type. This may only be called on legal types.
161 TargetRegisterClass *getRegClassFor(EVT VT) const {
162 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
163 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
164 assert(RC && "This value type is not natively supported!");
168 /// isTypeLegal - Return true if the target has native support for the
169 /// specified value type. This means that it has a register that directly
170 /// holds it without promotions or expansions.
171 bool isTypeLegal(EVT VT) const {
172 assert(!VT.isSimple() ||
173 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
174 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
177 class ValueTypeActionImpl {
178 /// ValueTypeActions - This is a bitvector that contains two bits for each
179 /// value type, where the two bits correspond to the LegalizeAction enum.
180 /// This can be queried with "getTypeAction(VT)".
181 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2
182 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2];
184 ValueTypeActionImpl() {
185 ValueTypeActions[0] = ValueTypeActions[1] = 0;
186 ValueTypeActions[2] = ValueTypeActions[3] = 0;
188 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
189 ValueTypeActions[0] = RHS.ValueTypeActions[0];
190 ValueTypeActions[1] = RHS.ValueTypeActions[1];
191 ValueTypeActions[2] = RHS.ValueTypeActions[2];
192 ValueTypeActions[3] = RHS.ValueTypeActions[3];
195 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
196 if (VT.isExtended()) {
198 return VT.isPow2VectorType() ? Expand : Promote;
201 // First promote to a power-of-two size, then expand if necessary.
202 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote;
203 assert(0 && "Unsupported extended type!");
206 unsigned I = VT.getSimpleVT().SimpleTy;
207 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
208 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
210 void setTypeAction(EVT VT, LegalizeAction Action) {
211 unsigned I = VT.getSimpleVT().SimpleTy;
212 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
213 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
217 const ValueTypeActionImpl &getValueTypeActions() const {
218 return ValueTypeActions;
221 /// getTypeAction - Return how we should legalize values of this type, either
222 /// it is already legal (return 'Legal') or we need to promote it to a larger
223 /// type (return 'Promote'), or we need to expand it into multiple registers
224 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
225 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
226 return ValueTypeActions.getTypeAction(Context, VT);
229 /// getTypeToTransformTo - For types supported by the target, this is an
230 /// identity function. For types that must be promoted to larger types, this
231 /// returns the larger type to promote to. For integer types that are larger
232 /// than the largest integer register, this contains one step in the expansion
233 /// to get to the smaller register. For illegal floating point types, this
234 /// returns the integer type to transform to.
235 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
237 assert((unsigned)VT.getSimpleVT().SimpleTy <
238 array_lengthof(TransformToType));
239 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
240 assert(getTypeAction(Context, NVT) != Promote &&
241 "Promote may not follow Expand or Promote");
246 EVT NVT = VT.getPow2VectorType(Context);
248 // Vector length is a power of 2 - split to half the size.
249 unsigned NumElts = VT.getVectorNumElements();
250 EVT EltVT = VT.getVectorElementType();
251 return (NumElts == 1) ?
252 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
254 // Promote to a power of two size, avoiding multi-step promotion.
255 return getTypeAction(Context, NVT) == Promote ?
256 getTypeToTransformTo(Context, NVT) : NVT;
257 } else if (VT.isInteger()) {
258 EVT NVT = VT.getRoundIntegerType(Context);
260 // Size is a power of two - expand to half the size.
261 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
263 // Promote to a power of two size, avoiding multi-step promotion.
264 return getTypeAction(Context, NVT) == Promote ?
265 getTypeToTransformTo(Context, NVT) : NVT;
267 assert(0 && "Unsupported extended type!");
268 return MVT(MVT::Other); // Not reached
271 /// getTypeToExpandTo - For types supported by the target, this is an
272 /// identity function. For types that must be expanded (i.e. integer types
273 /// that are larger than the largest integer register or illegal floating
274 /// point types), this returns the largest legal type it will be expanded to.
275 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
276 assert(!VT.isVector());
278 switch (getTypeAction(Context, VT)) {
282 VT = getTypeToTransformTo(Context, VT);
285 assert(false && "Type is not legal nor is it to be expanded!");
292 /// getVectorTypeBreakdown - Vector types are broken down into some number of
293 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
294 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
295 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
297 /// This method returns the number of registers needed, and the VT for each
298 /// register. It also returns the VT and quantity of the intermediate values
299 /// before they are promoted/expanded.
301 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
303 unsigned &NumIntermediates,
304 EVT &RegisterVT) const;
306 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
307 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
308 /// this is the case, it returns true and store the intrinsic
309 /// information into the IntrinsicInfo that was passed to the function.
310 typedef struct IntrinsicInfo {
311 unsigned opc; // target opcode
312 EVT memVT; // memory VT
313 const Value* ptrVal; // value representing memory location
314 int offset; // offset off of ptrVal
315 unsigned align; // alignment
316 bool vol; // is volatile?
317 bool readMem; // reads memory?
318 bool writeMem; // writes memory?
321 virtual bool getTgtMemIntrinsic(IntrinsicInfo& Info,
322 CallInst &I, unsigned Intrinsic) {
326 /// getWidenVectorType: given a vector type, returns the type to widen to
327 /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
328 /// If there is no vector type that we want to widen to, returns MVT::Other
329 /// When and were to widen is target dependent based on the cost of
330 /// scalarizing vs using the wider vector type.
331 virtual EVT getWidenVectorType(EVT VT) const;
333 /// isFPImmLegal - Returns true if the target can instruction select the
334 /// specified FP immediate natively. If false, the legalizer will materialize
335 /// the FP immediate as a load from a constant pool.
336 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
340 /// isShuffleMaskLegal - Targets can use this to indicate that they only
341 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
342 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
343 /// are assumed to be legal.
344 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
349 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
350 /// used by Targets can use this to indicate if there is a suitable
351 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
353 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
358 /// getOperationAction - Return how this operation should be treated: either
359 /// it is legal, needs to be promoted to a larger size, needs to be
360 /// expanded to some other code sequence, or the target has a custom expander
362 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
363 if (VT.isExtended()) return Expand;
364 assert(Op < array_lengthof(OpActions[0]) &&
365 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(OpActions[0][0])*8 &&
366 "Table isn't big enough!");
367 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
370 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3);
373 /// isOperationLegalOrCustom - Return true if the specified operation is
374 /// legal on this target or can be made legal with custom lowering. This
375 /// is used to help guide high-level lowering decisions.
376 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
377 return (VT == MVT::Other || isTypeLegal(VT)) &&
378 (getOperationAction(Op, VT) == Legal ||
379 getOperationAction(Op, VT) == Custom);
382 /// isOperationLegal - Return true if the specified operation is legal on this
384 bool isOperationLegal(unsigned Op, EVT VT) const {
385 return (VT == MVT::Other || isTypeLegal(VT)) &&
386 getOperationAction(Op, VT) == Legal;
389 /// getLoadExtAction - Return how this load with extension should be treated:
390 /// either it is legal, needs to be promoted to a larger size, needs to be
391 /// expanded to some other code sequence, or the target has a custom expander
393 LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const {
394 assert(LType < array_lengthof(LoadExtActions) &&
395 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(LoadExtActions[0])*4 &&
396 "Table isn't big enough!");
397 return (LegalizeAction)((LoadExtActions[LType] >>
398 (2*VT.getSimpleVT().SimpleTy)) & 3);
401 /// isLoadExtLegal - Return true if the specified load with extension is legal
403 bool isLoadExtLegal(unsigned LType, EVT VT) const {
404 return VT.isSimple() &&
405 (getLoadExtAction(LType, VT) == Legal ||
406 getLoadExtAction(LType, VT) == Custom);
409 /// getTruncStoreAction - Return how this store with truncation should be
410 /// treated: either it is legal, needs to be promoted to a larger size, needs
411 /// to be expanded to some other code sequence, or the target has a custom
413 LegalizeAction getTruncStoreAction(EVT ValVT,
415 assert((unsigned)ValVT.getSimpleVT().SimpleTy <
416 array_lengthof(TruncStoreActions) &&
417 (unsigned)MemVT.getSimpleVT().SimpleTy <
418 sizeof(TruncStoreActions[0])*4 &&
419 "Table isn't big enough!");
420 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT().SimpleTy] >>
421 (2*MemVT.getSimpleVT().SimpleTy)) & 3);
424 /// isTruncStoreLegal - Return true if the specified store with truncation is
425 /// legal on this target.
426 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
427 return isTypeLegal(ValVT) && MemVT.isSimple() &&
428 (getTruncStoreAction(ValVT, MemVT) == Legal ||
429 getTruncStoreAction(ValVT, MemVT) == Custom);
432 /// getIndexedLoadAction - Return how the indexed load should be treated:
433 /// either it is legal, needs to be promoted to a larger size, needs to be
434 /// expanded to some other code sequence, or the target has a custom expander
437 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
438 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
439 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
440 "Table isn't big enough!");
441 return (LegalizeAction)((IndexedModeActions[
442 (unsigned)VT.getSimpleVT().SimpleTy][0][IdxMode]));
445 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
447 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
448 return VT.isSimple() &&
449 (getIndexedLoadAction(IdxMode, VT) == Legal ||
450 getIndexedLoadAction(IdxMode, VT) == Custom);
453 /// getIndexedStoreAction - Return how the indexed store should be treated:
454 /// either it is legal, needs to be promoted to a larger size, needs to be
455 /// expanded to some other code sequence, or the target has a custom expander
458 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
459 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) &&
460 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
461 "Table isn't big enough!");
462 return (LegalizeAction)((IndexedModeActions[
463 (unsigned)VT.getSimpleVT().SimpleTy][1][IdxMode]));
466 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
468 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
469 return VT.isSimple() &&
470 (getIndexedStoreAction(IdxMode, VT) == Legal ||
471 getIndexedStoreAction(IdxMode, VT) == Custom);
474 /// getConvertAction - Return how the conversion should be treated:
475 /// either it is legal, needs to be promoted to a larger size, needs to be
476 /// expanded to some other code sequence, or the target has a custom expander
479 getConvertAction(EVT FromVT, EVT ToVT) const {
480 assert((unsigned)FromVT.getSimpleVT().SimpleTy <
481 array_lengthof(ConvertActions) &&
482 (unsigned)ToVT.getSimpleVT().SimpleTy <
483 sizeof(ConvertActions[0])*4 &&
484 "Table isn't big enough!");
485 return (LegalizeAction)((ConvertActions[FromVT.getSimpleVT().SimpleTy] >>
486 (2*ToVT.getSimpleVT().SimpleTy)) & 3);
489 /// isConvertLegal - Return true if the specified conversion is legal
491 bool isConvertLegal(EVT FromVT, EVT ToVT) const {
492 return isTypeLegal(FromVT) && isTypeLegal(ToVT) &&
493 (getConvertAction(FromVT, ToVT) == Legal ||
494 getConvertAction(FromVT, ToVT) == Custom);
497 /// getCondCodeAction - Return how the condition code should be treated:
498 /// either it is legal, needs to be expanded to some other code sequence,
499 /// or the target has a custom expander for it.
501 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
502 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
503 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
504 "Table isn't big enough!");
505 LegalizeAction Action = (LegalizeAction)
506 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
507 assert(Action != Promote && "Can't promote condition code!");
511 /// isCondCodeLegal - Return true if the specified condition code is legal
513 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
514 return getCondCodeAction(CC, VT) == Legal ||
515 getCondCodeAction(CC, VT) == Custom;
519 /// getTypeToPromoteTo - If the action for this operation is to promote, this
520 /// method returns the ValueType to promote to.
521 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
522 assert(getOperationAction(Op, VT) == Promote &&
523 "This operation isn't promoted!");
525 // See if this has an explicit type specified.
526 std::map<std::pair<unsigned, MVT::SimpleValueType>,
527 MVT::SimpleValueType>::const_iterator PTTI =
528 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
529 if (PTTI != PromoteToType.end()) return PTTI->second;
531 assert((VT.isInteger() || VT.isFloatingPoint()) &&
532 "Cannot autopromote this type, add it with AddPromotedToType.");
536 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
537 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
538 "Didn't find type to promote to!");
539 } while (!isTypeLegal(NVT) ||
540 getOperationAction(Op, NVT) == Promote);
544 /// getValueType - Return the EVT corresponding to this LLVM type.
545 /// This is fixed by the LLVM operations except for the pointer size. If
546 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
547 /// counterpart (e.g. structs), otherwise it will assert.
548 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
549 EVT VT = EVT::getEVT(Ty, AllowUnknown);
550 return VT == MVT:: iPTR ? PointerTy : VT;
553 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
554 /// function arguments in the caller parameter area. This is the actual
555 /// alignment, not its logarithm.
556 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
558 /// getRegisterType - Return the type of registers that this ValueType will
559 /// eventually require.
560 EVT getRegisterType(MVT VT) const {
561 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
562 return RegisterTypeForVT[VT.SimpleTy];
565 /// getRegisterType - Return the type of registers that this ValueType will
566 /// eventually require.
567 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
569 assert((unsigned)VT.getSimpleVT().SimpleTy <
570 array_lengthof(RegisterTypeForVT));
571 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
575 unsigned NumIntermediates;
576 (void)getVectorTypeBreakdown(Context, VT, VT1,
577 NumIntermediates, RegisterVT);
580 if (VT.isInteger()) {
581 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
583 assert(0 && "Unsupported extended type!");
584 return EVT(MVT::Other); // Not reached
587 /// getNumRegisters - Return the number of registers that this ValueType will
588 /// eventually require. This is one for any types promoted to live in larger
589 /// registers, but may be more than one for types (like i64) that are split
590 /// into pieces. For types like i140, which are first promoted then expanded,
591 /// it is the number of registers needed to hold all the bits of the original
592 /// type. For an i140 on a 32 bit machine this means 5 registers.
593 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
595 assert((unsigned)VT.getSimpleVT().SimpleTy <
596 array_lengthof(NumRegistersForVT));
597 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
601 unsigned NumIntermediates;
602 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
604 if (VT.isInteger()) {
605 unsigned BitWidth = VT.getSizeInBits();
606 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
607 return (BitWidth + RegWidth - 1) / RegWidth;
609 assert(0 && "Unsupported extended type!");
610 return 0; // Not reached
613 /// ShouldShrinkFPConstant - If true, then instruction selection should
614 /// seek to shrink the FP constant of the specified type to a smaller type
615 /// in order to save space and / or reduce runtime.
616 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
618 /// hasTargetDAGCombine - If true, the target has custom DAG combine
619 /// transformations that it can perform for the specified node.
620 bool hasTargetDAGCombine(ISD::NodeType NT) const {
621 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
622 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
625 /// This function returns the maximum number of store operations permitted
626 /// to replace a call to llvm.memset. The value is set by the target at the
627 /// performance threshold for such a replacement.
628 /// @brief Get maximum # of store operations permitted for llvm.memset
629 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
631 /// This function returns the maximum number of store operations permitted
632 /// to replace a call to llvm.memcpy. The value is set by the target at the
633 /// performance threshold for such a replacement.
634 /// @brief Get maximum # of store operations permitted for llvm.memcpy
635 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
637 /// This function returns the maximum number of store operations permitted
638 /// to replace a call to llvm.memmove. The value is set by the target at the
639 /// performance threshold for such a replacement.
640 /// @brief Get maximum # of store operations permitted for llvm.memmove
641 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
643 /// This function returns true if the target allows unaligned memory accesses.
644 /// of the specified type. This is used, for example, in situations where an
645 /// array copy/move/set is converted to a sequence of store operations. It's
646 /// use helps to ensure that such replacements don't generate code that causes
647 /// an alignment error (trap) on the target machine.
648 /// @brief Determine if the target supports unaligned memory accesses.
649 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
653 /// This function returns true if the target would benefit from code placement
655 /// @brief Determine if the target should perform code placement optimization.
656 bool shouldOptimizeCodePlacement() const {
657 return benefitFromCodePlacementOpt;
660 /// getOptimalMemOpType - Returns the target specific optimal type for load
661 /// and store operations as a result of memset, memcpy, and memmove lowering.
662 /// It returns EVT::iAny if SelectionDAG should be responsible for
664 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
665 bool isSrcConst, bool isSrcStr,
666 SelectionDAG &DAG) const {
670 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
671 /// to implement llvm.setjmp.
672 bool usesUnderscoreSetJmp() const {
673 return UseUnderscoreSetJmp;
676 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
677 /// to implement llvm.longjmp.
678 bool usesUnderscoreLongJmp() const {
679 return UseUnderscoreLongJmp;
682 /// getStackPointerRegisterToSaveRestore - If a physical register, this
683 /// specifies the register that llvm.savestack/llvm.restorestack should save
685 unsigned getStackPointerRegisterToSaveRestore() const {
686 return StackPointerRegisterToSaveRestore;
689 /// getExceptionAddressRegister - If a physical register, this returns
690 /// the register that receives the exception address on entry to a landing
692 unsigned getExceptionAddressRegister() const {
693 return ExceptionPointerRegister;
696 /// getExceptionSelectorRegister - If a physical register, this returns
697 /// the register that receives the exception typeid on entry to a landing
699 unsigned getExceptionSelectorRegister() const {
700 return ExceptionSelectorRegister;
703 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
704 /// set, the default is 200)
705 unsigned getJumpBufSize() const {
709 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
710 /// (if never set, the default is 0)
711 unsigned getJumpBufAlignment() const {
712 return JumpBufAlignment;
715 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
716 /// limit. Any block whose size is greater should not be predicated.
717 unsigned getIfCvtBlockSizeLimit() const {
718 return IfCvtBlockSizeLimit;
721 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
722 /// block to be considered for duplication. Any block whose size is greater
723 /// should not be duplicated to facilitate its predication.
724 unsigned getIfCvtDupBlockSizeLimit() const {
725 return IfCvtDupBlockSizeLimit;
728 /// getPrefLoopAlignment - return the preferred loop alignment.
730 unsigned getPrefLoopAlignment() const {
731 return PrefLoopAlignment;
734 /// getPreIndexedAddressParts - returns true by value, base pointer and
735 /// offset pointer and addressing mode by reference if the node's address
736 /// can be legally represented as pre-indexed load / store address.
737 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
739 ISD::MemIndexedMode &AM,
740 SelectionDAG &DAG) const {
744 /// getPostIndexedAddressParts - returns true by value, base pointer and
745 /// offset pointer and addressing mode by reference if this node can be
746 /// combined with a load / store to form a post-indexed load / store.
747 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
748 SDValue &Base, SDValue &Offset,
749 ISD::MemIndexedMode &AM,
750 SelectionDAG &DAG) const {
754 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
755 /// current function. The returned value is a member of the
756 /// MachineJumpTableInfo::JTEntryKind enum.
757 virtual unsigned getJumpTableEncoding() const;
759 virtual const MCExpr *
760 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
761 const MachineBasicBlock *MBB, unsigned uid,
762 MCContext &Ctx) const {
763 assert(0 && "Need to implement this hook if target has custom JTIs");
767 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
769 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
770 SelectionDAG &DAG) const;
772 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
773 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
775 virtual const MCExpr *
776 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
777 unsigned JTI, MCContext &Ctx) const;
779 /// isOffsetFoldingLegal - Return true if folding a constant offset
780 /// with the given GlobalAddress is legal. It is frequently not legal in
781 /// PIC relocation models.
782 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
784 /// getFunctionAlignment - Return the Log2 alignment of this function.
785 virtual unsigned getFunctionAlignment(const Function *) const = 0;
787 //===--------------------------------------------------------------------===//
788 // TargetLowering Optimization Methods
791 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
792 /// SDValues for returning information from TargetLowering to its clients
793 /// that want to combine
794 struct TargetLoweringOpt {
800 explicit TargetLoweringOpt(SelectionDAG &InDAG, bool Shrink = false) :
801 DAG(InDAG), ShrinkOps(Shrink) {}
803 bool CombineTo(SDValue O, SDValue N) {
809 /// ShrinkDemandedConstant - Check to see if the specified operand of the
810 /// specified instruction is a constant integer. If so, check to see if
811 /// there are any bits set in the constant that are not demanded. If so,
812 /// shrink the constant and return true.
813 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
815 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
816 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
817 /// cast, but it could be generalized for targets with other types of
818 /// implicit widening casts.
819 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
823 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
824 /// DemandedMask bits of the result of Op are ever used downstream. If we can
825 /// use this information to simplify Op, create a new simplified DAG node and
826 /// return true, returning the original and new nodes in Old and New.
827 /// Otherwise, analyze the expression and return a mask of KnownOne and
828 /// KnownZero bits for the expression (used to simplify the caller).
829 /// The KnownZero/One bits may only be accurate for those bits in the
831 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
832 APInt &KnownZero, APInt &KnownOne,
833 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
835 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
836 /// Mask are known to be either zero or one and return them in the
837 /// KnownZero/KnownOne bitsets.
838 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
842 const SelectionDAG &DAG,
843 unsigned Depth = 0) const;
845 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
846 /// targets that want to expose additional information about sign bits to the
848 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
849 unsigned Depth = 0) const;
851 struct DAGCombinerInfo {
852 void *DC; // The DAG Combiner object.
854 bool BeforeLegalizeOps;
855 bool CalledByLegalizer;
859 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
860 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
861 CalledByLegalizer(cl), DAG(dag) {}
863 bool isBeforeLegalize() const { return BeforeLegalize; }
864 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
865 bool isCalledByLegalizer() const { return CalledByLegalizer; }
867 void AddToWorklist(SDNode *N);
868 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
870 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
871 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
873 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
876 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
877 /// and cc. If it is unable to simplify it, return a null SDValue.
878 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
879 ISD::CondCode Cond, bool foldBooleans,
880 DAGCombinerInfo &DCI, DebugLoc dl) const;
882 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
883 /// node is a GlobalAddress + offset.
885 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
887 /// PerformDAGCombine - This method will be invoked for all target nodes and
888 /// for any target-independent nodes that the target has registered with
891 /// The semantics are as follows:
893 /// SDValue.Val == 0 - No change was made
894 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
895 /// otherwise - N should be replaced by the returned Operand.
897 /// In addition, methods provided by DAGCombinerInfo may be used to perform
898 /// more complex transformations.
900 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
902 //===--------------------------------------------------------------------===//
903 // TargetLowering Configuration Methods - These methods should be invoked by
904 // the derived class constructor to configure this object for the target.
908 /// setShiftAmountType - Describe the type that should be used for shift
909 /// amounts. This type defaults to the pointer type.
910 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
912 /// setBooleanContents - Specify how the target extends the result of a
913 /// boolean value from i1 to a wider type. See getBooleanContents.
914 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
916 /// setSchedulingPreference - Specify the target scheduling preference.
917 void setSchedulingPreference(SchedPreference Pref) {
918 SchedPreferenceInfo = Pref;
921 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
922 /// use _setjmp to implement llvm.setjmp or the non _ version.
923 /// Defaults to false.
924 void setUseUnderscoreSetJmp(bool Val) {
925 UseUnderscoreSetJmp = Val;
928 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
929 /// use _longjmp to implement llvm.longjmp or the non _ version.
930 /// Defaults to false.
931 void setUseUnderscoreLongJmp(bool Val) {
932 UseUnderscoreLongJmp = Val;
935 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
936 /// specifies the register that llvm.savestack/llvm.restorestack should save
938 void setStackPointerRegisterToSaveRestore(unsigned R) {
939 StackPointerRegisterToSaveRestore = R;
942 /// setExceptionPointerRegister - If set to a physical register, this sets
943 /// the register that receives the exception address on entry to a landing
945 void setExceptionPointerRegister(unsigned R) {
946 ExceptionPointerRegister = R;
949 /// setExceptionSelectorRegister - If set to a physical register, this sets
950 /// the register that receives the exception typeid on entry to a landing
952 void setExceptionSelectorRegister(unsigned R) {
953 ExceptionSelectorRegister = R;
956 /// SelectIsExpensive - Tells the code generator not to expand operations
957 /// into sequences that use the select operations if possible.
958 void setSelectIsExpensive() { SelectIsExpensive = true; }
960 /// setIntDivIsCheap - Tells the code generator that integer divide is
961 /// expensive, and if possible, should be replaced by an alternate sequence
962 /// of instructions not containing an integer divide.
963 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
965 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
966 /// srl/add/sra for a signed divide by power of two, and let the target handle
968 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
970 /// addRegisterClass - Add the specified register class as an available
971 /// regclass for the specified value type. This indicates the selector can
972 /// handle values of that class natively.
973 void addRegisterClass(EVT VT, TargetRegisterClass *RC) {
974 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
975 AvailableRegClasses.push_back(std::make_pair(VT, RC));
976 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
979 /// computeRegisterProperties - Once all of the register classes are added,
980 /// this allows us to compute derived properties we expose.
981 void computeRegisterProperties();
983 /// setOperationAction - Indicate that the specified operation does not work
984 /// with the specified type and indicate what to do about it.
985 void setOperationAction(unsigned Op, MVT VT,
986 LegalizeAction Action) {
987 unsigned I = (unsigned)VT.SimpleTy;
990 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2));
991 OpActions[I][Op] |= (uint64_t)Action << (J*2);
994 /// setLoadExtAction - Indicate that the specified load with extension does
995 /// not work with the with specified type and indicate what to do about it.
996 void setLoadExtAction(unsigned ExtType, MVT VT,
997 LegalizeAction Action) {
998 assert((unsigned)VT.SimpleTy*2 < 63 &&
999 ExtType < array_lengthof(LoadExtActions) &&
1000 "Table isn't big enough!");
1001 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1002 LoadExtActions[ExtType] |= (uint64_t)Action << VT.SimpleTy*2;
1005 /// setTruncStoreAction - Indicate that the specified truncating store does
1006 /// not work with the with specified type and indicate what to do about it.
1007 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1008 LegalizeAction Action) {
1009 assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) &&
1010 (unsigned)MemVT.SimpleTy*2 < 63 &&
1011 "Table isn't big enough!");
1012 TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2);
1013 TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2;
1016 /// setIndexedLoadAction - Indicate that the specified indexed load does or
1017 /// does not work with the with specified type and indicate what to do abort
1018 /// it. NOTE: All indexed mode loads are initialized to Expand in
1019 /// TargetLowering.cpp
1020 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1021 LegalizeAction Action) {
1022 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1023 IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
1024 "Table isn't big enough!");
1025 IndexedModeActions[(unsigned)VT.SimpleTy][0][IdxMode] = (uint8_t)Action;
1028 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1029 /// does not work with the with specified type and indicate what to do about
1030 /// it. NOTE: All indexed mode stores are initialized to Expand in
1031 /// TargetLowering.cpp
1032 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1033 LegalizeAction Action) {
1034 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1035 IdxMode < array_lengthof(IndexedModeActions[0][1] ) &&
1036 "Table isn't big enough!");
1037 IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action;
1040 /// setConvertAction - Indicate that the specified conversion does or does
1041 /// not work with the with specified type and indicate what to do about it.
1042 void setConvertAction(MVT FromVT, MVT ToVT,
1043 LegalizeAction Action) {
1044 assert((unsigned)FromVT.SimpleTy < array_lengthof(ConvertActions) &&
1045 (unsigned)ToVT.SimpleTy < MVT::LAST_VALUETYPE &&
1046 "Table isn't big enough!");
1047 ConvertActions[FromVT.SimpleTy] &= ~(uint64_t(3UL) << ToVT.SimpleTy*2);
1048 ConvertActions[FromVT.SimpleTy] |= (uint64_t)Action << ToVT.SimpleTy*2;
1051 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1052 /// supported on the target and indicate what to do about it.
1053 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1054 LegalizeAction Action) {
1055 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1056 (unsigned)CC < array_lengthof(CondCodeActions) &&
1057 "Table isn't big enough!");
1058 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1059 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1062 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1063 /// promotion code defaults to trying a larger integer/fp until it can find
1064 /// one that works. If that default is insufficient, this method can be used
1065 /// by the target to override the default.
1066 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1067 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1070 /// setTargetDAGCombine - Targets should invoke this method for each target
1071 /// independent node that they want to provide a custom DAG combiner for by
1072 /// implementing the PerformDAGCombine virtual method.
1073 void setTargetDAGCombine(ISD::NodeType NT) {
1074 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1075 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1078 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1079 /// bytes); default is 200
1080 void setJumpBufSize(unsigned Size) {
1084 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1085 /// alignment (in bytes); default is 0
1086 void setJumpBufAlignment(unsigned Align) {
1087 JumpBufAlignment = Align;
1090 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1091 /// limit (in number of instructions); default is 2.
1092 void setIfCvtBlockSizeLimit(unsigned Limit) {
1093 IfCvtBlockSizeLimit = Limit;
1096 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1097 /// of instructions) to be considered for code duplication during
1098 /// if-conversion; default is 2.
1099 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1100 IfCvtDupBlockSizeLimit = Limit;
1103 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1104 /// alignment is zero, it means the target does not care about loop alignment.
1105 void setPrefLoopAlignment(unsigned Align) {
1106 PrefLoopAlignment = Align;
1111 virtual const TargetSubtarget *getSubtarget() {
1112 assert(0 && "Not Implemented");
1113 return NULL; // this is here to silence compiler errors
1116 //===--------------------------------------------------------------------===//
1117 // Lowering methods - These methods must be implemented by targets so that
1118 // the SelectionDAGLowering code knows how to lower these.
1121 /// LowerFormalArguments - This hook must be implemented to lower the
1122 /// incoming (formal) arguments, described by the Ins array, into the
1123 /// specified DAG. The implementation should fill in the InVals array
1124 /// with legal-type argument values, and return the resulting token
1128 LowerFormalArguments(SDValue Chain,
1129 CallingConv::ID CallConv, bool isVarArg,
1130 const SmallVectorImpl<ISD::InputArg> &Ins,
1131 DebugLoc dl, SelectionDAG &DAG,
1132 SmallVectorImpl<SDValue> &InVals) {
1133 assert(0 && "Not Implemented");
1134 return SDValue(); // this is here to silence compiler errors
1137 /// LowerCallTo - This function lowers an abstract call to a function into an
1138 /// actual call. This returns a pair of operands. The first element is the
1139 /// return value for the function (if RetTy is not VoidTy). The second
1140 /// element is the outgoing token chain. It calls LowerCall to do the actual
1142 struct ArgListEntry {
1153 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1154 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1156 typedef std::vector<ArgListEntry> ArgListTy;
1157 std::pair<SDValue, SDValue>
1158 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1159 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1160 CallingConv::ID CallConv, bool isTailCall,
1161 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
1162 SelectionDAG &DAG, DebugLoc dl, unsigned Order);
1164 /// LowerCall - This hook must be implemented to lower calls into the
1165 /// the specified DAG. The outgoing arguments to the call are described
1166 /// by the Outs array, and the values to be returned by the call are
1167 /// described by the Ins array. The implementation should fill in the
1168 /// InVals array with legal-type return values from the call, and return
1169 /// the resulting token chain value.
1171 LowerCall(SDValue Chain, SDValue Callee,
1172 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
1173 const SmallVectorImpl<ISD::OutputArg> &Outs,
1174 const SmallVectorImpl<ISD::InputArg> &Ins,
1175 DebugLoc dl, SelectionDAG &DAG,
1176 SmallVectorImpl<SDValue> &InVals) {
1177 assert(0 && "Not Implemented");
1178 return SDValue(); // this is here to silence compiler errors
1181 /// CanLowerReturn - This hook should be implemented to check whether the
1182 /// return values described by the Outs array can fit into the return
1183 /// registers. If false is returned, an sret-demotion is performed.
1185 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1186 const SmallVectorImpl<EVT> &OutTys,
1187 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1190 // Return true by default to get preexisting behavior.
1193 /// LowerReturn - This hook must be implemented to lower outgoing
1194 /// return values, described by the Outs array, into the specified
1195 /// DAG. The implementation should return the resulting token chain
1199 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1200 const SmallVectorImpl<ISD::OutputArg> &Outs,
1201 DebugLoc dl, SelectionDAG &DAG) {
1202 assert(0 && "Not Implemented");
1203 return SDValue(); // this is here to silence compiler errors
1206 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
1207 /// memcpy. This can be used by targets to provide code sequences for cases
1208 /// that don't fit the target's parameters for simple loads/stores and can be
1209 /// more efficient than using a library call. This function can return a null
1210 /// SDValue if the target declines to use custom code and a different
1211 /// lowering strategy should be used.
1213 /// If AlwaysInline is true, the size is constant and the target should not
1214 /// emit any calls and is strongly encouraged to attempt to emit inline code
1215 /// even if it is beyond the usual threshold because this intrinsic is being
1216 /// expanded in a place where calls are not feasible (e.g. within the prologue
1217 /// for another call). If the target chooses to decline an AlwaysInline
1218 /// request here, legalize will resort to using simple loads and stores.
1220 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1222 SDValue Op1, SDValue Op2,
1223 SDValue Op3, unsigned Align,
1225 const Value *DstSV, uint64_t DstOff,
1226 const Value *SrcSV, uint64_t SrcOff) {
1230 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a
1231 /// memmove. This can be used by targets to provide code sequences for cases
1232 /// that don't fit the target's parameters for simple loads/stores and can be
1233 /// more efficient than using a library call. This function can return a null
1234 /// SDValue if the target declines to use custom code and a different
1235 /// lowering strategy should be used.
1237 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl,
1239 SDValue Op1, SDValue Op2,
1240 SDValue Op3, unsigned Align,
1241 const Value *DstSV, uint64_t DstOff,
1242 const Value *SrcSV, uint64_t SrcOff) {
1246 /// EmitTargetCodeForMemset - Emit target-specific code that performs a
1247 /// memset. This can be used by targets to provide code sequences for cases
1248 /// that don't fit the target's parameters for simple stores and can be more
1249 /// efficient than using a library call. This function can return a null
1250 /// SDValue if the target declines to use custom code and a different
1251 /// lowering strategy should be used.
1253 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
1255 SDValue Op1, SDValue Op2,
1256 SDValue Op3, unsigned Align,
1257 const Value *DstSV, uint64_t DstOff) {
1261 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1262 /// to legalize nodes with an illegal operand type but legal result types.
1263 /// It replaces the LowerOperation callback in the type Legalizer.
1264 /// The reason we can not do away with LowerOperation entirely is that
1265 /// LegalizeDAG isn't yet ready to use this callback.
1266 /// TODO: Consider merging with ReplaceNodeResults.
1268 /// The target places new result values for the node in Results (their number
1269 /// and types must exactly match those of the original return values of
1270 /// the node), or leaves Results empty, which indicates that the node is not
1271 /// to be custom lowered after all.
1272 /// The default implementation calls LowerOperation.
1273 virtual void LowerOperationWrapper(SDNode *N,
1274 SmallVectorImpl<SDValue> &Results,
1277 /// LowerOperation - This callback is invoked for operations that are
1278 /// unsupported by the target, which are registered to use 'custom' lowering,
1279 /// and whose defined values are all legal.
1280 /// If the target has no operations that require custom lowering, it need not
1281 /// implement this. The default implementation of this aborts.
1282 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
1284 /// ReplaceNodeResults - This callback is invoked when a node result type is
1285 /// illegal for the target, and the operation was registered to use 'custom'
1286 /// lowering for that result type. The target places new result values for
1287 /// the node in Results (their number and types must exactly match those of
1288 /// the original return values of the node), or leaves Results empty, which
1289 /// indicates that the node is not to be custom lowered after all.
1291 /// If the target has no operations that require custom lowering, it need not
1292 /// implement this. The default implementation aborts.
1293 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1294 SelectionDAG &DAG) {
1295 assert(0 && "ReplaceNodeResults not implemented for this target!");
1298 /// getTargetNodeName() - This method returns the name of a target specific
1300 virtual const char *getTargetNodeName(unsigned Opcode) const;
1302 /// createFastISel - This method returns a target specific FastISel object,
1303 /// or null if the target does not support "fast" ISel.
1305 createFastISel(MachineFunction &,
1306 MachineModuleInfo *, DwarfWriter *,
1307 DenseMap<const Value *, unsigned> &,
1308 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1309 DenseMap<const AllocaInst *, int> &
1311 , SmallSet<Instruction*, 8> &CatchInfoLost
1317 //===--------------------------------------------------------------------===//
1318 // Inline Asm Support hooks
1321 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1322 /// call to be explicit llvm code if it wants to. This is useful for
1323 /// turning simple inline asms into LLVM intrinsics, which gives the
1324 /// compiler more information about the behavior of the code.
1325 virtual bool ExpandInlineAsm(CallInst *CI) const {
1329 enum ConstraintType {
1330 C_Register, // Constraint represents specific register(s).
1331 C_RegisterClass, // Constraint represents any of register(s) in class.
1332 C_Memory, // Memory constraint.
1333 C_Other, // Something else.
1334 C_Unknown // Unsupported constraint.
1337 /// AsmOperandInfo - This contains information for each constraint that we are
1339 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1340 /// ConstraintCode - This contains the actual string for the code, like "m".
1341 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1342 /// most closely matches the operand.
1343 std::string ConstraintCode;
1345 /// ConstraintType - Information about the constraint code, e.g. Register,
1346 /// RegisterClass, Memory, Other, Unknown.
1347 TargetLowering::ConstraintType ConstraintType;
1349 /// CallOperandval - If this is the result output operand or a
1350 /// clobber, this is null, otherwise it is the incoming operand to the
1351 /// CallInst. This gets modified as the asm is processed.
1352 Value *CallOperandVal;
1354 /// ConstraintVT - The ValueType for the operand value.
1357 /// isMatchingInputConstraint - Return true of this is an input operand that
1358 /// is a matching constraint like "4".
1359 bool isMatchingInputConstraint() const;
1361 /// getMatchedOperand - If this is an input matching constraint, this method
1362 /// returns the output operand it matches.
1363 unsigned getMatchedOperand() const;
1365 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1366 : InlineAsm::ConstraintInfo(info),
1367 ConstraintType(TargetLowering::C_Unknown),
1368 CallOperandVal(0), ConstraintVT(MVT::Other) {
1372 /// ComputeConstraintToUse - Determines the constraint code and constraint
1373 /// type to use for the specific AsmOperandInfo, setting
1374 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1375 /// being passed in is available, it can be passed in as Op, otherwise an
1376 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1377 /// constraint of the inline asm instruction being processed is 'm'.
1378 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1381 SelectionDAG *DAG = 0) const;
1383 /// getConstraintType - Given a constraint, return the type of constraint it
1384 /// is for this target.
1385 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1387 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1388 /// return a list of registers that can be used to satisfy the constraint.
1389 /// This should only be used for C_RegisterClass constraints.
1390 virtual std::vector<unsigned>
1391 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1394 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1395 /// {edx}), return the register number and the register class for the
1398 /// Given a register class constraint, like 'r', if this corresponds directly
1399 /// to an LLVM register class, return a register of 0 and the register class
1402 /// This should only be used for C_Register constraints. On error,
1403 /// this returns a register number of 0 and a null register class pointer..
1404 virtual std::pair<unsigned, const TargetRegisterClass*>
1405 getRegForInlineAsmConstraint(const std::string &Constraint,
1408 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1409 /// with another that has more specific requirements based on the type of the
1410 /// corresponding operand. This returns null if there is no replacement to
1412 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1414 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1415 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1416 /// it means one of the asm constraint of the inline asm instruction being
1417 /// processed is 'm'.
1418 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1420 std::vector<SDValue> &Ops,
1421 SelectionDAG &DAG) const;
1423 //===--------------------------------------------------------------------===//
1424 // Instruction Emitting Hooks
1427 // EmitInstrWithCustomInserter - This method should be implemented by targets
1428 // that mark instructions with the 'usesCustomInserter' flag. These
1429 // instructions are special in various ways, which require special support to
1430 // insert. The specified MachineInstr is created but not inserted into any
1431 // basic blocks, and this method is called to expand it into a sequence of
1432 // instructions, potentially also creating new basic blocks and control flow.
1433 // When new basic blocks are inserted and the edges from MBB to its successors
1434 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
1436 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1437 MachineBasicBlock *MBB,
1438 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
1440 //===--------------------------------------------------------------------===//
1441 // Addressing mode description hooks (used by LSR etc).
1444 /// AddrMode - This represents an addressing mode of:
1445 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1446 /// If BaseGV is null, there is no BaseGV.
1447 /// If BaseOffs is zero, there is no base offset.
1448 /// If HasBaseReg is false, there is no base register.
1449 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1453 GlobalValue *BaseGV;
1457 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1460 /// isLegalAddressingMode - Return true if the addressing mode represented by
1461 /// AM is legal for this target, for a load/store of the specified type.
1462 /// The type may be VoidTy, in which case only return true if the addressing
1463 /// mode is legal for a load/store of any legal type.
1464 /// TODO: Handle pre/postinc as well.
1465 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1467 /// isTruncateFree - Return true if it's free to truncate a value of
1468 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1469 /// register EAX to i16 by referencing its sub-register AX.
1470 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1474 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1478 /// isZExtFree - Return true if any actual instruction that defines a
1479 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1480 /// register. This does not necessarily include registers defined in
1481 /// unknown ways, such as incoming arguments, or copies from unknown
1482 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1483 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1484 /// all instructions that define 32-bit values implicit zero-extend the
1485 /// result out to 64 bits.
1486 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1490 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1494 /// isNarrowingProfitable - Return true if it's profitable to narrow
1495 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1496 /// from i32 to i8 but not from i32 to i16.
1497 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1501 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1502 /// icmp immediate, that is the target has icmp instructions which can compare
1503 /// a register against the immediate without having to materialize the
1504 /// immediate into a register.
1505 virtual bool isLegalICmpImmediate(int64_t Imm) const {
1509 //===--------------------------------------------------------------------===//
1510 // Div utility functions
1512 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1513 std::vector<SDNode*>* Created) const;
1514 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1515 std::vector<SDNode*>* Created) const;
1518 //===--------------------------------------------------------------------===//
1519 // Runtime Library hooks
1522 /// setLibcallName - Rename the default libcall routine name for the specified
1524 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1525 LibcallRoutineNames[Call] = Name;
1528 /// getLibcallName - Get the libcall routine name for the specified libcall.
1530 const char *getLibcallName(RTLIB::Libcall Call) const {
1531 return LibcallRoutineNames[Call];
1534 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1535 /// result of the comparison libcall against zero.
1536 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1537 CmpLibcallCCs[Call] = CC;
1540 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1541 /// the comparison libcall against zero.
1542 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1543 return CmpLibcallCCs[Call];
1546 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1547 /// specified libcall.
1548 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1549 LibcallCallingConvs[Call] = CC;
1552 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1553 /// specified libcall.
1554 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1555 return LibcallCallingConvs[Call];
1560 const TargetData *TD;
1561 TargetLoweringObjectFile &TLOF;
1563 /// PointerTy - The type to use for pointers, usually i32 or i64.
1567 /// IsLittleEndian - True if this is a little endian target.
1569 bool IsLittleEndian;
1571 /// SelectIsExpensive - Tells the code generator not to expand operations
1572 /// into sequences that use the select operations if possible.
1573 bool SelectIsExpensive;
1575 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1576 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1577 /// a real cost model is in place. If we ever optimize for size, this will be
1578 /// set to true unconditionally.
1581 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1582 /// srl/add/sra for a signed divide by power of two, and let the target handle
1584 bool Pow2DivIsCheap;
1586 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1587 /// llvm.setjmp. Defaults to false.
1588 bool UseUnderscoreSetJmp;
1590 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1591 /// llvm.longjmp. Defaults to false.
1592 bool UseUnderscoreLongJmp;
1594 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1598 /// BooleanContents - Information about the contents of the high-bits in
1599 /// boolean values held in a type wider than i1. See getBooleanContents.
1600 BooleanContent BooleanContents;
1602 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1603 /// total cycles or lowest register usage.
1604 SchedPreference SchedPreferenceInfo;
1606 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1607 unsigned JumpBufSize;
1609 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1611 unsigned JumpBufAlignment;
1613 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1615 unsigned IfCvtBlockSizeLimit;
1617 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1618 /// duplicated during if-conversion.
1619 unsigned IfCvtDupBlockSizeLimit;
1621 /// PrefLoopAlignment - The perferred loop alignment.
1623 unsigned PrefLoopAlignment;
1625 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1626 /// specifies the register that llvm.savestack/llvm.restorestack should save
1628 unsigned StackPointerRegisterToSaveRestore;
1630 /// ExceptionPointerRegister - If set to a physical register, this specifies
1631 /// the register that receives the exception address on entry to a landing
1633 unsigned ExceptionPointerRegister;
1635 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1636 /// the register that receives the exception typeid on entry to a landing
1638 unsigned ExceptionSelectorRegister;
1640 /// RegClassForVT - This indicates the default register class to use for
1641 /// each ValueType the target supports natively.
1642 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1643 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1644 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1646 /// TransformToType - For any value types we are promoting or expanding, this
1647 /// contains the value type that we are changing to. For Expanded types, this
1648 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1649 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1650 /// by the system, this holds the same type (e.g. i32 -> i32).
1651 EVT TransformToType[MVT::LAST_VALUETYPE];
1653 /// OpActions - For each operation and each value type, keep a LegalizeAction
1654 /// that indicates how instruction selection should deal with the operation.
1655 /// Most operations are Legal (aka, supported natively by the target), but
1656 /// operations that are not should be described. Note that operations on
1657 /// non-legal value types are not described here.
1658 /// This array is accessed using VT.getSimpleVT(), so it is subject to
1659 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits.
1660 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
1662 /// LoadExtActions - For each load of load extension type and each value type,
1663 /// keep a LegalizeAction that indicates how instruction selection should deal
1665 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1667 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1668 /// indicates how instruction selection should deal with the store.
1669 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1671 /// IndexedModeActions - For each indexed mode and each value type,
1672 /// keep a pair of LegalizeAction that indicates how instruction
1673 /// selection should deal with the load / store. The first
1674 /// dimension is now the value_type for the reference. The second
1675 /// dimension is the load [0] vs. store[1]. The third dimension
1676 /// represents the various modes for load store.
1677 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
1679 /// ConvertActions - For each conversion from source type to destination type,
1680 /// keep a LegalizeAction that indicates how instruction selection should
1681 /// deal with the conversion.
1682 /// Currently, this is used only for floating->floating conversions
1683 /// (FP_EXTEND and FP_ROUND).
1684 uint64_t ConvertActions[MVT::LAST_VALUETYPE];
1686 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1687 /// LegalizeAction that indicates how instruction selection should
1688 /// deal with the condition code.
1689 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1691 ValueTypeActionImpl ValueTypeActions;
1693 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1695 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1696 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1697 /// which sets a bit in this array.
1699 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1701 /// PromoteToType - For operations that must be promoted to a specific type,
1702 /// this holds the destination type. This map should be sparse, so don't hold
1705 /// Targets add entries to this map with AddPromotedToType(..), clients access
1706 /// this with getTypeToPromoteTo(..).
1707 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1710 /// LibcallRoutineNames - Stores the name each libcall.
1712 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1714 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1715 /// of each of the comparison libcall against zero.
1716 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1718 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1720 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1723 /// When lowering \@llvm.memset this field specifies the maximum number of
1724 /// store operations that may be substituted for the call to memset. Targets
1725 /// must set this value based on the cost threshold for that target. Targets
1726 /// should assume that the memset will be done using as many of the largest
1727 /// store operations first, followed by smaller ones, if necessary, per
1728 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1729 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1730 /// store. This only applies to setting a constant array of a constant size.
1731 /// @brief Specify maximum number of store instructions per memset call.
1732 unsigned maxStoresPerMemset;
1734 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1735 /// store operations that may be substituted for a call to memcpy. Targets
1736 /// must set this value based on the cost threshold for that target. Targets
1737 /// should assume that the memcpy will be done using as many of the largest
1738 /// store operations first, followed by smaller ones, if necessary, per
1739 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1740 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1741 /// and one 1-byte store. This only applies to copying a constant array of
1743 /// @brief Specify maximum bytes of store instructions per memcpy call.
1744 unsigned maxStoresPerMemcpy;
1746 /// When lowering \@llvm.memmove this field specifies the maximum number of
1747 /// store instructions that may be substituted for a call to memmove. Targets
1748 /// must set this value based on the cost threshold for that target. Targets
1749 /// should assume that the memmove will be done using as many of the largest
1750 /// store operations first, followed by smaller ones, if necessary, per
1751 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1752 /// with 8-bit alignment would result in nine 1-byte stores. This only
1753 /// applies to copying a constant array of constant size.
1754 /// @brief Specify maximum bytes of store instructions per memmove call.
1755 unsigned maxStoresPerMemmove;
1757 /// This field specifies whether the target can benefit from code placement
1759 bool benefitFromCodePlacementOpt;
1761 } // end llvm namespace