1 //===-- llvm/Target/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes how to lower LLVM code to machine code. This has two
13 // 1. Which ValueTypes are natively supported by the target.
14 // 2. Which operations are supported for supported ValueTypes.
15 // 3. Cost thresholds for alternative implementations of certain operations.
17 // In addition it has a few other components, like information about FP
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TARGET_TARGETLOWERING_H
23 #define LLVM_TARGET_TARGETLOWERING_H
25 #include "llvm/CallingConv.h"
26 #include "llvm/InlineAsm.h"
27 #include "llvm/CodeGen/SelectionDAGNodes.h"
28 #include "llvm/CodeGen/RuntimeLibcalls.h"
29 #include "llvm/ADT/APFloat.h"
30 #include "llvm/ADT/DenseMap.h"
31 #include "llvm/ADT/SmallSet.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/STLExtras.h"
34 #include "llvm/Support/DebugLoc.h"
35 #include "llvm/Target/TargetMachine.h"
45 class MachineBasicBlock;
46 class MachineFunction;
47 class MachineFrameInfo;
49 class MachineJumpTableInfo;
50 class MachineModuleInfo;
59 class TargetRegisterClass;
60 class TargetSubtarget;
61 class TargetLoweringObjectFile;
64 // FIXME: should this be here?
73 TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc);
76 //===----------------------------------------------------------------------===//
77 /// TargetLowering - This class defines information used to lower LLVM code to
78 /// legal SelectionDAG operators that the target instruction selector can accept
81 /// This class also defines callbacks that targets must implement to lower
82 /// target-specific constructs to SelectionDAG operators.
84 class TargetLowering {
85 TargetLowering(const TargetLowering&); // DO NOT IMPLEMENT
86 void operator=(const TargetLowering&); // DO NOT IMPLEMENT
88 /// LegalizeAction - This enum indicates whether operations are valid for a
89 /// target, and if not, what action should be used to make them valid.
91 Legal, // The target natively supports this operation.
92 Promote, // This operation should be executed in a larger type.
93 Expand, // Try to expand this to other ops, otherwise use a libcall.
94 Custom // Use the LowerOperation hook to implement custom lowering.
97 enum BooleanContent { // How the target represents true/false values.
98 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
99 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
100 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
103 enum SchedPreference {
104 SchedulingForLatency, // Scheduling for shortest total latency.
105 SchedulingForRegPressure // Scheduling for lowest register pressure.
108 /// NOTE: The constructor takes ownership of TLOF.
109 explicit TargetLowering(TargetMachine &TM, TargetLoweringObjectFile *TLOF);
110 virtual ~TargetLowering();
112 TargetMachine &getTargetMachine() const { return TM; }
113 const TargetData *getTargetData() const { return TD; }
114 TargetLoweringObjectFile &getObjFileLowering() const { return TLOF; }
116 bool isBigEndian() const { return !IsLittleEndian; }
117 bool isLittleEndian() const { return IsLittleEndian; }
118 MVT getPointerTy() const { return PointerTy; }
119 MVT getShiftAmountTy() const { return ShiftAmountTy; }
121 /// isSelectExpensive - Return true if the select operation is expensive for
123 bool isSelectExpensive() const { return SelectIsExpensive; }
125 /// isIntDivCheap() - Return true if integer divide is usually cheaper than
126 /// a sequence of several shifts, adds, and multiplies for this target.
127 bool isIntDivCheap() const { return IntDivIsCheap; }
129 /// isPow2DivCheap() - Return true if pow2 div is cheaper than a chain of
131 bool isPow2DivCheap() const { return Pow2DivIsCheap; }
133 /// getSetCCResultType - Return the ValueType of the result of SETCC
134 /// operations. Also used to obtain the target's preferred type for
135 /// the condition operand of SELECT and BRCOND nodes. In the case of
136 /// BRCOND the argument passed is MVT::Other since there are no other
137 /// operands to get a type hint from.
139 MVT::SimpleValueType getSetCCResultType(EVT VT) const;
141 /// getCmpLibcallReturnType - Return the ValueType for comparison
142 /// libcalls. Comparions libcalls include floating point comparion calls,
143 /// and Ordered/Unordered check calls on floating point numbers.
145 MVT::SimpleValueType getCmpLibcallReturnType() const;
147 /// getBooleanContents - For targets without i1 registers, this gives the
148 /// nature of the high-bits of boolean values held in types wider than i1.
149 /// "Boolean values" are special true/false values produced by nodes like
150 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
151 /// Not to be confused with general values promoted from i1.
152 BooleanContent getBooleanContents() const { return BooleanContents;}
154 /// getSchedulingPreference - Return target scheduling preference.
155 SchedPreference getSchedulingPreference() const {
156 return SchedPreferenceInfo;
159 /// getRegClassFor - Return the register class that should be used for the
160 /// specified value type. This may only be called on legal types.
161 TargetRegisterClass *getRegClassFor(EVT VT) const {
162 assert(VT.isSimple() && "getRegClassFor called on illegal type!");
163 TargetRegisterClass *RC = RegClassForVT[VT.getSimpleVT().SimpleTy];
164 assert(RC && "This value type is not natively supported!");
168 /// isTypeLegal - Return true if the target has native support for the
169 /// specified value type. This means that it has a register that directly
170 /// holds it without promotions or expansions.
171 bool isTypeLegal(EVT VT) const {
172 assert(!VT.isSimple() ||
173 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
174 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != 0;
177 class ValueTypeActionImpl {
178 /// ValueTypeActions - This is a bitvector that contains two bits for each
179 /// value type, where the two bits correspond to the LegalizeAction enum.
180 /// This can be queried with "getTypeAction(VT)".
181 /// dimension by (MVT::MAX_ALLOWED_VALUETYPE/32) * 2
182 uint32_t ValueTypeActions[(MVT::MAX_ALLOWED_VALUETYPE/32)*2];
184 ValueTypeActionImpl() {
185 ValueTypeActions[0] = ValueTypeActions[1] = 0;
186 ValueTypeActions[2] = ValueTypeActions[3] = 0;
188 ValueTypeActionImpl(const ValueTypeActionImpl &RHS) {
189 ValueTypeActions[0] = RHS.ValueTypeActions[0];
190 ValueTypeActions[1] = RHS.ValueTypeActions[1];
191 ValueTypeActions[2] = RHS.ValueTypeActions[2];
192 ValueTypeActions[3] = RHS.ValueTypeActions[3];
195 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
196 if (VT.isExtended()) {
198 return VT.isPow2VectorType() ? Expand : Promote;
201 // First promote to a power-of-two size, then expand if necessary.
202 return VT == VT.getRoundIntegerType(Context) ? Expand : Promote;
203 assert(0 && "Unsupported extended type!");
206 unsigned I = VT.getSimpleVT().SimpleTy;
207 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
208 return (LegalizeAction)((ValueTypeActions[I>>4] >> ((2*I) & 31)) & 3);
210 void setTypeAction(EVT VT, LegalizeAction Action) {
211 unsigned I = VT.getSimpleVT().SimpleTy;
212 assert(I<4*array_lengthof(ValueTypeActions)*sizeof(ValueTypeActions[0]));
213 ValueTypeActions[I>>4] |= Action << ((I*2) & 31);
217 const ValueTypeActionImpl &getValueTypeActions() const {
218 return ValueTypeActions;
221 /// getTypeAction - Return how we should legalize values of this type, either
222 /// it is already legal (return 'Legal') or we need to promote it to a larger
223 /// type (return 'Promote'), or we need to expand it into multiple registers
224 /// of smaller integer type (return 'Expand'). 'Custom' is not an option.
225 LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const {
226 return ValueTypeActions.getTypeAction(Context, VT);
229 /// getTypeToTransformTo - For types supported by the target, this is an
230 /// identity function. For types that must be promoted to larger types, this
231 /// returns the larger type to promote to. For integer types that are larger
232 /// than the largest integer register, this contains one step in the expansion
233 /// to get to the smaller register. For illegal floating point types, this
234 /// returns the integer type to transform to.
235 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
237 assert((unsigned)VT.getSimpleVT().SimpleTy <
238 array_lengthof(TransformToType));
239 EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy];
240 assert(getTypeAction(Context, NVT) != Promote &&
241 "Promote may not follow Expand or Promote");
246 EVT NVT = VT.getPow2VectorType(Context);
248 // Vector length is a power of 2 - split to half the size.
249 unsigned NumElts = VT.getVectorNumElements();
250 EVT EltVT = VT.getVectorElementType();
251 return (NumElts == 1) ?
252 EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2);
254 // Promote to a power of two size, avoiding multi-step promotion.
255 return getTypeAction(Context, NVT) == Promote ?
256 getTypeToTransformTo(Context, NVT) : NVT;
257 } else if (VT.isInteger()) {
258 EVT NVT = VT.getRoundIntegerType(Context);
260 // Size is a power of two - expand to half the size.
261 return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2);
263 // Promote to a power of two size, avoiding multi-step promotion.
264 return getTypeAction(Context, NVT) == Promote ?
265 getTypeToTransformTo(Context, NVT) : NVT;
267 assert(0 && "Unsupported extended type!");
268 return MVT(MVT::Other); // Not reached
271 /// getTypeToExpandTo - For types supported by the target, this is an
272 /// identity function. For types that must be expanded (i.e. integer types
273 /// that are larger than the largest integer register or illegal floating
274 /// point types), this returns the largest legal type it will be expanded to.
275 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
276 assert(!VT.isVector());
278 switch (getTypeAction(Context, VT)) {
282 VT = getTypeToTransformTo(Context, VT);
285 assert(false && "Type is not legal nor is it to be expanded!");
292 /// getVectorTypeBreakdown - Vector types are broken down into some number of
293 /// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
294 /// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
295 /// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
297 /// This method returns the number of registers needed, and the VT for each
298 /// register. It also returns the VT and quantity of the intermediate values
299 /// before they are promoted/expanded.
301 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
303 unsigned &NumIntermediates,
304 EVT &RegisterVT) const;
306 /// getTgtMemIntrinsic: Given an intrinsic, checks if on the target the
307 /// intrinsic will need to map to a MemIntrinsicNode (touches memory). If
308 /// this is the case, it returns true and store the intrinsic
309 /// information into the IntrinsicInfo that was passed to the function.
310 struct IntrinsicInfo {
311 unsigned opc; // target opcode
312 EVT memVT; // memory VT
313 const Value* ptrVal; // value representing memory location
314 int offset; // offset off of ptrVal
315 unsigned align; // alignment
316 bool vol; // is volatile?
317 bool readMem; // reads memory?
318 bool writeMem; // writes memory?
321 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
322 CallInst &I, unsigned Intrinsic) {
326 /// isFPImmLegal - Returns true if the target can instruction select the
327 /// specified FP immediate natively. If false, the legalizer will materialize
328 /// the FP immediate as a load from a constant pool.
329 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
333 /// isShuffleMaskLegal - Targets can use this to indicate that they only
334 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
335 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
336 /// are assumed to be legal.
337 virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
342 /// canOpTrap - Returns true if the operation can trap for the value type.
343 /// VT must be a legal type. By default, we optimistically assume most
344 /// operations don't trap except for divide and remainder.
345 virtual bool canOpTrap(unsigned Op, EVT VT) const;
347 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
348 /// used by Targets can use this to indicate if there is a suitable
349 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
351 virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
356 /// getOperationAction - Return how this operation should be treated: either
357 /// it is legal, needs to be promoted to a larger size, needs to be
358 /// expanded to some other code sequence, or the target has a custom expander
360 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
361 if (VT.isExtended()) return Expand;
362 assert(Op < array_lengthof(OpActions[0]) &&
363 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(OpActions[0][0])*8 &&
364 "Table isn't big enough!");
365 unsigned I = (unsigned) VT.getSimpleVT().SimpleTy;
368 return (LegalizeAction)((OpActions[I][Op] >> (J*2) ) & 3);
371 /// isOperationLegalOrCustom - Return true if the specified operation is
372 /// legal on this target or can be made legal with custom lowering. This
373 /// is used to help guide high-level lowering decisions.
374 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
375 return (VT == MVT::Other || isTypeLegal(VT)) &&
376 (getOperationAction(Op, VT) == Legal ||
377 getOperationAction(Op, VT) == Custom);
380 /// isOperationLegal - Return true if the specified operation is legal on this
382 bool isOperationLegal(unsigned Op, EVT VT) const {
383 return (VT == MVT::Other || isTypeLegal(VT)) &&
384 getOperationAction(Op, VT) == Legal;
387 /// getLoadExtAction - Return how this load with extension should be treated:
388 /// either it is legal, needs to be promoted to a larger size, needs to be
389 /// expanded to some other code sequence, or the target has a custom expander
391 LegalizeAction getLoadExtAction(unsigned LType, EVT VT) const {
392 assert(LType < array_lengthof(LoadExtActions) &&
393 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(LoadExtActions[0])*4 &&
394 "Table isn't big enough!");
395 return (LegalizeAction)((LoadExtActions[LType] >>
396 (2*VT.getSimpleVT().SimpleTy)) & 3);
399 /// isLoadExtLegal - Return true if the specified load with extension is legal
401 bool isLoadExtLegal(unsigned LType, EVT VT) const {
402 return VT.isSimple() &&
403 (getLoadExtAction(LType, VT) == Legal ||
404 getLoadExtAction(LType, VT) == Custom);
407 /// getTruncStoreAction - Return how this store with truncation should be
408 /// treated: either it is legal, needs to be promoted to a larger size, needs
409 /// to be expanded to some other code sequence, or the target has a custom
411 LegalizeAction getTruncStoreAction(EVT ValVT,
413 assert((unsigned)ValVT.getSimpleVT().SimpleTy <
414 array_lengthof(TruncStoreActions) &&
415 (unsigned)MemVT.getSimpleVT().SimpleTy <
416 sizeof(TruncStoreActions[0])*4 &&
417 "Table isn't big enough!");
418 return (LegalizeAction)((TruncStoreActions[ValVT.getSimpleVT().SimpleTy] >>
419 (2*MemVT.getSimpleVT().SimpleTy)) & 3);
422 /// isTruncStoreLegal - Return true if the specified store with truncation is
423 /// legal on this target.
424 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
425 return isTypeLegal(ValVT) && MemVT.isSimple() &&
426 (getTruncStoreAction(ValVT, MemVT) == Legal ||
427 getTruncStoreAction(ValVT, MemVT) == Custom);
430 /// getIndexedLoadAction - Return how the indexed load should be treated:
431 /// either it is legal, needs to be promoted to a larger size, needs to be
432 /// expanded to some other code sequence, or the target has a custom expander
435 getIndexedLoadAction(unsigned IdxMode, EVT VT) const {
436 assert( IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
437 ((unsigned)VT.getSimpleVT().SimpleTy) < MVT::LAST_VALUETYPE &&
438 "Table isn't big enough!");
439 return (LegalizeAction)((IndexedModeActions[
440 (unsigned)VT.getSimpleVT().SimpleTy][0][IdxMode]));
443 /// isIndexedLoadLegal - Return true if the specified indexed load is legal
445 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
446 return VT.isSimple() &&
447 (getIndexedLoadAction(IdxMode, VT) == Legal ||
448 getIndexedLoadAction(IdxMode, VT) == Custom);
451 /// getIndexedStoreAction - Return how the indexed store should be treated:
452 /// either it is legal, needs to be promoted to a larger size, needs to be
453 /// expanded to some other code sequence, or the target has a custom expander
456 getIndexedStoreAction(unsigned IdxMode, EVT VT) const {
457 assert(IdxMode < array_lengthof(IndexedModeActions[0][1]) &&
458 (unsigned)VT.getSimpleVT().SimpleTy < MVT::LAST_VALUETYPE &&
459 "Table isn't big enough!");
460 return (LegalizeAction)((IndexedModeActions[
461 (unsigned)VT.getSimpleVT().SimpleTy][1][IdxMode]));
464 /// isIndexedStoreLegal - Return true if the specified indexed load is legal
466 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
467 return VT.isSimple() &&
468 (getIndexedStoreAction(IdxMode, VT) == Legal ||
469 getIndexedStoreAction(IdxMode, VT) == Custom);
472 /// getCondCodeAction - Return how the condition code should be treated:
473 /// either it is legal, needs to be expanded to some other code sequence,
474 /// or the target has a custom expander for it.
476 getCondCodeAction(ISD::CondCode CC, EVT VT) const {
477 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
478 (unsigned)VT.getSimpleVT().SimpleTy < sizeof(CondCodeActions[0])*4 &&
479 "Table isn't big enough!");
480 LegalizeAction Action = (LegalizeAction)
481 ((CondCodeActions[CC] >> (2*VT.getSimpleVT().SimpleTy)) & 3);
482 assert(Action != Promote && "Can't promote condition code!");
486 /// isCondCodeLegal - Return true if the specified condition code is legal
488 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const {
489 return getCondCodeAction(CC, VT) == Legal ||
490 getCondCodeAction(CC, VT) == Custom;
494 /// getTypeToPromoteTo - If the action for this operation is to promote, this
495 /// method returns the ValueType to promote to.
496 EVT getTypeToPromoteTo(unsigned Op, EVT VT) const {
497 assert(getOperationAction(Op, VT) == Promote &&
498 "This operation isn't promoted!");
500 // See if this has an explicit type specified.
501 std::map<std::pair<unsigned, MVT::SimpleValueType>,
502 MVT::SimpleValueType>::const_iterator PTTI =
503 PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy));
504 if (PTTI != PromoteToType.end()) return PTTI->second;
506 assert((VT.isInteger() || VT.isFloatingPoint()) &&
507 "Cannot autopromote this type, add it with AddPromotedToType.");
511 NVT = (MVT::SimpleValueType)(NVT.getSimpleVT().SimpleTy+1);
512 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
513 "Didn't find type to promote to!");
514 } while (!isTypeLegal(NVT) ||
515 getOperationAction(Op, NVT) == Promote);
519 /// getValueType - Return the EVT corresponding to this LLVM type.
520 /// This is fixed by the LLVM operations except for the pointer size. If
521 /// AllowUnknown is true, this will return MVT::Other for types with no EVT
522 /// counterpart (e.g. structs), otherwise it will assert.
523 EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
524 EVT VT = EVT::getEVT(Ty, AllowUnknown);
525 return VT == MVT::iPTR ? PointerTy : VT;
528 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
529 /// function arguments in the caller parameter area. This is the actual
530 /// alignment, not its logarithm.
531 virtual unsigned getByValTypeAlignment(const Type *Ty) const;
533 /// getRegisterType - Return the type of registers that this ValueType will
534 /// eventually require.
535 EVT getRegisterType(MVT VT) const {
536 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
537 return RegisterTypeForVT[VT.SimpleTy];
540 /// getRegisterType - Return the type of registers that this ValueType will
541 /// eventually require.
542 EVT getRegisterType(LLVMContext &Context, EVT VT) const {
544 assert((unsigned)VT.getSimpleVT().SimpleTy <
545 array_lengthof(RegisterTypeForVT));
546 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
550 unsigned NumIntermediates;
551 (void)getVectorTypeBreakdown(Context, VT, VT1,
552 NumIntermediates, RegisterVT);
555 if (VT.isInteger()) {
556 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
558 assert(0 && "Unsupported extended type!");
559 return EVT(MVT::Other); // Not reached
562 /// getNumRegisters - Return the number of registers that this ValueType will
563 /// eventually require. This is one for any types promoted to live in larger
564 /// registers, but may be more than one for types (like i64) that are split
565 /// into pieces. For types like i140, which are first promoted then expanded,
566 /// it is the number of registers needed to hold all the bits of the original
567 /// type. For an i140 on a 32 bit machine this means 5 registers.
568 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
570 assert((unsigned)VT.getSimpleVT().SimpleTy <
571 array_lengthof(NumRegistersForVT));
572 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
576 unsigned NumIntermediates;
577 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
579 if (VT.isInteger()) {
580 unsigned BitWidth = VT.getSizeInBits();
581 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
582 return (BitWidth + RegWidth - 1) / RegWidth;
584 assert(0 && "Unsupported extended type!");
585 return 0; // Not reached
588 /// ShouldShrinkFPConstant - If true, then instruction selection should
589 /// seek to shrink the FP constant of the specified type to a smaller type
590 /// in order to save space and / or reduce runtime.
591 virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
593 /// hasTargetDAGCombine - If true, the target has custom DAG combine
594 /// transformations that it can perform for the specified node.
595 bool hasTargetDAGCombine(ISD::NodeType NT) const {
596 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
597 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
600 /// This function returns the maximum number of store operations permitted
601 /// to replace a call to llvm.memset. The value is set by the target at the
602 /// performance threshold for such a replacement.
603 /// @brief Get maximum # of store operations permitted for llvm.memset
604 unsigned getMaxStoresPerMemset() const { return maxStoresPerMemset; }
606 /// This function returns the maximum number of store operations permitted
607 /// to replace a call to llvm.memcpy. The value is set by the target at the
608 /// performance threshold for such a replacement.
609 /// @brief Get maximum # of store operations permitted for llvm.memcpy
610 unsigned getMaxStoresPerMemcpy() const { return maxStoresPerMemcpy; }
612 /// This function returns the maximum number of store operations permitted
613 /// to replace a call to llvm.memmove. The value is set by the target at the
614 /// performance threshold for such a replacement.
615 /// @brief Get maximum # of store operations permitted for llvm.memmove
616 unsigned getMaxStoresPerMemmove() const { return maxStoresPerMemmove; }
618 /// This function returns true if the target allows unaligned memory accesses.
619 /// of the specified type. This is used, for example, in situations where an
620 /// array copy/move/set is converted to a sequence of store operations. It's
621 /// use helps to ensure that such replacements don't generate code that causes
622 /// an alignment error (trap) on the target machine.
623 /// @brief Determine if the target supports unaligned memory accesses.
624 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
628 /// This function returns true if the target would benefit from code placement
630 /// @brief Determine if the target should perform code placement optimization.
631 bool shouldOptimizeCodePlacement() const {
632 return benefitFromCodePlacementOpt;
635 /// getOptimalMemOpType - Returns the target specific optimal type for load
636 /// and store operations as a result of memset, memcpy, and memmove lowering.
637 /// If DstAlign is zero that means it's safe to destination alignment can
638 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
639 /// a need to check it against alignment requirement, probably because the
640 /// source does not need to be loaded. It returns EVT::Other if SelectionDAG
641 /// should be responsible for determining it.
642 virtual EVT getOptimalMemOpType(uint64_t Size,
643 unsigned DstAlign, unsigned SrcAlign,
644 bool SafeToUseFP, SelectionDAG &DAG) const {
648 /// usesUnderscoreSetJmp - Determine if we should use _setjmp or setjmp
649 /// to implement llvm.setjmp.
650 bool usesUnderscoreSetJmp() const {
651 return UseUnderscoreSetJmp;
654 /// usesUnderscoreLongJmp - Determine if we should use _longjmp or longjmp
655 /// to implement llvm.longjmp.
656 bool usesUnderscoreLongJmp() const {
657 return UseUnderscoreLongJmp;
660 /// getStackPointerRegisterToSaveRestore - If a physical register, this
661 /// specifies the register that llvm.savestack/llvm.restorestack should save
663 unsigned getStackPointerRegisterToSaveRestore() const {
664 return StackPointerRegisterToSaveRestore;
667 /// getExceptionAddressRegister - If a physical register, this returns
668 /// the register that receives the exception address on entry to a landing
670 unsigned getExceptionAddressRegister() const {
671 return ExceptionPointerRegister;
674 /// getExceptionSelectorRegister - If a physical register, this returns
675 /// the register that receives the exception typeid on entry to a landing
677 unsigned getExceptionSelectorRegister() const {
678 return ExceptionSelectorRegister;
681 /// getJumpBufSize - returns the target's jmp_buf size in bytes (if never
682 /// set, the default is 200)
683 unsigned getJumpBufSize() const {
687 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
688 /// (if never set, the default is 0)
689 unsigned getJumpBufAlignment() const {
690 return JumpBufAlignment;
693 /// getIfCvtBlockLimit - returns the target specific if-conversion block size
694 /// limit. Any block whose size is greater should not be predicated.
695 unsigned getIfCvtBlockSizeLimit() const {
696 return IfCvtBlockSizeLimit;
699 /// getIfCvtDupBlockLimit - returns the target specific size limit for a
700 /// block to be considered for duplication. Any block whose size is greater
701 /// should not be duplicated to facilitate its predication.
702 unsigned getIfCvtDupBlockSizeLimit() const {
703 return IfCvtDupBlockSizeLimit;
706 /// getPrefLoopAlignment - return the preferred loop alignment.
708 unsigned getPrefLoopAlignment() const {
709 return PrefLoopAlignment;
712 /// getPreIndexedAddressParts - returns true by value, base pointer and
713 /// offset pointer and addressing mode by reference if the node's address
714 /// can be legally represented as pre-indexed load / store address.
715 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
717 ISD::MemIndexedMode &AM,
718 SelectionDAG &DAG) const {
722 /// getPostIndexedAddressParts - returns true by value, base pointer and
723 /// offset pointer and addressing mode by reference if this node can be
724 /// combined with a load / store to form a post-indexed load / store.
725 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
726 SDValue &Base, SDValue &Offset,
727 ISD::MemIndexedMode &AM,
728 SelectionDAG &DAG) const {
732 /// getJumpTableEncoding - Return the entry encoding for a jump table in the
733 /// current function. The returned value is a member of the
734 /// MachineJumpTableInfo::JTEntryKind enum.
735 virtual unsigned getJumpTableEncoding() const;
737 virtual const MCExpr *
738 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
739 const MachineBasicBlock *MBB, unsigned uid,
740 MCContext &Ctx) const {
741 assert(0 && "Need to implement this hook if target has custom JTIs");
745 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
747 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
748 SelectionDAG &DAG) const;
750 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the
751 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an
753 virtual const MCExpr *
754 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
755 unsigned JTI, MCContext &Ctx) const;
757 /// isOffsetFoldingLegal - Return true if folding a constant offset
758 /// with the given GlobalAddress is legal. It is frequently not legal in
759 /// PIC relocation models.
760 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
762 /// getFunctionAlignment - Return the Log2 alignment of this function.
763 virtual unsigned getFunctionAlignment(const Function *) const = 0;
765 //===--------------------------------------------------------------------===//
766 // TargetLowering Optimization Methods
769 /// TargetLoweringOpt - A convenience struct that encapsulates a DAG, and two
770 /// SDValues for returning information from TargetLowering to its clients
771 /// that want to combine
772 struct TargetLoweringOpt {
778 explicit TargetLoweringOpt(SelectionDAG &InDAG, bool Shrink = false) :
779 DAG(InDAG), ShrinkOps(Shrink) {}
781 bool CombineTo(SDValue O, SDValue N) {
787 /// ShrinkDemandedConstant - Check to see if the specified operand of the
788 /// specified instruction is a constant integer. If so, check to see if
789 /// there are any bits set in the constant that are not demanded. If so,
790 /// shrink the constant and return true.
791 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded);
793 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
794 /// casts are free. This uses isZExtFree and ZERO_EXTEND for the widening
795 /// cast, but it could be generalized for targets with other types of
796 /// implicit widening casts.
797 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
801 /// SimplifyDemandedBits - Look at Op. At this point, we know that only the
802 /// DemandedMask bits of the result of Op are ever used downstream. If we can
803 /// use this information to simplify Op, create a new simplified DAG node and
804 /// return true, returning the original and new nodes in Old and New.
805 /// Otherwise, analyze the expression and return a mask of KnownOne and
806 /// KnownZero bits for the expression (used to simplify the caller).
807 /// The KnownZero/One bits may only be accurate for those bits in the
809 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
810 APInt &KnownZero, APInt &KnownOne,
811 TargetLoweringOpt &TLO, unsigned Depth = 0) const;
813 /// computeMaskedBitsForTargetNode - Determine which of the bits specified in
814 /// Mask are known to be either zero or one and return them in the
815 /// KnownZero/KnownOne bitsets.
816 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
820 const SelectionDAG &DAG,
821 unsigned Depth = 0) const;
823 /// ComputeNumSignBitsForTargetNode - This method can be implemented by
824 /// targets that want to expose additional information about sign bits to the
826 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
827 unsigned Depth = 0) const;
829 struct DAGCombinerInfo {
830 void *DC; // The DAG Combiner object.
832 bool BeforeLegalizeOps;
833 bool CalledByLegalizer;
837 DAGCombinerInfo(SelectionDAG &dag, bool bl, bool blo, bool cl, void *dc)
838 : DC(dc), BeforeLegalize(bl), BeforeLegalizeOps(blo),
839 CalledByLegalizer(cl), DAG(dag) {}
841 bool isBeforeLegalize() const { return BeforeLegalize; }
842 bool isBeforeLegalizeOps() const { return BeforeLegalizeOps; }
843 bool isCalledByLegalizer() const { return CalledByLegalizer; }
845 void AddToWorklist(SDNode *N);
846 SDValue CombineTo(SDNode *N, const std::vector<SDValue> &To,
848 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
849 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
851 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
854 /// SimplifySetCC - Try to simplify a setcc built with the specified operands
855 /// and cc. If it is unable to simplify it, return a null SDValue.
856 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
857 ISD::CondCode Cond, bool foldBooleans,
858 DAGCombinerInfo &DCI, DebugLoc dl) const;
860 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the
861 /// node is a GlobalAddress + offset.
863 isGAPlusOffset(SDNode *N, GlobalValue* &GA, int64_t &Offset) const;
865 /// PerformDAGCombine - This method will be invoked for all target nodes and
866 /// for any target-independent nodes that the target has registered with
869 /// The semantics are as follows:
871 /// SDValue.Val == 0 - No change was made
872 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
873 /// otherwise - N should be replaced by the returned Operand.
875 /// In addition, methods provided by DAGCombinerInfo may be used to perform
876 /// more complex transformations.
878 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
880 //===--------------------------------------------------------------------===//
881 // TargetLowering Configuration Methods - These methods should be invoked by
882 // the derived class constructor to configure this object for the target.
886 /// setShiftAmountType - Describe the type that should be used for shift
887 /// amounts. This type defaults to the pointer type.
888 void setShiftAmountType(MVT VT) { ShiftAmountTy = VT; }
890 /// setBooleanContents - Specify how the target extends the result of a
891 /// boolean value from i1 to a wider type. See getBooleanContents.
892 void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
894 /// setSchedulingPreference - Specify the target scheduling preference.
895 void setSchedulingPreference(SchedPreference Pref) {
896 SchedPreferenceInfo = Pref;
899 /// setUseUnderscoreSetJmp - Indicate whether this target prefers to
900 /// use _setjmp to implement llvm.setjmp or the non _ version.
901 /// Defaults to false.
902 void setUseUnderscoreSetJmp(bool Val) {
903 UseUnderscoreSetJmp = Val;
906 /// setUseUnderscoreLongJmp - Indicate whether this target prefers to
907 /// use _longjmp to implement llvm.longjmp or the non _ version.
908 /// Defaults to false.
909 void setUseUnderscoreLongJmp(bool Val) {
910 UseUnderscoreLongJmp = Val;
913 /// setStackPointerRegisterToSaveRestore - If set to a physical register, this
914 /// specifies the register that llvm.savestack/llvm.restorestack should save
916 void setStackPointerRegisterToSaveRestore(unsigned R) {
917 StackPointerRegisterToSaveRestore = R;
920 /// setExceptionPointerRegister - If set to a physical register, this sets
921 /// the register that receives the exception address on entry to a landing
923 void setExceptionPointerRegister(unsigned R) {
924 ExceptionPointerRegister = R;
927 /// setExceptionSelectorRegister - If set to a physical register, this sets
928 /// the register that receives the exception typeid on entry to a landing
930 void setExceptionSelectorRegister(unsigned R) {
931 ExceptionSelectorRegister = R;
934 /// SelectIsExpensive - Tells the code generator not to expand operations
935 /// into sequences that use the select operations if possible.
936 void setSelectIsExpensive() { SelectIsExpensive = true; }
938 /// setIntDivIsCheap - Tells the code generator that integer divide is
939 /// expensive, and if possible, should be replaced by an alternate sequence
940 /// of instructions not containing an integer divide.
941 void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; }
943 /// setPow2DivIsCheap - Tells the code generator that it shouldn't generate
944 /// srl/add/sra for a signed divide by power of two, and let the target handle
946 void setPow2DivIsCheap(bool isCheap = true) { Pow2DivIsCheap = isCheap; }
948 /// addRegisterClass - Add the specified register class as an available
949 /// regclass for the specified value type. This indicates the selector can
950 /// handle values of that class natively.
951 void addRegisterClass(EVT VT, TargetRegisterClass *RC) {
952 assert((unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
953 AvailableRegClasses.push_back(std::make_pair(VT, RC));
954 RegClassForVT[VT.getSimpleVT().SimpleTy] = RC;
957 /// computeRegisterProperties - Once all of the register classes are added,
958 /// this allows us to compute derived properties we expose.
959 void computeRegisterProperties();
961 /// setOperationAction - Indicate that the specified operation does not work
962 /// with the specified type and indicate what to do about it.
963 void setOperationAction(unsigned Op, MVT VT,
964 LegalizeAction Action) {
965 unsigned I = (unsigned)VT.SimpleTy;
968 OpActions[I][Op] &= ~(uint64_t(3UL) << (J*2));
969 OpActions[I][Op] |= (uint64_t)Action << (J*2);
972 /// setLoadExtAction - Indicate that the specified load with extension does
973 /// not work with the specified type and indicate what to do about it.
974 void setLoadExtAction(unsigned ExtType, MVT VT,
975 LegalizeAction Action) {
976 assert((unsigned)VT.SimpleTy*2 < 63 &&
977 ExtType < array_lengthof(LoadExtActions) &&
978 "Table isn't big enough!");
979 LoadExtActions[ExtType] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
980 LoadExtActions[ExtType] |= (uint64_t)Action << VT.SimpleTy*2;
983 /// setTruncStoreAction - Indicate that the specified truncating store does
984 /// not work with the specified type and indicate what to do about it.
985 void setTruncStoreAction(MVT ValVT, MVT MemVT,
986 LegalizeAction Action) {
987 assert((unsigned)ValVT.SimpleTy < array_lengthof(TruncStoreActions) &&
988 (unsigned)MemVT.SimpleTy*2 < 63 &&
989 "Table isn't big enough!");
990 TruncStoreActions[ValVT.SimpleTy] &= ~(uint64_t(3UL) << MemVT.SimpleTy*2);
991 TruncStoreActions[ValVT.SimpleTy] |= (uint64_t)Action << MemVT.SimpleTy*2;
994 /// setIndexedLoadAction - Indicate that the specified indexed load does or
995 /// does not work with the specified type and indicate what to do abort
996 /// it. NOTE: All indexed mode loads are initialized to Expand in
997 /// TargetLowering.cpp
998 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
999 LegalizeAction Action) {
1000 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1001 IdxMode < array_lengthof(IndexedModeActions[0][0]) &&
1002 "Table isn't big enough!");
1003 IndexedModeActions[(unsigned)VT.SimpleTy][0][IdxMode] = (uint8_t)Action;
1006 /// setIndexedStoreAction - Indicate that the specified indexed store does or
1007 /// does not work with the specified type and indicate what to do about
1008 /// it. NOTE: All indexed mode stores are initialized to Expand in
1009 /// TargetLowering.cpp
1010 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1011 LegalizeAction Action) {
1012 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1013 IdxMode < array_lengthof(IndexedModeActions[0][1] ) &&
1014 "Table isn't big enough!");
1015 IndexedModeActions[(unsigned)VT.SimpleTy][1][IdxMode] = (uint8_t)Action;
1018 /// setCondCodeAction - Indicate that the specified condition code is or isn't
1019 /// supported on the target and indicate what to do about it.
1020 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1021 LegalizeAction Action) {
1022 assert((unsigned)VT.SimpleTy < MVT::LAST_VALUETYPE &&
1023 (unsigned)CC < array_lengthof(CondCodeActions) &&
1024 "Table isn't big enough!");
1025 CondCodeActions[(unsigned)CC] &= ~(uint64_t(3UL) << VT.SimpleTy*2);
1026 CondCodeActions[(unsigned)CC] |= (uint64_t)Action << VT.SimpleTy*2;
1029 /// AddPromotedToType - If Opc/OrigVT is specified as being promoted, the
1030 /// promotion code defaults to trying a larger integer/fp until it can find
1031 /// one that works. If that default is insufficient, this method can be used
1032 /// by the target to override the default.
1033 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1034 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1037 /// setTargetDAGCombine - Targets should invoke this method for each target
1038 /// independent node that they want to provide a custom DAG combiner for by
1039 /// implementing the PerformDAGCombine virtual method.
1040 void setTargetDAGCombine(ISD::NodeType NT) {
1041 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1042 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1045 /// setJumpBufSize - Set the target's required jmp_buf buffer size (in
1046 /// bytes); default is 200
1047 void setJumpBufSize(unsigned Size) {
1051 /// setJumpBufAlignment - Set the target's required jmp_buf buffer
1052 /// alignment (in bytes); default is 0
1053 void setJumpBufAlignment(unsigned Align) {
1054 JumpBufAlignment = Align;
1057 /// setIfCvtBlockSizeLimit - Set the target's if-conversion block size
1058 /// limit (in number of instructions); default is 2.
1059 void setIfCvtBlockSizeLimit(unsigned Limit) {
1060 IfCvtBlockSizeLimit = Limit;
1063 /// setIfCvtDupBlockSizeLimit - Set the target's block size limit (in number
1064 /// of instructions) to be considered for code duplication during
1065 /// if-conversion; default is 2.
1066 void setIfCvtDupBlockSizeLimit(unsigned Limit) {
1067 IfCvtDupBlockSizeLimit = Limit;
1070 /// setPrefLoopAlignment - Set the target's preferred loop alignment. Default
1071 /// alignment is zero, it means the target does not care about loop alignment.
1072 void setPrefLoopAlignment(unsigned Align) {
1073 PrefLoopAlignment = Align;
1078 virtual const TargetSubtarget *getSubtarget() {
1079 assert(0 && "Not Implemented");
1080 return NULL; // this is here to silence compiler errors
1083 //===--------------------------------------------------------------------===//
1084 // Lowering methods - These methods must be implemented by targets so that
1085 // the SelectionDAGLowering code knows how to lower these.
1088 /// LowerFormalArguments - This hook must be implemented to lower the
1089 /// incoming (formal) arguments, described by the Ins array, into the
1090 /// specified DAG. The implementation should fill in the InVals array
1091 /// with legal-type argument values, and return the resulting token
1095 LowerFormalArguments(SDValue Chain,
1096 CallingConv::ID CallConv, bool isVarArg,
1097 const SmallVectorImpl<ISD::InputArg> &Ins,
1098 DebugLoc dl, SelectionDAG &DAG,
1099 SmallVectorImpl<SDValue> &InVals) {
1100 assert(0 && "Not Implemented");
1101 return SDValue(); // this is here to silence compiler errors
1104 /// LowerCallTo - This function lowers an abstract call to a function into an
1105 /// actual call. This returns a pair of operands. The first element is the
1106 /// return value for the function (if RetTy is not VoidTy). The second
1107 /// element is the outgoing token chain. It calls LowerCall to do the actual
1109 struct ArgListEntry {
1120 ArgListEntry() : isSExt(false), isZExt(false), isInReg(false),
1121 isSRet(false), isNest(false), isByVal(false), Alignment(0) { }
1123 typedef std::vector<ArgListEntry> ArgListTy;
1124 std::pair<SDValue, SDValue>
1125 LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
1126 bool isVarArg, bool isInreg, unsigned NumFixedArgs,
1127 CallingConv::ID CallConv, bool isTailCall,
1128 bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
1129 SelectionDAG &DAG, DebugLoc dl);
1131 /// LowerCall - This hook must be implemented to lower calls into the
1132 /// the specified DAG. The outgoing arguments to the call are described
1133 /// by the Outs array, and the values to be returned by the call are
1134 /// described by the Ins array. The implementation should fill in the
1135 /// InVals array with legal-type return values from the call, and return
1136 /// the resulting token chain value.
1138 LowerCall(SDValue Chain, SDValue Callee,
1139 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
1140 const SmallVectorImpl<ISD::OutputArg> &Outs,
1141 const SmallVectorImpl<ISD::InputArg> &Ins,
1142 DebugLoc dl, SelectionDAG &DAG,
1143 SmallVectorImpl<SDValue> &InVals) {
1144 assert(0 && "Not Implemented");
1145 return SDValue(); // this is here to silence compiler errors
1148 /// CanLowerReturn - This hook should be implemented to check whether the
1149 /// return values described by the Outs array can fit into the return
1150 /// registers. If false is returned, an sret-demotion is performed.
1152 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1153 const SmallVectorImpl<EVT> &OutTys,
1154 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1157 // Return true by default to get preexisting behavior.
1160 /// LowerReturn - This hook must be implemented to lower outgoing
1161 /// return values, described by the Outs array, into the specified
1162 /// DAG. The implementation should return the resulting token chain
1166 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1167 const SmallVectorImpl<ISD::OutputArg> &Outs,
1168 DebugLoc dl, SelectionDAG &DAG) {
1169 assert(0 && "Not Implemented");
1170 return SDValue(); // this is here to silence compiler errors
1173 /// EmitTargetCodeForMemcpy - Emit target-specific code that performs a
1174 /// memcpy. This can be used by targets to provide code sequences for cases
1175 /// that don't fit the target's parameters for simple loads/stores and can be
1176 /// more efficient than using a library call. This function can return a null
1177 /// SDValue if the target declines to use custom code and a different
1178 /// lowering strategy should be used.
1180 /// If AlwaysInline is true, the size is constant and the target should not
1181 /// emit any calls and is strongly encouraged to attempt to emit inline code
1182 /// even if it is beyond the usual threshold because this intrinsic is being
1183 /// expanded in a place where calls are not feasible (e.g. within the prologue
1184 /// for another call). If the target chooses to decline an AlwaysInline
1185 /// request here, legalize will resort to using simple loads and stores.
1187 EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
1189 SDValue Op1, SDValue Op2,
1190 SDValue Op3, unsigned Align, bool isVolatile,
1192 const Value *DstSV, uint64_t DstOff,
1193 const Value *SrcSV, uint64_t SrcOff) {
1197 /// EmitTargetCodeForMemmove - Emit target-specific code that performs a
1198 /// memmove. This can be used by targets to provide code sequences for cases
1199 /// that don't fit the target's parameters for simple loads/stores and can be
1200 /// more efficient than using a library call. This function can return a null
1201 /// SDValue if the target declines to use custom code and a different
1202 /// lowering strategy should be used.
1204 EmitTargetCodeForMemmove(SelectionDAG &DAG, DebugLoc dl,
1206 SDValue Op1, SDValue Op2,
1207 SDValue Op3, unsigned Align, bool isVolatile,
1208 const Value *DstSV, uint64_t DstOff,
1209 const Value *SrcSV, uint64_t SrcOff) {
1213 /// EmitTargetCodeForMemset - Emit target-specific code that performs a
1214 /// memset. This can be used by targets to provide code sequences for cases
1215 /// that don't fit the target's parameters for simple stores and can be more
1216 /// efficient than using a library call. This function can return a null
1217 /// SDValue if the target declines to use custom code and a different
1218 /// lowering strategy should be used.
1220 EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
1222 SDValue Op1, SDValue Op2,
1223 SDValue Op3, unsigned Align, bool isVolatile,
1224 const Value *DstSV, uint64_t DstOff) {
1228 /// LowerOperationWrapper - This callback is invoked by the type legalizer
1229 /// to legalize nodes with an illegal operand type but legal result types.
1230 /// It replaces the LowerOperation callback in the type Legalizer.
1231 /// The reason we can not do away with LowerOperation entirely is that
1232 /// LegalizeDAG isn't yet ready to use this callback.
1233 /// TODO: Consider merging with ReplaceNodeResults.
1235 /// The target places new result values for the node in Results (their number
1236 /// and types must exactly match those of the original return values of
1237 /// the node), or leaves Results empty, which indicates that the node is not
1238 /// to be custom lowered after all.
1239 /// The default implementation calls LowerOperation.
1240 virtual void LowerOperationWrapper(SDNode *N,
1241 SmallVectorImpl<SDValue> &Results,
1244 /// LowerOperation - This callback is invoked for operations that are
1245 /// unsupported by the target, which are registered to use 'custom' lowering,
1246 /// and whose defined values are all legal.
1247 /// If the target has no operations that require custom lowering, it need not
1248 /// implement this. The default implementation of this aborts.
1249 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
1251 /// ReplaceNodeResults - This callback is invoked when a node result type is
1252 /// illegal for the target, and the operation was registered to use 'custom'
1253 /// lowering for that result type. The target places new result values for
1254 /// the node in Results (their number and types must exactly match those of
1255 /// the original return values of the node), or leaves Results empty, which
1256 /// indicates that the node is not to be custom lowered after all.
1258 /// If the target has no operations that require custom lowering, it need not
1259 /// implement this. The default implementation aborts.
1260 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
1261 SelectionDAG &DAG) {
1262 assert(0 && "ReplaceNodeResults not implemented for this target!");
1265 /// getTargetNodeName() - This method returns the name of a target specific
1267 virtual const char *getTargetNodeName(unsigned Opcode) const;
1269 /// createFastISel - This method returns a target specific FastISel object,
1270 /// or null if the target does not support "fast" ISel.
1272 createFastISel(MachineFunction &,
1273 MachineModuleInfo *, DwarfWriter *,
1274 DenseMap<const Value *, unsigned> &,
1275 DenseMap<const BasicBlock *, MachineBasicBlock *> &,
1276 DenseMap<const AllocaInst *, int> &
1278 , SmallSet<Instruction*, 8> &CatchInfoLost
1284 //===--------------------------------------------------------------------===//
1285 // Inline Asm Support hooks
1288 /// ExpandInlineAsm - This hook allows the target to expand an inline asm
1289 /// call to be explicit llvm code if it wants to. This is useful for
1290 /// turning simple inline asms into LLVM intrinsics, which gives the
1291 /// compiler more information about the behavior of the code.
1292 virtual bool ExpandInlineAsm(CallInst *CI) const {
1296 enum ConstraintType {
1297 C_Register, // Constraint represents specific register(s).
1298 C_RegisterClass, // Constraint represents any of register(s) in class.
1299 C_Memory, // Memory constraint.
1300 C_Other, // Something else.
1301 C_Unknown // Unsupported constraint.
1304 /// AsmOperandInfo - This contains information for each constraint that we are
1306 struct AsmOperandInfo : public InlineAsm::ConstraintInfo {
1307 /// ConstraintCode - This contains the actual string for the code, like "m".
1308 /// TargetLowering picks the 'best' code from ConstraintInfo::Codes that
1309 /// most closely matches the operand.
1310 std::string ConstraintCode;
1312 /// ConstraintType - Information about the constraint code, e.g. Register,
1313 /// RegisterClass, Memory, Other, Unknown.
1314 TargetLowering::ConstraintType ConstraintType;
1316 /// CallOperandval - If this is the result output operand or a
1317 /// clobber, this is null, otherwise it is the incoming operand to the
1318 /// CallInst. This gets modified as the asm is processed.
1319 Value *CallOperandVal;
1321 /// ConstraintVT - The ValueType for the operand value.
1324 /// isMatchingInputConstraint - Return true of this is an input operand that
1325 /// is a matching constraint like "4".
1326 bool isMatchingInputConstraint() const;
1328 /// getMatchedOperand - If this is an input matching constraint, this method
1329 /// returns the output operand it matches.
1330 unsigned getMatchedOperand() const;
1332 AsmOperandInfo(const InlineAsm::ConstraintInfo &info)
1333 : InlineAsm::ConstraintInfo(info),
1334 ConstraintType(TargetLowering::C_Unknown),
1335 CallOperandVal(0), ConstraintVT(MVT::Other) {
1339 /// ComputeConstraintToUse - Determines the constraint code and constraint
1340 /// type to use for the specific AsmOperandInfo, setting
1341 /// OpInfo.ConstraintCode and OpInfo.ConstraintType. If the actual operand
1342 /// being passed in is available, it can be passed in as Op, otherwise an
1343 /// empty SDValue can be passed. If hasMemory is true it means one of the asm
1344 /// constraint of the inline asm instruction being processed is 'm'.
1345 virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo,
1348 SelectionDAG *DAG = 0) const;
1350 /// getConstraintType - Given a constraint, return the type of constraint it
1351 /// is for this target.
1352 virtual ConstraintType getConstraintType(const std::string &Constraint) const;
1354 /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
1355 /// return a list of registers that can be used to satisfy the constraint.
1356 /// This should only be used for C_RegisterClass constraints.
1357 virtual std::vector<unsigned>
1358 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1361 /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g.
1362 /// {edx}), return the register number and the register class for the
1365 /// Given a register class constraint, like 'r', if this corresponds directly
1366 /// to an LLVM register class, return a register of 0 and the register class
1369 /// This should only be used for C_Register constraints. On error,
1370 /// this returns a register number of 0 and a null register class pointer..
1371 virtual std::pair<unsigned, const TargetRegisterClass*>
1372 getRegForInlineAsmConstraint(const std::string &Constraint,
1375 /// LowerXConstraint - try to replace an X constraint, which matches anything,
1376 /// with another that has more specific requirements based on the type of the
1377 /// corresponding operand. This returns null if there is no replacement to
1379 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
1381 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
1382 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
1383 /// it means one of the asm constraint of the inline asm instruction being
1384 /// processed is 'm'.
1385 virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter,
1387 std::vector<SDValue> &Ops,
1388 SelectionDAG &DAG) const;
1390 //===--------------------------------------------------------------------===//
1391 // Instruction Emitting Hooks
1394 // EmitInstrWithCustomInserter - This method should be implemented by targets
1395 // that mark instructions with the 'usesCustomInserter' flag. These
1396 // instructions are special in various ways, which require special support to
1397 // insert. The specified MachineInstr is created but not inserted into any
1398 // basic blocks, and this method is called to expand it into a sequence of
1399 // instructions, potentially also creating new basic blocks and control flow.
1400 // When new basic blocks are inserted and the edges from MBB to its successors
1401 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the
1403 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
1404 MachineBasicBlock *MBB,
1405 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
1407 //===--------------------------------------------------------------------===//
1408 // Addressing mode description hooks (used by LSR etc).
1411 /// AddrMode - This represents an addressing mode of:
1412 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1413 /// If BaseGV is null, there is no BaseGV.
1414 /// If BaseOffs is zero, there is no base offset.
1415 /// If HasBaseReg is false, there is no base register.
1416 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1420 GlobalValue *BaseGV;
1424 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {}
1427 /// isLegalAddressingMode - Return true if the addressing mode represented by
1428 /// AM is legal for this target, for a load/store of the specified type.
1429 /// The type may be VoidTy, in which case only return true if the addressing
1430 /// mode is legal for a load/store of any legal type.
1431 /// TODO: Handle pre/postinc as well.
1432 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
1434 /// isTruncateFree - Return true if it's free to truncate a value of
1435 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
1436 /// register EAX to i16 by referencing its sub-register AX.
1437 virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
1441 virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
1445 /// isZExtFree - Return true if any actual instruction that defines a
1446 /// value of type Ty1 implicitly zero-extends the value to Ty2 in the result
1447 /// register. This does not necessarily include registers defined in
1448 /// unknown ways, such as incoming arguments, or copies from unknown
1449 /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
1450 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
1451 /// all instructions that define 32-bit values implicit zero-extend the
1452 /// result out to 64 bits.
1453 virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
1457 virtual bool isZExtFree(EVT VT1, EVT VT2) const {
1461 /// isNarrowingProfitable - Return true if it's profitable to narrow
1462 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
1463 /// from i32 to i8 but not from i32 to i16.
1464 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
1468 /// isLegalICmpImmediate - Return true if the specified immediate is legal
1469 /// icmp immediate, that is the target has icmp instructions which can compare
1470 /// a register against the immediate without having to materialize the
1471 /// immediate into a register.
1472 virtual bool isLegalICmpImmediate(int64_t Imm) const {
1476 //===--------------------------------------------------------------------===//
1477 // Div utility functions
1479 SDValue BuildSDIV(SDNode *N, SelectionDAG &DAG,
1480 std::vector<SDNode*>* Created) const;
1481 SDValue BuildUDIV(SDNode *N, SelectionDAG &DAG,
1482 std::vector<SDNode*>* Created) const;
1485 //===--------------------------------------------------------------------===//
1486 // Runtime Library hooks
1489 /// setLibcallName - Rename the default libcall routine name for the specified
1491 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
1492 LibcallRoutineNames[Call] = Name;
1495 /// getLibcallName - Get the libcall routine name for the specified libcall.
1497 const char *getLibcallName(RTLIB::Libcall Call) const {
1498 return LibcallRoutineNames[Call];
1501 /// setCmpLibcallCC - Override the default CondCode to be used to test the
1502 /// result of the comparison libcall against zero.
1503 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
1504 CmpLibcallCCs[Call] = CC;
1507 /// getCmpLibcallCC - Get the CondCode that's to be used to test the result of
1508 /// the comparison libcall against zero.
1509 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
1510 return CmpLibcallCCs[Call];
1513 /// setLibcallCallingConv - Set the CallingConv that should be used for the
1514 /// specified libcall.
1515 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
1516 LibcallCallingConvs[Call] = CC;
1519 /// getLibcallCallingConv - Get the CallingConv that should be used for the
1520 /// specified libcall.
1521 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
1522 return LibcallCallingConvs[Call];
1527 const TargetData *TD;
1528 TargetLoweringObjectFile &TLOF;
1530 /// PointerTy - The type to use for pointers, usually i32 or i64.
1534 /// IsLittleEndian - True if this is a little endian target.
1536 bool IsLittleEndian;
1538 /// SelectIsExpensive - Tells the code generator not to expand operations
1539 /// into sequences that use the select operations if possible.
1540 bool SelectIsExpensive;
1542 /// IntDivIsCheap - Tells the code generator not to expand integer divides by
1543 /// constants into a sequence of muls, adds, and shifts. This is a hack until
1544 /// a real cost model is in place. If we ever optimize for size, this will be
1545 /// set to true unconditionally.
1548 /// Pow2DivIsCheap - Tells the code generator that it shouldn't generate
1549 /// srl/add/sra for a signed divide by power of two, and let the target handle
1551 bool Pow2DivIsCheap;
1553 /// UseUnderscoreSetJmp - This target prefers to use _setjmp to implement
1554 /// llvm.setjmp. Defaults to false.
1555 bool UseUnderscoreSetJmp;
1557 /// UseUnderscoreLongJmp - This target prefers to use _longjmp to implement
1558 /// llvm.longjmp. Defaults to false.
1559 bool UseUnderscoreLongJmp;
1561 /// ShiftAmountTy - The type to use for shift amounts, usually i8 or whatever
1565 /// BooleanContents - Information about the contents of the high-bits in
1566 /// boolean values held in a type wider than i1. See getBooleanContents.
1567 BooleanContent BooleanContents;
1569 /// SchedPreferenceInfo - The target scheduling preference: shortest possible
1570 /// total cycles or lowest register usage.
1571 SchedPreference SchedPreferenceInfo;
1573 /// JumpBufSize - The size, in bytes, of the target's jmp_buf buffers
1574 unsigned JumpBufSize;
1576 /// JumpBufAlignment - The alignment, in bytes, of the target's jmp_buf
1578 unsigned JumpBufAlignment;
1580 /// IfCvtBlockSizeLimit - The maximum allowed size for a block to be
1582 unsigned IfCvtBlockSizeLimit;
1584 /// IfCvtDupBlockSizeLimit - The maximum allowed size for a block to be
1585 /// duplicated during if-conversion.
1586 unsigned IfCvtDupBlockSizeLimit;
1588 /// PrefLoopAlignment - The perferred loop alignment.
1590 unsigned PrefLoopAlignment;
1592 /// StackPointerRegisterToSaveRestore - If set to a physical register, this
1593 /// specifies the register that llvm.savestack/llvm.restorestack should save
1595 unsigned StackPointerRegisterToSaveRestore;
1597 /// ExceptionPointerRegister - If set to a physical register, this specifies
1598 /// the register that receives the exception address on entry to a landing
1600 unsigned ExceptionPointerRegister;
1602 /// ExceptionSelectorRegister - If set to a physical register, this specifies
1603 /// the register that receives the exception typeid on entry to a landing
1605 unsigned ExceptionSelectorRegister;
1607 /// RegClassForVT - This indicates the default register class to use for
1608 /// each ValueType the target supports natively.
1609 TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
1610 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
1611 EVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
1613 /// TransformToType - For any value types we are promoting or expanding, this
1614 /// contains the value type that we are changing to. For Expanded types, this
1615 /// contains one step of the expand (e.g. i64 -> i32), even if there are
1616 /// multiple steps required (e.g. i64 -> i16). For types natively supported
1617 /// by the system, this holds the same type (e.g. i32 -> i32).
1618 EVT TransformToType[MVT::LAST_VALUETYPE];
1620 /// OpActions - For each operation and each value type, keep a LegalizeAction
1621 /// that indicates how instruction selection should deal with the operation.
1622 /// Most operations are Legal (aka, supported natively by the target), but
1623 /// operations that are not should be described. Note that operations on
1624 /// non-legal value types are not described here.
1625 /// This array is accessed using VT.getSimpleVT(), so it is subject to
1626 /// the MVT::MAX_ALLOWED_VALUETYPE * 2 bits.
1627 uint64_t OpActions[MVT::MAX_ALLOWED_VALUETYPE/(sizeof(uint64_t)*4)][ISD::BUILTIN_OP_END];
1629 /// LoadExtActions - For each load of load extension type and each value type,
1630 /// keep a LegalizeAction that indicates how instruction selection should deal
1632 uint64_t LoadExtActions[ISD::LAST_LOADEXT_TYPE];
1634 /// TruncStoreActions - For each truncating store, keep a LegalizeAction that
1635 /// indicates how instruction selection should deal with the store.
1636 uint64_t TruncStoreActions[MVT::LAST_VALUETYPE];
1638 /// IndexedModeActions - For each indexed mode and each value type,
1639 /// keep a pair of LegalizeAction that indicates how instruction
1640 /// selection should deal with the load / store. The first
1641 /// dimension is now the value_type for the reference. The second
1642 /// dimension is the load [0] vs. store[1]. The third dimension
1643 /// represents the various modes for load store.
1644 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][2][ISD::LAST_INDEXED_MODE];
1646 /// CondCodeActions - For each condition code (ISD::CondCode) keep a
1647 /// LegalizeAction that indicates how instruction selection should
1648 /// deal with the condition code.
1649 uint64_t CondCodeActions[ISD::SETCC_INVALID];
1651 ValueTypeActionImpl ValueTypeActions;
1653 std::vector<std::pair<EVT, TargetRegisterClass*> > AvailableRegClasses;
1655 /// TargetDAGCombineArray - Targets can specify ISD nodes that they would
1656 /// like PerformDAGCombine callbacks for by calling setTargetDAGCombine(),
1657 /// which sets a bit in this array.
1659 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
1661 /// PromoteToType - For operations that must be promoted to a specific type,
1662 /// this holds the destination type. This map should be sparse, so don't hold
1665 /// Targets add entries to this map with AddPromotedToType(..), clients access
1666 /// this with getTypeToPromoteTo(..).
1667 std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>
1670 /// LibcallRoutineNames - Stores the name each libcall.
1672 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
1674 /// CmpLibcallCCs - The ISD::CondCode that should be used to test the result
1675 /// of each of the comparison libcall against zero.
1676 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
1678 /// LibcallCallingConvs - Stores the CallingConv that should be used for each
1680 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
1683 /// When lowering \@llvm.memset this field specifies the maximum number of
1684 /// store operations that may be substituted for the call to memset. Targets
1685 /// must set this value based on the cost threshold for that target. Targets
1686 /// should assume that the memset will be done using as many of the largest
1687 /// store operations first, followed by smaller ones, if necessary, per
1688 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
1689 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
1690 /// store. This only applies to setting a constant array of a constant size.
1691 /// @brief Specify maximum number of store instructions per memset call.
1692 unsigned maxStoresPerMemset;
1694 /// When lowering \@llvm.memcpy this field specifies the maximum number of
1695 /// store operations that may be substituted for a call to memcpy. Targets
1696 /// must set this value based on the cost threshold for that target. Targets
1697 /// should assume that the memcpy will be done using as many of the largest
1698 /// store operations first, followed by smaller ones, if necessary, per
1699 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
1700 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
1701 /// and one 1-byte store. This only applies to copying a constant array of
1703 /// @brief Specify maximum bytes of store instructions per memcpy call.
1704 unsigned maxStoresPerMemcpy;
1706 /// When lowering \@llvm.memmove this field specifies the maximum number of
1707 /// store instructions that may be substituted for a call to memmove. Targets
1708 /// must set this value based on the cost threshold for that target. Targets
1709 /// should assume that the memmove will be done using as many of the largest
1710 /// store operations first, followed by smaller ones, if necessary, per
1711 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
1712 /// with 8-bit alignment would result in nine 1-byte stores. This only
1713 /// applies to copying a constant array of constant size.
1714 /// @brief Specify maximum bytes of store instructions per memmove call.
1715 unsigned maxStoresPerMemmove;
1717 /// This field specifies whether the target can benefit from code placement
1719 bool benefitFromCodePlacementOpt;
1721 } // end llvm namespace