1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/Target/TargetInstrItineraries.h"
26 class TargetSubtarget;
27 class TargetInstrInfo;
28 class TargetIntrinsicInfo;
31 class TargetFrameInfo;
32 class MachineCodeEmitter;
34 class ObjectCodeEmitter;
35 class TargetRegisterInfo;
36 class PassManagerBase;
39 class TargetELFWriterInfo;
40 class formatted_raw_ostream;
42 // Relocation model types.
47 PIC_, // Cannot be named PIC due to collision with -DPIC
63 // Code generation optimization level.
64 namespace CodeGenOpt {
73 // Specify if we should encode the LSDA pointer in the FDE as 4- or 8-bytes.
74 namespace DwarfLSDAEncoding {
82 //===----------------------------------------------------------------------===//
84 /// TargetMachine - Primary interface to the complete machine description for
85 /// the target machine. All target-specific information should be accessible
86 /// through this interface.
89 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
90 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
91 protected: // Can only create subclasses.
92 TargetMachine(const Target &);
94 /// getSubtargetImpl - virtual method implemented by subclasses that returns
95 /// a reference to that target's TargetSubtarget-derived member variable.
96 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
98 /// TheTarget - The Target that this machine was created for.
99 const Target &TheTarget;
101 /// AsmInfo - Contains target specific asm information.
103 const MCAsmInfo *AsmInfo;
106 virtual ~TargetMachine();
108 const Target &getTarget() const { return TheTarget; }
110 // Interfaces to the major aspects of target machine information:
111 // -- Instruction opcode and operand information
112 // -- Pipelines and scheduling information
113 // -- Stack frame information
114 // -- Selection DAG lowering information
116 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
117 virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
118 virtual TargetLowering *getTargetLowering() const { return 0; }
119 virtual const TargetData *getTargetData() const { return 0; }
121 /// getMCAsmInfo - Return target specific asm information.
123 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
125 /// getSubtarget - This method returns a pointer to the specified type of
126 /// TargetSubtarget. In debug builds, it verifies that the object being
127 /// returned is of the correct type.
128 template<typename STC> const STC &getSubtarget() const {
129 return *static_cast<const STC*>(getSubtargetImpl());
132 /// getRegisterInfo - If register information is available, return it. If
133 /// not, return null. This is kept separate from RegInfo until RegInfo has
134 /// details of graph coloring register allocation removed from it.
136 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
138 /// getIntrinsicInfo - If intrinsic information is available, return it. If
139 /// not, return null.
141 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
143 /// getJITInfo - If this target supports a JIT, return information for it,
144 /// otherwise return null.
146 virtual TargetJITInfo *getJITInfo() { return 0; }
148 /// getInstrItineraryData - Returns instruction itinerary data for the target
149 /// or specific subtarget.
151 virtual const InstrItineraryData getInstrItineraryData() const {
152 return InstrItineraryData();
155 /// getELFWriterInfo - If this target supports an ELF writer, return
156 /// information for it, otherwise return null.
158 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
160 /// getRelocationModel - Returns the code generation relocation model. The
161 /// choices are static, PIC, and dynamic-no-pic, and target default.
162 static Reloc::Model getRelocationModel();
164 /// setRelocationModel - Sets the code generation relocation model.
166 static void setRelocationModel(Reloc::Model Model);
168 /// getCodeModel - Returns the code model. The choices are small, kernel,
169 /// medium, large, and target default.
170 static CodeModel::Model getCodeModel();
172 /// setCodeModel - Sets the code model.
174 static void setCodeModel(CodeModel::Model Model);
176 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
178 static bool getAsmVerbosityDefault();
180 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
182 static void setAsmVerbosityDefault(bool);
184 /// getLSDAEncoding - Returns the LSDA pointer encoding. The choices are
185 /// 4-byte, 8-byte, and target default. The CIE is hard-coded to indicate that
186 /// the LSDA pointer in the FDE section is an "sdata4", and should be encoded
187 /// as a 4-byte pointer by default. However, some systems may require a
188 /// different size due to bugs or other conditions. We will default to a
189 /// 4-byte encoding unless the system tells us otherwise.
191 /// FIXME: This call-back isn't good! We should be using the correct encoding
192 /// regardless of the system. However, there are some systems which have bugs
193 /// that prevent this from occuring.
194 virtual DwarfLSDAEncoding::Encoding getLSDAEncoding() const {
195 return DwarfLSDAEncoding::Default;
198 /// CodeGenFileType - These enums are meant to be passed into
199 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
200 /// it to indicate what type of file could actually be made.
201 enum CodeGenFileType {
208 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
209 /// on this target. User flag overrides.
210 virtual bool getEnableTailMergeDefault() const { return true; }
212 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
213 /// specified file emitted. Typically this will involve several steps of code
215 /// This method should return InvalidFile if emission of this file type
216 /// is not supported.
218 virtual CodeGenFileType addPassesToEmitFile(PassManagerBase &,
219 formatted_raw_ostream &,
220 CodeGenFileType Filetype,
222 return CGFT_ErrorOccurred;
225 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
226 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
227 /// actually outputting the machine code and resolving things like the address
228 /// of functions. This method returns true if machine code emission is
231 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
237 /// addPassesToEmitWholeFile - This method can be implemented by targets that
238 /// require having the entire module at once. This is not recommended, do not
240 virtual bool WantsWholeFile() const { return false; }
241 virtual bool addPassesToEmitWholeFile(PassManager &, formatted_raw_ostream &,
248 /// LLVMTargetMachine - This class describes a target machine that is
249 /// implemented with the LLVM target-independent code generator.
251 class LLVMTargetMachine : public TargetMachine {
252 protected: // Can only create subclasses.
253 LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
255 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
256 /// both emitting to assembly files or machine code output.
258 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level);
261 virtual void setCodeModelForJIT();
262 virtual void setCodeModelForStatic();
266 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
267 /// specified file emitted. Typically this will involve several steps of code
268 /// generation. If OptLevel is None, the code generator should emit code as
269 /// fast as possible, though the generated code may be less efficient. This
270 /// method should return CGFT_ErrorOccurred if emission of this file type is
273 /// The default implementation of this method adds components from the
274 /// LLVM retargetable code generator, invoking the methods below to get
275 /// target-specific passes in standard locations.
277 virtual CodeGenFileType addPassesToEmitFile(PassManagerBase &PM,
278 formatted_raw_ostream &Out,
279 CodeGenFileType FileType,
282 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
283 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
284 /// actually outputting the machine code and resolving things like the address
285 /// of functions. This method returns true if machine code emission is
288 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
292 /// Target-Independent Code Generator Pass Configuration Options.
294 /// addInstSelector - This method should add any "last minute" LLVM->LLVM
295 /// passes, then install an instruction selector pass, which converts from
296 /// LLVM code to machine instructions.
297 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
301 /// addPreRegAlloc - This method may be implemented by targets that want to
302 /// run passes immediately before register allocation. This should return
303 /// true if -print-machineinstrs should print after these passes.
304 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
308 /// addPostRegAlloc - This method may be implemented by targets that want
309 /// to run passes after register allocation but before prolog-epilog
310 /// insertion. This should return true if -print-machineinstrs should print
311 /// after these passes.
312 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
316 /// addPreSched2 - This method may be implemented by targets that want to
317 /// run passes after prolog-epilog insertion and before the second instruction
318 /// scheduling pass. This should return true if -print-machineinstrs should
319 /// print after these passes.
320 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
324 /// addPreEmitPass - This pass may be implemented by targets that want to run
325 /// passes immediately before machine code is emitted. This should return
326 /// true if -print-machineinstrs should print out the code after the passes.
327 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
332 /// addCodeEmitter - This pass should be overridden by the target to add a
333 /// code emitter, if supported. If this is not supported, 'true' should be
335 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
340 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
341 /// on this target. User flag overrides.
342 virtual bool getEnableTailMergeDefault() const { return true; }
345 } // End llvm namespace