1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/Target/TargetInstrItineraries.h"
26 class TargetSubtarget;
27 class TargetInstrInfo;
28 class TargetIntrinsicInfo;
31 class TargetSelectionDAGInfo;
32 class TargetFrameInfo;
35 class TargetRegisterInfo;
36 class PassManagerBase;
39 class TargetELFWriterInfo;
40 class formatted_raw_ostream;
42 // Relocation model types.
47 PIC_, // Cannot be named PIC due to collision with -DPIC
63 // Code generation optimization level.
64 namespace CodeGenOpt {
75 None, // No preference
76 Latency, // Scheduling for shortest total latency.
77 RegPressure, // Scheduling for lowest register pressure.
78 Hybrid // Scheduling for both latency and register pressure.
82 //===----------------------------------------------------------------------===//
84 /// TargetMachine - Primary interface to the complete machine description for
85 /// the target machine. All target-specific information should be accessible
86 /// through this interface.
89 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
90 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
91 protected: // Can only create subclasses.
92 TargetMachine(const Target &);
94 /// getSubtargetImpl - virtual method implemented by subclasses that returns
95 /// a reference to that target's TargetSubtarget-derived member variable.
96 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
98 /// TheTarget - The Target that this machine was created for.
99 const Target &TheTarget;
101 /// AsmInfo - Contains target specific asm information.
103 const MCAsmInfo *AsmInfo;
105 unsigned MCRelaxAll : 1;
108 virtual ~TargetMachine();
110 const Target &getTarget() const { return TheTarget; }
112 // Interfaces to the major aspects of target machine information:
113 // -- Instruction opcode and operand information
114 // -- Pipelines and scheduling information
115 // -- Stack frame information
116 // -- Selection DAG lowering information
118 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
119 virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
120 virtual const TargetLowering *getTargetLowering() const { return 0; }
121 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
122 virtual const TargetData *getTargetData() const { return 0; }
124 /// getMCAsmInfo - Return target specific asm information.
126 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
128 /// getSubtarget - This method returns a pointer to the specified type of
129 /// TargetSubtarget. In debug builds, it verifies that the object being
130 /// returned is of the correct type.
131 template<typename STC> const STC &getSubtarget() const {
132 return *static_cast<const STC*>(getSubtargetImpl());
135 /// getRegisterInfo - If register information is available, return it. If
136 /// not, return null. This is kept separate from RegInfo until RegInfo has
137 /// details of graph coloring register allocation removed from it.
139 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
141 /// getIntrinsicInfo - If intrinsic information is available, return it. If
142 /// not, return null.
144 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
146 /// getJITInfo - If this target supports a JIT, return information for it,
147 /// otherwise return null.
149 virtual TargetJITInfo *getJITInfo() { return 0; }
151 /// getInstrItineraryData - Returns instruction itinerary data for the target
152 /// or specific subtarget.
154 virtual const InstrItineraryData getInstrItineraryData() const {
155 return InstrItineraryData();
158 /// getELFWriterInfo - If this target supports an ELF writer, return
159 /// information for it, otherwise return null.
161 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
163 /// hasMCRelaxAll - Check whether all machine code instructions should be
165 bool hasMCRelaxAll() const { return MCRelaxAll; }
167 /// setMCRelaxAll - Set whether all machine code instructions should be
169 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
171 /// getRelocationModel - Returns the code generation relocation model. The
172 /// choices are static, PIC, and dynamic-no-pic, and target default.
173 static Reloc::Model getRelocationModel();
175 /// setRelocationModel - Sets the code generation relocation model.
177 static void setRelocationModel(Reloc::Model Model);
179 /// getCodeModel - Returns the code model. The choices are small, kernel,
180 /// medium, large, and target default.
181 static CodeModel::Model getCodeModel();
183 /// setCodeModel - Sets the code model.
185 static void setCodeModel(CodeModel::Model Model);
187 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
189 static bool getAsmVerbosityDefault();
191 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
193 static void setAsmVerbosityDefault(bool);
195 /// getDataSections - Return true if data objects should be emitted into their
196 /// own section, corresponds to -fdata-sections.
197 static bool getDataSections();
199 /// getFunctionSections - Return true if functions should be emitted into
200 /// their own section, corresponding to -ffunction-sections.
201 static bool getFunctionSections();
203 /// setDataSections - Set if the data are emit into separate sections.
204 static void setDataSections(bool);
206 /// setFunctionSections - Set if the functions are emit into separate
208 static void setFunctionSections(bool);
210 /// CodeGenFileType - These enums are meant to be passed into
211 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
212 /// it to indicate what type of file could actually be made.
213 enum CodeGenFileType {
216 CGFT_Null // Do not emit any output.
219 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
220 /// on this target. User flag overrides.
221 virtual bool getEnableTailMergeDefault() const { return true; }
223 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
224 /// specified file emitted. Typically this will involve several steps of code
225 /// generation. This method should return true if emission of this file type
226 /// is not supported, or false on success.
227 virtual bool addPassesToEmitFile(PassManagerBase &,
228 formatted_raw_ostream &,
235 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
236 /// get machine code emitted. This uses a JITCodeEmitter object to handle
237 /// actually outputting the machine code and resolving things like the address
238 /// of functions. This method returns true if machine code emission is
241 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
249 /// LLVMTargetMachine - This class describes a target machine that is
250 /// implemented with the LLVM target-independent code generator.
252 class LLVMTargetMachine : public TargetMachine {
253 std::string TargetTriple;
255 protected: // Can only create subclasses.
256 LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
259 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
260 /// both emitting to assembly files or machine code output.
262 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
263 bool DisableVerify, MCContext *&OutCtx);
265 virtual void setCodeModelForJIT();
266 virtual void setCodeModelForStatic();
270 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
271 /// specified file emitted. Typically this will involve several steps of code
272 /// generation. If OptLevel is None, the code generator should emit code as
273 /// fast as possible, though the generated code may be less efficient.
274 virtual bool addPassesToEmitFile(PassManagerBase &PM,
275 formatted_raw_ostream &Out,
276 CodeGenFileType FileType,
278 bool DisableVerify = true);
280 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
281 /// get machine code emitted. This uses a JITCodeEmitter object to handle
282 /// actually outputting the machine code and resolving things like the address
283 /// of functions. This method returns true if machine code emission is
286 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
289 bool DisableVerify = true);
291 /// Target-Independent Code Generator Pass Configuration Options.
293 /// addInstSelector - This method should add any "last minute" LLVM->LLVM
294 /// passes, then install an instruction selector pass, which converts from
295 /// LLVM code to machine instructions.
296 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
300 /// addPreRegAlloc - This method may be implemented by targets that want to
301 /// run passes immediately before register allocation. This should return
302 /// true if -print-machineinstrs should print after these passes.
303 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
307 /// addPostRegAlloc - This method may be implemented by targets that want
308 /// to run passes after register allocation but before prolog-epilog
309 /// insertion. This should return true if -print-machineinstrs should print
310 /// after these passes.
311 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
315 /// addPreSched2 - This method may be implemented by targets that want to
316 /// run passes after prolog-epilog insertion and before the second instruction
317 /// scheduling pass. This should return true if -print-machineinstrs should
318 /// print after these passes.
319 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
323 /// addPreEmitPass - This pass may be implemented by targets that want to run
324 /// passes immediately before machine code is emitted. This should return
325 /// true if -print-machineinstrs should print out the code after the passes.
326 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
331 /// addCodeEmitter - This pass should be overridden by the target to add a
332 /// code emitter, if supported. If this is not supported, 'true' should be
334 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
339 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
340 /// on this target. User flag overrides.
341 virtual bool getEnableTailMergeDefault() const { return true; }
344 } // End llvm namespace