1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/Target/TargetInstrItineraries.h"
26 class TargetSubtarget;
27 class TargetInstrInfo;
28 class TargetIntrinsicInfo;
31 class TargetSelectionDAGInfo;
32 class TargetFrameInfo;
35 class TargetRegisterInfo;
36 class PassManagerBase;
39 class TargetELFWriterInfo;
40 class formatted_raw_ostream;
42 // Relocation model types.
47 PIC_, // Cannot be named PIC due to collision with -DPIC
63 // Code generation optimization level.
64 namespace CodeGenOpt {
75 None, // No preference
76 Latency, // Scheduling for shortest total latency.
77 RegPressure, // Scheduling for lowest register pressure.
78 Hybrid, // Scheduling for both latency and register pressure.
79 ILP // Scheduling for ILP in low register pressure mode.
83 //===----------------------------------------------------------------------===//
85 /// TargetMachine - Primary interface to the complete machine description for
86 /// the target machine. All target-specific information should be accessible
87 /// through this interface.
90 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
91 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
92 protected: // Can only create subclasses.
93 TargetMachine(const Target &);
95 /// getSubtargetImpl - virtual method implemented by subclasses that returns
96 /// a reference to that target's TargetSubtarget-derived member variable.
97 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
99 /// TheTarget - The Target that this machine was created for.
100 const Target &TheTarget;
102 /// AsmInfo - Contains target specific asm information.
104 const MCAsmInfo *AsmInfo;
106 unsigned MCRelaxAll : 1;
109 virtual ~TargetMachine();
111 const Target &getTarget() const { return TheTarget; }
113 // Interfaces to the major aspects of target machine information:
114 // -- Instruction opcode and operand information
115 // -- Pipelines and scheduling information
116 // -- Stack frame information
117 // -- Selection DAG lowering information
119 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
120 virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
121 virtual const TargetLowering *getTargetLowering() const { return 0; }
122 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
123 virtual const TargetData *getTargetData() const { return 0; }
125 /// getMCAsmInfo - Return target specific asm information.
127 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
129 /// getSubtarget - This method returns a pointer to the specified type of
130 /// TargetSubtarget. In debug builds, it verifies that the object being
131 /// returned is of the correct type.
132 template<typename STC> const STC &getSubtarget() const {
133 return *static_cast<const STC*>(getSubtargetImpl());
136 /// getRegisterInfo - If register information is available, return it. If
137 /// not, return null. This is kept separate from RegInfo until RegInfo has
138 /// details of graph coloring register allocation removed from it.
140 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
142 /// getIntrinsicInfo - If intrinsic information is available, return it. If
143 /// not, return null.
145 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
147 /// getJITInfo - If this target supports a JIT, return information for it,
148 /// otherwise return null.
150 virtual TargetJITInfo *getJITInfo() { return 0; }
152 /// getInstrItineraryData - Returns instruction itinerary data for the target
153 /// or specific subtarget.
155 virtual const InstrItineraryData getInstrItineraryData() const {
156 return InstrItineraryData();
159 /// getELFWriterInfo - If this target supports an ELF writer, return
160 /// information for it, otherwise return null.
162 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
164 /// hasMCRelaxAll - Check whether all machine code instructions should be
166 bool hasMCRelaxAll() const { return MCRelaxAll; }
168 /// setMCRelaxAll - Set whether all machine code instructions should be
170 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
172 /// getRelocationModel - Returns the code generation relocation model. The
173 /// choices are static, PIC, and dynamic-no-pic, and target default.
174 static Reloc::Model getRelocationModel();
176 /// setRelocationModel - Sets the code generation relocation model.
178 static void setRelocationModel(Reloc::Model Model);
180 /// getCodeModel - Returns the code model. The choices are small, kernel,
181 /// medium, large, and target default.
182 static CodeModel::Model getCodeModel();
184 /// setCodeModel - Sets the code model.
186 static void setCodeModel(CodeModel::Model Model);
188 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
190 static bool getAsmVerbosityDefault();
192 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
194 static void setAsmVerbosityDefault(bool);
196 /// getDataSections - Return true if data objects should be emitted into their
197 /// own section, corresponds to -fdata-sections.
198 static bool getDataSections();
200 /// getFunctionSections - Return true if functions should be emitted into
201 /// their own section, corresponding to -ffunction-sections.
202 static bool getFunctionSections();
204 /// setDataSections - Set if the data are emit into separate sections.
205 static void setDataSections(bool);
207 /// setFunctionSections - Set if the functions are emit into separate
209 static void setFunctionSections(bool);
211 /// CodeGenFileType - These enums are meant to be passed into
212 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
213 /// it to indicate what type of file could actually be made.
214 enum CodeGenFileType {
217 CGFT_Null // Do not emit any output.
220 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
221 /// on this target. User flag overrides.
222 virtual bool getEnableTailMergeDefault() const { return true; }
224 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
225 /// specified file emitted. Typically this will involve several steps of code
226 /// generation. This method should return true if emission of this file type
227 /// is not supported, or false on success.
228 virtual bool addPassesToEmitFile(PassManagerBase &,
229 formatted_raw_ostream &,
236 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
237 /// get machine code emitted. This uses a JITCodeEmitter object to handle
238 /// actually outputting the machine code and resolving things like the address
239 /// of functions. This method returns true if machine code emission is
242 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
249 /// addPassesToEmitMC - Add passes to the specified pass manager to get
250 /// machine code emitted with the MCJIT. This method returns true if machine
251 /// code is not supported. It fills the MCContext Ctx pointer which can be
252 /// used to build custom MCStreamer.
254 virtual bool addPassesToEmitMC(PassManagerBase &,
262 /// LLVMTargetMachine - This class describes a target machine that is
263 /// implemented with the LLVM target-independent code generator.
265 class LLVMTargetMachine : public TargetMachine {
266 std::string TargetTriple;
268 protected: // Can only create subclasses.
269 LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
272 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
273 /// both emitting to assembly files or machine code output.
275 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
276 bool DisableVerify, MCContext *&OutCtx);
278 virtual void setCodeModelForJIT();
279 virtual void setCodeModelForStatic();
283 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
284 /// specified file emitted. Typically this will involve several steps of code
285 /// generation. If OptLevel is None, the code generator should emit code as
286 /// fast as possible, though the generated code may be less efficient.
287 virtual bool addPassesToEmitFile(PassManagerBase &PM,
288 formatted_raw_ostream &Out,
289 CodeGenFileType FileType,
291 bool DisableVerify = true);
293 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
294 /// get machine code emitted. This uses a JITCodeEmitter object to handle
295 /// actually outputting the machine code and resolving things like the address
296 /// of functions. This method returns true if machine code emission is
299 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
302 bool DisableVerify = true);
304 /// addPassesToEmitMC - Add passes to the specified pass manager to get
305 /// machine code emitted with the MCJIT. This method returns true if machine
306 /// code is not supported. It fills the MCContext Ctx pointer which can be
307 /// used to build custom MCStreamer.
309 virtual bool addPassesToEmitMC(PassManagerBase &PM,
311 CodeGenOpt::Level OptLevel,
312 bool DisableVerify = true);
314 /// Target-Independent Code Generator Pass Configuration Options.
316 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
317 /// passes (which are run just before instruction selector).
318 virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
322 /// addInstSelector - This method should install an instruction selector pass,
323 /// which converts from LLVM code to machine instructions.
324 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
328 /// addPreRegAlloc - This method may be implemented by targets that want to
329 /// run passes immediately before register allocation. This should return
330 /// true if -print-machineinstrs should print after these passes.
331 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
335 /// addPostRegAlloc - This method may be implemented by targets that want
336 /// to run passes after register allocation but before prolog-epilog
337 /// insertion. This should return true if -print-machineinstrs should print
338 /// after these passes.
339 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
343 /// addPreSched2 - This method may be implemented by targets that want to
344 /// run passes after prolog-epilog insertion and before the second instruction
345 /// scheduling pass. This should return true if -print-machineinstrs should
346 /// print after these passes.
347 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
351 /// addPreEmitPass - This pass may be implemented by targets that want to run
352 /// passes immediately before machine code is emitted. This should return
353 /// true if -print-machineinstrs should print out the code after the passes.
354 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
359 /// addCodeEmitter - This pass should be overridden by the target to add a
360 /// code emitter, if supported. If this is not supported, 'true' should be
362 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
367 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
368 /// on this target. User flag overrides.
369 virtual bool getEnableTailMergeDefault() const { return true; }
372 } // End llvm namespace