1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/MC/MCCodeGenInfo.h"
18 #include "llvm/ADT/StringRef.h"
24 class InstrItineraryData;
31 class PassManagerBase;
34 class TargetELFWriterInfo;
35 class TargetFrameLowering;
36 class TargetInstrInfo;
37 class TargetIntrinsicInfo;
40 class TargetRegisterInfo;
41 class TargetSelectionDAGInfo;
42 class TargetSubtargetInfo;
43 class formatted_raw_ostream;
48 None, // No preference
49 RegPressure, // Scheduling for lowest register pressure.
50 Hybrid, // Scheduling for both latency and register pressure.
51 ILP // Scheduling for ILP in low register pressure mode.
55 //===----------------------------------------------------------------------===//
57 /// TargetMachine - Primary interface to the complete machine description for
58 /// the target machine. All target-specific information should be accessible
59 /// through this interface.
62 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
63 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
64 protected: // Can only create subclasses.
65 TargetMachine(const Target &T, StringRef TargetTriple,
66 StringRef CPU, StringRef FS);
68 /// getSubtargetImpl - virtual method implemented by subclasses that returns
69 /// a reference to that target's TargetSubtargetInfo-derived member variable.
70 virtual const TargetSubtargetInfo *getSubtargetImpl() const { return 0; }
72 /// TheTarget - The Target that this machine was created for.
73 const Target &TheTarget;
75 /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target
76 /// feature strings the TargetMachine instance is created with.
77 std::string TargetTriple;
78 std::string TargetCPU;
81 /// CodeGenInfo - Low level target information such as relocation model.
82 const MCCodeGenInfo *CodeGenInfo;
84 /// AsmInfo - Contains target specific asm information.
86 const MCAsmInfo *AsmInfo;
88 unsigned MCRelaxAll : 1;
89 unsigned MCNoExecStack : 1;
90 unsigned MCSaveTempLabels : 1;
91 unsigned MCUseLoc : 1;
92 unsigned MCUseCFI : 1;
93 unsigned MCUseDwarfDirectory : 1;
96 virtual ~TargetMachine();
98 const Target &getTarget() const { return TheTarget; }
100 const StringRef getTargetTriple() const { return TargetTriple; }
101 const StringRef getTargetCPU() const { return TargetCPU; }
102 const StringRef getTargetFeatureString() const { return TargetFS; }
104 // Interfaces to the major aspects of target machine information:
105 // -- Instruction opcode and operand information
106 // -- Pipelines and scheduling information
107 // -- Stack frame information
108 // -- Selection DAG lowering information
110 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
111 virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
112 virtual const TargetLowering *getTargetLowering() const { return 0; }
113 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
114 virtual const TargetData *getTargetData() const { return 0; }
116 /// getMCAsmInfo - Return target specific asm information.
118 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
120 /// getSubtarget - This method returns a pointer to the specified type of
121 /// TargetSubtargetInfo. In debug builds, it verifies that the object being
122 /// returned is of the correct type.
123 template<typename STC> const STC &getSubtarget() const {
124 return *static_cast<const STC*>(getSubtargetImpl());
127 /// getRegisterInfo - If register information is available, return it. If
128 /// not, return null. This is kept separate from RegInfo until RegInfo has
129 /// details of graph coloring register allocation removed from it.
131 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
133 /// getIntrinsicInfo - If intrinsic information is available, return it. If
134 /// not, return null.
136 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
138 /// getJITInfo - If this target supports a JIT, return information for it,
139 /// otherwise return null.
141 virtual TargetJITInfo *getJITInfo() { return 0; }
143 /// getInstrItineraryData - Returns instruction itinerary data for the target
144 /// or specific subtarget.
146 virtual const InstrItineraryData *getInstrItineraryData() const {
150 /// getELFWriterInfo - If this target supports an ELF writer, return
151 /// information for it, otherwise return null.
153 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
155 /// hasMCRelaxAll - Check whether all machine code instructions should be
157 bool hasMCRelaxAll() const { return MCRelaxAll; }
159 /// setMCRelaxAll - Set whether all machine code instructions should be
161 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
163 /// hasMCSaveTempLabels - Check whether temporary labels will be preserved
164 /// (i.e., not treated as temporary).
165 bool hasMCSaveTempLabels() const { return MCSaveTempLabels; }
167 /// setMCSaveTempLabels - Set whether temporary labels will be preserved
168 /// (i.e., not treated as temporary).
169 void setMCSaveTempLabels(bool Value) { MCSaveTempLabels = Value; }
171 /// hasMCNoExecStack - Check whether an executable stack is not needed.
172 bool hasMCNoExecStack() const { return MCNoExecStack; }
174 /// setMCNoExecStack - Set whether an executabel stack is not needed.
175 void setMCNoExecStack(bool Value) { MCNoExecStack = Value; }
177 /// hasMCUseLoc - Check whether we should use dwarf's .loc directive.
178 bool hasMCUseLoc() const { return MCUseLoc; }
180 /// setMCUseLoc - Set whether all we should use dwarf's .loc directive.
181 void setMCUseLoc(bool Value) { MCUseLoc = Value; }
183 /// hasMCUseCFI - Check whether we should use dwarf's .cfi_* directives.
184 bool hasMCUseCFI() const { return MCUseCFI; }
186 /// setMCUseCFI - Set whether all we should use dwarf's .cfi_* directives.
187 void setMCUseCFI(bool Value) { MCUseCFI = Value; }
189 /// hasMCUseDwarfDirectory - Check whether we should use .file directives with
190 /// explicit directories.
191 bool hasMCUseDwarfDirectory() const { return MCUseDwarfDirectory; }
193 /// setMCUseDwarfDirectory - Set whether all we should use .file directives
194 /// with explicit directories.
195 void setMCUseDwarfDirectory(bool Value) { MCUseDwarfDirectory = Value; }
197 /// getRelocationModel - Returns the code generation relocation model. The
198 /// choices are static, PIC, and dynamic-no-pic, and target default.
199 Reloc::Model getRelocationModel() const;
201 /// getCodeModel - Returns the code model. The choices are small, kernel,
202 /// medium, large, and target default.
203 CodeModel::Model getCodeModel() const;
205 /// getOptLevel - Returns the optimization level: None, Less,
206 /// Default, or Aggressive.
207 CodeGenOpt::Level getOptLevel() const;
209 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
211 static bool getAsmVerbosityDefault();
213 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
215 static void setAsmVerbosityDefault(bool);
217 /// getDataSections - Return true if data objects should be emitted into their
218 /// own section, corresponds to -fdata-sections.
219 static bool getDataSections();
221 /// getFunctionSections - Return true if functions should be emitted into
222 /// their own section, corresponding to -ffunction-sections.
223 static bool getFunctionSections();
225 /// setDataSections - Set if the data are emit into separate sections.
226 static void setDataSections(bool);
228 /// setFunctionSections - Set if the functions are emit into separate
230 static void setFunctionSections(bool);
232 /// CodeGenFileType - These enums are meant to be passed into
233 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
234 /// it to indicate what type of file could actually be made.
235 enum CodeGenFileType {
238 CGFT_Null // Do not emit any output.
241 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
242 /// on this target. User flag overrides.
243 virtual bool getEnableTailMergeDefault() const { return true; }
245 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
246 /// specified file emitted. Typically this will involve several steps of code
247 /// generation. This method should return true if emission of this file type
248 /// is not supported, or false on success.
249 virtual bool addPassesToEmitFile(PassManagerBase &,
250 formatted_raw_ostream &,
252 bool /*DisableVerify*/ = true) {
256 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
257 /// get machine code emitted. This uses a JITCodeEmitter object to handle
258 /// actually outputting the machine code and resolving things like the address
259 /// of functions. This method returns true if machine code emission is
262 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
264 bool /*DisableVerify*/ = true) {
268 /// addPassesToEmitMC - Add passes to the specified pass manager to get
269 /// machine code emitted with the MCJIT. This method returns true if machine
270 /// code is not supported. It fills the MCContext Ctx pointer which can be
271 /// used to build custom MCStreamer.
273 virtual bool addPassesToEmitMC(PassManagerBase &,
276 bool /*DisableVerify*/ = true) {
281 /// LLVMTargetMachine - This class describes a target machine that is
282 /// implemented with the LLVM target-independent code generator.
284 class LLVMTargetMachine : public TargetMachine {
285 protected: // Can only create subclasses.
286 LLVMTargetMachine(const Target &T, StringRef TargetTriple,
287 StringRef CPU, StringRef FS,
288 Reloc::Model RM, CodeModel::Model CM,
289 CodeGenOpt::Level OL);
292 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
293 /// both emitting to assembly files or machine code output.
295 bool addCommonCodeGenPasses(PassManagerBase &,
296 bool DisableVerify, MCContext *&OutCtx);
299 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
300 /// specified file emitted. Typically this will involve several steps of code
302 virtual bool addPassesToEmitFile(PassManagerBase &PM,
303 formatted_raw_ostream &Out,
304 CodeGenFileType FileType,
305 bool DisableVerify = true);
307 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
308 /// get machine code emitted. This uses a JITCodeEmitter object to handle
309 /// actually outputting the machine code and resolving things like the address
310 /// of functions. This method returns true if machine code emission is
313 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
315 bool DisableVerify = true);
317 /// addPassesToEmitMC - Add passes to the specified pass manager to get
318 /// machine code emitted with the MCJIT. This method returns true if machine
319 /// code is not supported. It fills the MCContext Ctx pointer which can be
320 /// used to build custom MCStreamer.
322 virtual bool addPassesToEmitMC(PassManagerBase &PM,
325 bool DisableVerify = true);
327 /// Target-Independent Code Generator Pass Configuration Options.
329 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
330 /// passes (which are run just before instruction selector).
331 virtual bool addPreISel(PassManagerBase &) {
335 /// addInstSelector - This method should install an instruction selector pass,
336 /// which converts from LLVM code to machine instructions.
337 virtual bool addInstSelector(PassManagerBase &) {
341 /// addPreRegAlloc - This method may be implemented by targets that want to
342 /// run passes immediately before register allocation. This should return
343 /// true if -print-machineinstrs should print after these passes.
344 virtual bool addPreRegAlloc(PassManagerBase &) {
348 /// addPostRegAlloc - This method may be implemented by targets that want
349 /// to run passes after register allocation but before prolog-epilog
350 /// insertion. This should return true if -print-machineinstrs should print
351 /// after these passes.
352 virtual bool addPostRegAlloc(PassManagerBase &) {
356 /// addPreSched2 - This method may be implemented by targets that want to
357 /// run passes after prolog-epilog insertion and before the second instruction
358 /// scheduling pass. This should return true if -print-machineinstrs should
359 /// print after these passes.
360 virtual bool addPreSched2(PassManagerBase &) {
364 /// addPreEmitPass - This pass may be implemented by targets that want to run
365 /// passes immediately before machine code is emitted. This should return
366 /// true if -print-machineinstrs should print out the code after the passes.
367 virtual bool addPreEmitPass(PassManagerBase &) {
372 /// addCodeEmitter - This pass should be overridden by the target to add a
373 /// code emitter, if supported. If this is not supported, 'true' should be
375 virtual bool addCodeEmitter(PassManagerBase &,
380 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
381 /// on this target. User flag overrides.
382 virtual bool getEnableTailMergeDefault() const { return true; }
385 } // End llvm namespace