1 //===-- llvm/Target/TargetMachine.h - General Target Information -*- C++ -*-==//
3 // This file describes the general parts of a Target machine.
5 //===----------------------------------------------------------------------===//
7 #ifndef LLVM_TARGET_TARGETMACHINE_H
8 #define LLVM_TARGET_TARGETMACHINE_H
10 #include "llvm/Target/TargetData.h"
11 #include "Support/NonCopyable.h"
13 class TargetInstrInfo;
14 class TargetInstrDescriptor;
15 class TargetSchedInfo;
17 class TargetFrameInfo;
18 class TargetCacheInfo;
20 class MachineCodeEmitter;
25 //===----------------------------------------------------------------------===//
27 /// TargetMachine - Primary interface to the complete machine description for
28 /// the target machine. All target-specific information should be accessible
29 /// through this interface.
31 class TargetMachine : public NonCopyableV {
32 const std::string Name;
33 const TargetData DataLayout; // Calculates type size & alignment
36 TargetMachine(const std::string &name, // Can only create subclasses...
37 bool LittleEndian = false,
38 unsigned char SubWordSize = 1, unsigned char IntRegSize = 8,
39 unsigned char PtrSize = 8, unsigned char PtrAl = 8,
40 unsigned char DoubleAl = 8, unsigned char FloatAl = 4,
41 unsigned char LongAl = 8, unsigned char IntAl = 4,
42 unsigned char ShortAl = 2, unsigned char ByteAl = 1)
43 : Name(name), DataLayout(name, LittleEndian, SubWordSize, IntRegSize,
44 PtrSize, PtrAl, DoubleAl, FloatAl, LongAl,
45 IntAl, ShortAl, ByteAl) {}
47 virtual ~TargetMachine() {}
49 const std::string &getName() const { return Name; }
51 // Interfaces to the major aspects of target machine information:
52 // -- Instruction opcode and operand information
53 // -- Pipelines and scheduling information
54 // -- Register information
55 // -- Stack frame information
56 // -- Cache hierarchy information
57 // -- Machine-level optimization information (peephole only)
59 virtual const TargetInstrInfo& getInstrInfo() const = 0;
60 virtual const TargetSchedInfo& getSchedInfo() const = 0;
61 virtual const TargetRegInfo& getRegInfo() const = 0;
62 virtual const TargetFrameInfo& getFrameInfo() const = 0;
63 virtual const TargetCacheInfo& getCacheInfo() const = 0;
64 virtual const TargetOptInfo& getOptInfo() const = 0;
65 const TargetData &getTargetData() const { return DataLayout; }
67 /// getRegisterInfo - If register information is available, return it. If
68 /// not, return null. This is kept separate from RegInfo until RegInfo has
69 /// details of graph coloring register allocation removed from it.
71 virtual const MRegisterInfo* getRegisterInfo() const { return 0; }
73 // Data storage information
75 virtual unsigned findOptimalStorageSize(const Type* ty) const;
77 /// addPassesToJITCompile - Add passes to the specified pass manager to
78 /// implement a fast dynamic compiler for this target. Return true if this is
79 /// not supported for this target.
81 virtual bool addPassesToJITCompile(PassManager &PM) { return true; }
83 /// addPassesToEmitAssembly - Add passes to the specified pass manager to get
84 /// assembly langage code emitted. Typically this will involve several steps
85 /// of code generation. This method should return true if assembly emission
88 virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out) {
92 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
93 /// get machine code emitted. This uses a MAchineCodeEmitter object to handle
94 /// actually outputting the machine code and resolving things like the address
95 /// of functions. This method should returns true if machine code emission is
98 virtual bool addPassesToEmitMachineCode(PassManager &PM,
99 MachineCodeEmitter &MCE) {