1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/Target/TargetInstrItineraries.h"
26 class TargetSubtarget;
27 class TargetInstrInfo;
28 class TargetIntrinsicInfo;
31 class TargetSelectionDAGInfo;
32 class TargetFrameLowering;
35 class TargetRegisterInfo;
36 class PassManagerBase;
39 class TargetELFWriterInfo;
40 class formatted_raw_ostream;
43 // Relocation model types.
48 PIC_, // Cannot be named PIC due to collision with -DPIC
64 // Code generation optimization level.
65 namespace CodeGenOpt {
76 None, // No preference
77 Latency, // Scheduling for shortest total latency.
78 RegPressure, // Scheduling for lowest register pressure.
79 Hybrid, // Scheduling for both latency and register pressure.
80 ILP // Scheduling for ILP in low register pressure mode.
84 //===----------------------------------------------------------------------===//
86 /// TargetMachine - Primary interface to the complete machine description for
87 /// the target machine. All target-specific information should be accessible
88 /// through this interface.
91 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
92 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
93 protected: // Can only create subclasses.
94 TargetMachine(const Target &);
96 /// getSubtargetImpl - virtual method implemented by subclasses that returns
97 /// a reference to that target's TargetSubtarget-derived member variable.
98 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
100 /// TheTarget - The Target that this machine was created for.
101 const Target &TheTarget;
103 /// AsmInfo - Contains target specific asm information.
105 const MCAsmInfo *AsmInfo;
107 unsigned MCRelaxAll : 1;
108 unsigned MCNoExecStack : 1;
109 unsigned MCSaveTempLabels : 1;
110 unsigned MCUseLoc : 1;
113 virtual ~TargetMachine();
115 const Target &getTarget() const { return TheTarget; }
117 // Interfaces to the major aspects of target machine information:
118 // -- Instruction opcode and operand information
119 // -- Pipelines and scheduling information
120 // -- Stack frame information
121 // -- Selection DAG lowering information
123 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
124 virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
125 virtual const TargetLowering *getTargetLowering() const { return 0; }
126 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
127 virtual const TargetData *getTargetData() const { return 0; }
129 /// getMCAsmInfo - Return target specific asm information.
131 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
133 /// getSubtarget - This method returns a pointer to the specified type of
134 /// TargetSubtarget. In debug builds, it verifies that the object being
135 /// returned is of the correct type.
136 template<typename STC> const STC &getSubtarget() const {
137 return *static_cast<const STC*>(getSubtargetImpl());
140 /// getRegisterInfo - If register information is available, return it. If
141 /// not, return null. This is kept separate from RegInfo until RegInfo has
142 /// details of graph coloring register allocation removed from it.
144 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
146 /// getIntrinsicInfo - If intrinsic information is available, return it. If
147 /// not, return null.
149 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
151 /// getJITInfo - If this target supports a JIT, return information for it,
152 /// otherwise return null.
154 virtual TargetJITInfo *getJITInfo() { return 0; }
156 /// getInstrItineraryData - Returns instruction itinerary data for the target
157 /// or specific subtarget.
159 virtual const InstrItineraryData *getInstrItineraryData() const {
163 /// getELFWriterInfo - If this target supports an ELF writer, return
164 /// information for it, otherwise return null.
166 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
168 /// hasMCRelaxAll - Check whether all machine code instructions should be
170 bool hasMCRelaxAll() const { return MCRelaxAll; }
172 /// setMCRelaxAll - Set whether all machine code instructions should be
174 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
176 /// hasMCSaveTempLabels - Check whether temporary labels will be preserved
177 /// (i.e., not treated as temporary).
178 bool hasMCSaveTempLabels() const { return MCSaveTempLabels; }
180 /// setMCSaveTempLabels - Set whether temporary labels will be preserved
181 /// (i.e., not treated as temporary).
182 void setMCSaveTempLabels(bool Value) { MCSaveTempLabels = Value; }
184 /// hasMCNoExecStack - Check whether an executable stack is not needed.
185 bool hasMCNoExecStack() const { return MCNoExecStack; }
187 /// setMCNoExecStack - Set whether an executabel stack is not needed.
188 void setMCNoExecStack(bool Value) { MCNoExecStack = Value; }
190 /// hasMCUseLoc - Check whether we should use dwarf's .loc directive.
191 bool hasMCUseLoc() const { return MCUseLoc; }
193 /// setMCUseLoc - Set whether all we should use dwarf's .loc directive.
194 void setMCUseLoc(bool Value) { MCUseLoc = Value; }
196 /// getRelocationModel - Returns the code generation relocation model. The
197 /// choices are static, PIC, and dynamic-no-pic, and target default.
198 static Reloc::Model getRelocationModel();
200 /// setRelocationModel - Sets the code generation relocation model.
202 static void setRelocationModel(Reloc::Model Model);
204 /// getCodeModel - Returns the code model. The choices are small, kernel,
205 /// medium, large, and target default.
206 static CodeModel::Model getCodeModel();
208 /// setCodeModel - Sets the code model.
210 static void setCodeModel(CodeModel::Model Model);
212 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
214 static bool getAsmVerbosityDefault();
216 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
218 static void setAsmVerbosityDefault(bool);
220 /// getDataSections - Return true if data objects should be emitted into their
221 /// own section, corresponds to -fdata-sections.
222 static bool getDataSections();
224 /// getFunctionSections - Return true if functions should be emitted into
225 /// their own section, corresponding to -ffunction-sections.
226 static bool getFunctionSections();
228 /// setDataSections - Set if the data are emit into separate sections.
229 static void setDataSections(bool);
231 /// setFunctionSections - Set if the functions are emit into separate
233 static void setFunctionSections(bool);
235 /// CodeGenFileType - These enums are meant to be passed into
236 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
237 /// it to indicate what type of file could actually be made.
238 enum CodeGenFileType {
241 CGFT_Null // Do not emit any output.
244 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
245 /// on this target. User flag overrides.
246 virtual bool getEnableTailMergeDefault() const { return true; }
248 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
249 /// specified file emitted. Typically this will involve several steps of code
250 /// generation. This method should return true if emission of this file type
251 /// is not supported, or false on success.
252 virtual bool addPassesToEmitFile(PassManagerBase &,
253 formatted_raw_ostream &,
260 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
261 /// get machine code emitted. This uses a JITCodeEmitter object to handle
262 /// actually outputting the machine code and resolving things like the address
263 /// of functions. This method returns true if machine code emission is
266 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
273 /// addPassesToEmitMC - Add passes to the specified pass manager to get
274 /// machine code emitted with the MCJIT. This method returns true if machine
275 /// code is not supported. It fills the MCContext Ctx pointer which can be
276 /// used to build custom MCStreamer.
278 virtual bool addPassesToEmitMC(PassManagerBase &,
287 /// LLVMTargetMachine - This class describes a target machine that is
288 /// implemented with the LLVM target-independent code generator.
290 class LLVMTargetMachine : public TargetMachine {
291 std::string TargetTriple;
293 protected: // Can only create subclasses.
294 LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
297 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
298 /// both emitting to assembly files or machine code output.
300 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
301 bool DisableVerify, MCContext *&OutCtx);
303 virtual void setCodeModelForJIT();
304 virtual void setCodeModelForStatic();
308 const std::string &getTargetTriple() const { return TargetTriple; }
310 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
311 /// specified file emitted. Typically this will involve several steps of code
312 /// generation. If OptLevel is None, the code generator should emit code as
313 /// fast as possible, though the generated code may be less efficient.
314 virtual bool addPassesToEmitFile(PassManagerBase &PM,
315 formatted_raw_ostream &Out,
316 CodeGenFileType FileType,
318 bool DisableVerify = true);
320 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
321 /// get machine code emitted. This uses a JITCodeEmitter object to handle
322 /// actually outputting the machine code and resolving things like the address
323 /// of functions. This method returns true if machine code emission is
326 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
329 bool DisableVerify = true);
331 /// addPassesToEmitMC - Add passes to the specified pass manager to get
332 /// machine code emitted with the MCJIT. This method returns true if machine
333 /// code is not supported. It fills the MCContext Ctx pointer which can be
334 /// used to build custom MCStreamer.
336 virtual bool addPassesToEmitMC(PassManagerBase &PM,
339 CodeGenOpt::Level OptLevel,
340 bool DisableVerify = true);
342 /// Target-Independent Code Generator Pass Configuration Options.
344 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
345 /// passes (which are run just before instruction selector).
346 virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
350 /// addInstSelector - This method should install an instruction selector pass,
351 /// which converts from LLVM code to machine instructions.
352 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
356 /// addPreRegAlloc - This method may be implemented by targets that want to
357 /// run passes immediately before register allocation. This should return
358 /// true if -print-machineinstrs should print after these passes.
359 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
363 /// addPostRegAlloc - This method may be implemented by targets that want
364 /// to run passes after register allocation but before prolog-epilog
365 /// insertion. This should return true if -print-machineinstrs should print
366 /// after these passes.
367 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
371 /// addPreSched2 - This method may be implemented by targets that want to
372 /// run passes after prolog-epilog insertion and before the second instruction
373 /// scheduling pass. This should return true if -print-machineinstrs should
374 /// print after these passes.
375 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
379 /// addPreEmitPass - This pass may be implemented by targets that want to run
380 /// passes immediately before machine code is emitted. This should return
381 /// true if -print-machineinstrs should print out the code after the passes.
382 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
387 /// addCodeEmitter - This pass should be overridden by the target to add a
388 /// code emitter, if supported. If this is not supported, 'true' should be
390 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
395 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
396 /// on this target. User flag overrides.
397 virtual bool getEnableTailMergeDefault() const { return true; }
400 } // End llvm namespace