1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/Target/TargetInstrItineraries.h"
26 class TargetSubtarget;
27 class TargetInstrInfo;
28 class TargetIntrinsicInfo;
31 class TargetSelectionDAGInfo;
32 class TargetFrameInfo;
35 class TargetRegisterInfo;
36 class PassManagerBase;
39 class TargetELFWriterInfo;
40 class formatted_raw_ostream;
42 // Relocation model types.
47 PIC_, // Cannot be named PIC due to collision with -DPIC
63 // Code generation optimization level.
64 namespace CodeGenOpt {
75 Latency, // Scheduling for shortest total latency.
76 RegPressure, // Scheduling for lowest register pressure.
77 Hybrid // Scheduling for both latency and register pressure.
81 //===----------------------------------------------------------------------===//
83 /// TargetMachine - Primary interface to the complete machine description for
84 /// the target machine. All target-specific information should be accessible
85 /// through this interface.
88 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
89 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
90 protected: // Can only create subclasses.
91 TargetMachine(const Target &);
93 /// getSubtargetImpl - virtual method implemented by subclasses that returns
94 /// a reference to that target's TargetSubtarget-derived member variable.
95 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
97 /// TheTarget - The Target that this machine was created for.
98 const Target &TheTarget;
100 /// AsmInfo - Contains target specific asm information.
102 const MCAsmInfo *AsmInfo;
105 virtual ~TargetMachine();
107 const Target &getTarget() const { return TheTarget; }
109 // Interfaces to the major aspects of target machine information:
110 // -- Instruction opcode and operand information
111 // -- Pipelines and scheduling information
112 // -- Stack frame information
113 // -- Selection DAG lowering information
115 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
116 virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
117 virtual const TargetLowering *getTargetLowering() const { return 0; }
118 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
119 virtual const TargetData *getTargetData() const { return 0; }
121 /// getMCAsmInfo - Return target specific asm information.
123 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
125 /// getSubtarget - This method returns a pointer to the specified type of
126 /// TargetSubtarget. In debug builds, it verifies that the object being
127 /// returned is of the correct type.
128 template<typename STC> const STC &getSubtarget() const {
129 return *static_cast<const STC*>(getSubtargetImpl());
132 /// getRegisterInfo - If register information is available, return it. If
133 /// not, return null. This is kept separate from RegInfo until RegInfo has
134 /// details of graph coloring register allocation removed from it.
136 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
138 /// getIntrinsicInfo - If intrinsic information is available, return it. If
139 /// not, return null.
141 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
143 /// getJITInfo - If this target supports a JIT, return information for it,
144 /// otherwise return null.
146 virtual TargetJITInfo *getJITInfo() { return 0; }
148 /// getInstrItineraryData - Returns instruction itinerary data for the target
149 /// or specific subtarget.
151 virtual const InstrItineraryData getInstrItineraryData() const {
152 return InstrItineraryData();
155 /// getELFWriterInfo - If this target supports an ELF writer, return
156 /// information for it, otherwise return null.
158 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
160 /// getRelocationModel - Returns the code generation relocation model. The
161 /// choices are static, PIC, and dynamic-no-pic, and target default.
162 static Reloc::Model getRelocationModel();
164 /// setRelocationModel - Sets the code generation relocation model.
166 static void setRelocationModel(Reloc::Model Model);
168 /// getCodeModel - Returns the code model. The choices are small, kernel,
169 /// medium, large, and target default.
170 static CodeModel::Model getCodeModel();
172 /// setCodeModel - Sets the code model.
174 static void setCodeModel(CodeModel::Model Model);
176 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
178 static bool getAsmVerbosityDefault();
180 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
182 static void setAsmVerbosityDefault(bool);
184 /// getDataSections - Return true if data objects should be emitted into their
185 /// own section, corresponds to -fdata-sections.
186 static bool getDataSections();
188 /// getFunctionSections - Return true if functions should be emitted into
189 /// their own section, corresponding to -ffunction-sections.
190 static bool getFunctionSections();
192 /// setDataSections - Set if the data are emit into separate sections.
193 static void setDataSections(bool);
195 /// setFunctionSections - Set if the functions are emit into separate
197 static void setFunctionSections(bool);
199 /// CodeGenFileType - These enums are meant to be passed into
200 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
201 /// it to indicate what type of file could actually be made.
202 enum CodeGenFileType {
205 CGFT_Null // Do not emit any output.
208 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
209 /// on this target. User flag overrides.
210 virtual bool getEnableTailMergeDefault() const { return true; }
212 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
213 /// specified file emitted. Typically this will involve several steps of code
214 /// generation. This method should return true if emission of this file type
215 /// is not supported, or false on success.
216 virtual bool addPassesToEmitFile(PassManagerBase &,
217 formatted_raw_ostream &,
224 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
225 /// get machine code emitted. This uses a JITCodeEmitter object to handle
226 /// actually outputting the machine code and resolving things like the address
227 /// of functions. This method returns true if machine code emission is
230 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
238 /// LLVMTargetMachine - This class describes a target machine that is
239 /// implemented with the LLVM target-independent code generator.
241 class LLVMTargetMachine : public TargetMachine {
242 std::string TargetTriple;
244 protected: // Can only create subclasses.
245 LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
248 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
249 /// both emitting to assembly files or machine code output.
251 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
252 bool DisableVerify, MCContext *&OutCtx);
254 virtual void setCodeModelForJIT();
255 virtual void setCodeModelForStatic();
259 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
260 /// specified file emitted. Typically this will involve several steps of code
261 /// generation. If OptLevel is None, the code generator should emit code as
262 /// fast as possible, though the generated code may be less efficient.
263 virtual bool addPassesToEmitFile(PassManagerBase &PM,
264 formatted_raw_ostream &Out,
265 CodeGenFileType FileType,
267 bool DisableVerify = true);
269 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
270 /// get machine code emitted. This uses a JITCodeEmitter object to handle
271 /// actually outputting the machine code and resolving things like the address
272 /// of functions. This method returns true if machine code emission is
275 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
278 bool DisableVerify = true);
280 /// Target-Independent Code Generator Pass Configuration Options.
282 /// addInstSelector - This method should add any "last minute" LLVM->LLVM
283 /// passes, then install an instruction selector pass, which converts from
284 /// LLVM code to machine instructions.
285 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
289 /// addPreRegAlloc - This method may be implemented by targets that want to
290 /// run passes immediately before register allocation. This should return
291 /// true if -print-machineinstrs should print after these passes.
292 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
296 /// addPostRegAlloc - This method may be implemented by targets that want
297 /// to run passes after register allocation but before prolog-epilog
298 /// insertion. This should return true if -print-machineinstrs should print
299 /// after these passes.
300 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
304 /// addPreSched2 - This method may be implemented by targets that want to
305 /// run passes after prolog-epilog insertion and before the second instruction
306 /// scheduling pass. This should return true if -print-machineinstrs should
307 /// print after these passes.
308 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
312 /// addPreEmitPass - This pass may be implemented by targets that want to run
313 /// passes immediately before machine code is emitted. This should return
314 /// true if -print-machineinstrs should print out the code after the passes.
315 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
320 /// addCodeEmitter - This pass should be overridden by the target to add a
321 /// code emitter, if supported. If this is not supported, 'true' should be
323 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
328 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
329 /// on this target. User flag overrides.
330 virtual bool getEnableTailMergeDefault() const { return true; }
333 } // End llvm namespace