1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/Target/TargetInstrItineraries.h"
26 class TargetSubtarget;
27 class TargetInstrInfo;
28 class TargetIntrinsicInfo;
31 class TargetSelectionDAGInfo;
32 class TargetFrameInfo;
35 class TargetRegisterInfo;
36 class PassManagerBase;
39 class TargetELFWriterInfo;
40 class formatted_raw_ostream;
42 // Relocation model types.
47 PIC_, // Cannot be named PIC due to collision with -DPIC
63 // Code generation optimization level.
64 namespace CodeGenOpt {
75 Latency, // Scheduling for shortest total latency.
76 RegPressure // Scheduling for lowest register pressure.
80 //===----------------------------------------------------------------------===//
82 /// TargetMachine - Primary interface to the complete machine description for
83 /// the target machine. All target-specific information should be accessible
84 /// through this interface.
87 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
88 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
89 protected: // Can only create subclasses.
90 TargetMachine(const Target &);
92 /// getSubtargetImpl - virtual method implemented by subclasses that returns
93 /// a reference to that target's TargetSubtarget-derived member variable.
94 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
96 /// TheTarget - The Target that this machine was created for.
97 const Target &TheTarget;
99 /// AsmInfo - Contains target specific asm information.
101 const MCAsmInfo *AsmInfo;
104 virtual ~TargetMachine();
106 const Target &getTarget() const { return TheTarget; }
108 // Interfaces to the major aspects of target machine information:
109 // -- Instruction opcode and operand information
110 // -- Pipelines and scheduling information
111 // -- Stack frame information
112 // -- Selection DAG lowering information
114 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
115 virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
116 virtual const TargetLowering *getTargetLowering() const { return 0; }
117 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
118 virtual const TargetData *getTargetData() const { return 0; }
120 /// getMCAsmInfo - Return target specific asm information.
122 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
124 /// getSubtarget - This method returns a pointer to the specified type of
125 /// TargetSubtarget. In debug builds, it verifies that the object being
126 /// returned is of the correct type.
127 template<typename STC> const STC &getSubtarget() const {
128 return *static_cast<const STC*>(getSubtargetImpl());
131 /// getRegisterInfo - If register information is available, return it. If
132 /// not, return null. This is kept separate from RegInfo until RegInfo has
133 /// details of graph coloring register allocation removed from it.
135 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
137 /// getIntrinsicInfo - If intrinsic information is available, return it. If
138 /// not, return null.
140 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
142 /// getJITInfo - If this target supports a JIT, return information for it,
143 /// otherwise return null.
145 virtual TargetJITInfo *getJITInfo() { return 0; }
147 /// getInstrItineraryData - Returns instruction itinerary data for the target
148 /// or specific subtarget.
150 virtual const InstrItineraryData getInstrItineraryData() const {
151 return InstrItineraryData();
154 /// getELFWriterInfo - If this target supports an ELF writer, return
155 /// information for it, otherwise return null.
157 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
159 /// getRelocationModel - Returns the code generation relocation model. The
160 /// choices are static, PIC, and dynamic-no-pic, and target default.
161 static Reloc::Model getRelocationModel();
163 /// setRelocationModel - Sets the code generation relocation model.
165 static void setRelocationModel(Reloc::Model Model);
167 /// getCodeModel - Returns the code model. The choices are small, kernel,
168 /// medium, large, and target default.
169 static CodeModel::Model getCodeModel();
171 /// setCodeModel - Sets the code model.
173 static void setCodeModel(CodeModel::Model Model);
175 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
177 static bool getAsmVerbosityDefault();
179 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
181 static void setAsmVerbosityDefault(bool);
183 /// getDataSections - Return true if data objects should be emitted into their
184 /// own section, corresponds to -fdata-sections.
185 static bool getDataSections();
187 /// getFunctionSections - Return true if functions should be emitted into
188 /// their own section, corresponding to -ffunction-sections.
189 static bool getFunctionSections();
191 /// setDataSections - Set if the data are emit into separate sections.
192 static void setDataSections(bool);
194 /// setFunctionSections - Set if the functions are emit into separate
196 static void setFunctionSections(bool);
198 /// CodeGenFileType - These enums are meant to be passed into
199 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
200 /// it to indicate what type of file could actually be made.
201 enum CodeGenFileType {
204 CGFT_Null // Do not emit any output.
207 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
208 /// on this target. User flag overrides.
209 virtual bool getEnableTailMergeDefault() const { return true; }
211 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
212 /// specified file emitted. Typically this will involve several steps of code
213 /// generation. This method should return true if emission of this file type
214 /// is not supported, or false on success.
215 virtual bool addPassesToEmitFile(PassManagerBase &,
216 formatted_raw_ostream &,
223 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
224 /// get machine code emitted. This uses a JITCodeEmitter object to handle
225 /// actually outputting the machine code and resolving things like the address
226 /// of functions. This method returns true if machine code emission is
229 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
237 /// LLVMTargetMachine - This class describes a target machine that is
238 /// implemented with the LLVM target-independent code generator.
240 class LLVMTargetMachine : public TargetMachine {
241 std::string TargetTriple;
243 protected: // Can only create subclasses.
244 LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
247 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
248 /// both emitting to assembly files or machine code output.
250 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
251 bool DisableVerify, MCContext *&OutCtx);
253 virtual void setCodeModelForJIT();
254 virtual void setCodeModelForStatic();
258 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
259 /// specified file emitted. Typically this will involve several steps of code
260 /// generation. If OptLevel is None, the code generator should emit code as
261 /// fast as possible, though the generated code may be less efficient.
262 virtual bool addPassesToEmitFile(PassManagerBase &PM,
263 formatted_raw_ostream &Out,
264 CodeGenFileType FileType,
266 bool DisableVerify = true);
268 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
269 /// get machine code emitted. This uses a JITCodeEmitter object to handle
270 /// actually outputting the machine code and resolving things like the address
271 /// of functions. This method returns true if machine code emission is
274 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
277 bool DisableVerify = true);
279 /// Target-Independent Code Generator Pass Configuration Options.
281 /// addInstSelector - This method should add any "last minute" LLVM->LLVM
282 /// passes, then install an instruction selector pass, which converts from
283 /// LLVM code to machine instructions.
284 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
288 /// addPreRegAlloc - This method may be implemented by targets that want to
289 /// run passes immediately before register allocation. This should return
290 /// true if -print-machineinstrs should print after these passes.
291 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
295 /// addPostRegAlloc - This method may be implemented by targets that want
296 /// to run passes after register allocation but before prolog-epilog
297 /// insertion. This should return true if -print-machineinstrs should print
298 /// after these passes.
299 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
303 /// addPreSched2 - This method may be implemented by targets that want to
304 /// run passes after prolog-epilog insertion and before the second instruction
305 /// scheduling pass. This should return true if -print-machineinstrs should
306 /// print after these passes.
307 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
311 /// addPreEmitPass - This pass may be implemented by targets that want to run
312 /// passes immediately before machine code is emitted. This should return
313 /// true if -print-machineinstrs should print out the code after the passes.
314 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
319 /// addCodeEmitter - This pass should be overridden by the target to add a
320 /// code emitter, if supported. If this is not supported, 'true' should be
322 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
327 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
328 /// on this target. User flag overrides.
329 virtual bool getEnableTailMergeDefault() const { return true; }
332 } // End llvm namespace