1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/Target/TargetInstrItineraries.h"
26 class TargetSubtarget;
27 class TargetInstrInfo;
28 class TargetIntrinsicInfo;
31 class TargetSelectionDAGInfo;
32 class TargetFrameInfo;
35 class TargetRegisterInfo;
36 class PassManagerBase;
39 class TargetELFWriterInfo;
40 class formatted_raw_ostream;
42 // Relocation model types.
47 PIC_, // Cannot be named PIC due to collision with -DPIC
63 // Code generation optimization level.
64 namespace CodeGenOpt {
75 None, // No preference
76 Latency, // Scheduling for shortest total latency.
77 RegPressure, // Scheduling for lowest register pressure.
78 Hybrid // Scheduling for both latency and register pressure.
82 //===----------------------------------------------------------------------===//
84 /// TargetMachine - Primary interface to the complete machine description for
85 /// the target machine. All target-specific information should be accessible
86 /// through this interface.
89 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
90 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
91 protected: // Can only create subclasses.
92 TargetMachine(const Target &);
94 /// getSubtargetImpl - virtual method implemented by subclasses that returns
95 /// a reference to that target's TargetSubtarget-derived member variable.
96 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
98 /// TheTarget - The Target that this machine was created for.
99 const Target &TheTarget;
101 /// AsmInfo - Contains target specific asm information.
103 const MCAsmInfo *AsmInfo;
106 virtual ~TargetMachine();
108 const Target &getTarget() const { return TheTarget; }
110 // Interfaces to the major aspects of target machine information:
111 // -- Instruction opcode and operand information
112 // -- Pipelines and scheduling information
113 // -- Stack frame information
114 // -- Selection DAG lowering information
116 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
117 virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
118 virtual const TargetLowering *getTargetLowering() const { return 0; }
119 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
120 virtual const TargetData *getTargetData() const { return 0; }
122 /// getMCAsmInfo - Return target specific asm information.
124 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
126 /// getSubtarget - This method returns a pointer to the specified type of
127 /// TargetSubtarget. In debug builds, it verifies that the object being
128 /// returned is of the correct type.
129 template<typename STC> const STC &getSubtarget() const {
130 return *static_cast<const STC*>(getSubtargetImpl());
133 /// getRegisterInfo - If register information is available, return it. If
134 /// not, return null. This is kept separate from RegInfo until RegInfo has
135 /// details of graph coloring register allocation removed from it.
137 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
139 /// getIntrinsicInfo - If intrinsic information is available, return it. If
140 /// not, return null.
142 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
144 /// getJITInfo - If this target supports a JIT, return information for it,
145 /// otherwise return null.
147 virtual TargetJITInfo *getJITInfo() { return 0; }
149 /// getInstrItineraryData - Returns instruction itinerary data for the target
150 /// or specific subtarget.
152 virtual const InstrItineraryData getInstrItineraryData() const {
153 return InstrItineraryData();
156 /// getELFWriterInfo - If this target supports an ELF writer, return
157 /// information for it, otherwise return null.
159 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
161 /// getRelocationModel - Returns the code generation relocation model. The
162 /// choices are static, PIC, and dynamic-no-pic, and target default.
163 static Reloc::Model getRelocationModel();
165 /// setRelocationModel - Sets the code generation relocation model.
167 static void setRelocationModel(Reloc::Model Model);
169 /// getCodeModel - Returns the code model. The choices are small, kernel,
170 /// medium, large, and target default.
171 static CodeModel::Model getCodeModel();
173 /// setCodeModel - Sets the code model.
175 static void setCodeModel(CodeModel::Model Model);
177 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
179 static bool getAsmVerbosityDefault();
181 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
183 static void setAsmVerbosityDefault(bool);
185 /// getDataSections - Return true if data objects should be emitted into their
186 /// own section, corresponds to -fdata-sections.
187 static bool getDataSections();
189 /// getFunctionSections - Return true if functions should be emitted into
190 /// their own section, corresponding to -ffunction-sections.
191 static bool getFunctionSections();
193 /// setDataSections - Set if the data are emit into separate sections.
194 static void setDataSections(bool);
196 /// setFunctionSections - Set if the functions are emit into separate
198 static void setFunctionSections(bool);
200 /// CodeGenFileType - These enums are meant to be passed into
201 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
202 /// it to indicate what type of file could actually be made.
203 enum CodeGenFileType {
206 CGFT_Null // Do not emit any output.
209 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
210 /// on this target. User flag overrides.
211 virtual bool getEnableTailMergeDefault() const { return true; }
213 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
214 /// specified file emitted. Typically this will involve several steps of code
215 /// generation. This method should return true if emission of this file type
216 /// is not supported, or false on success.
217 virtual bool addPassesToEmitFile(PassManagerBase &,
218 formatted_raw_ostream &,
225 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
226 /// get machine code emitted. This uses a JITCodeEmitter object to handle
227 /// actually outputting the machine code and resolving things like the address
228 /// of functions. This method returns true if machine code emission is
231 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
239 /// LLVMTargetMachine - This class describes a target machine that is
240 /// implemented with the LLVM target-independent code generator.
242 class LLVMTargetMachine : public TargetMachine {
243 std::string TargetTriple;
245 protected: // Can only create subclasses.
246 LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
249 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
250 /// both emitting to assembly files or machine code output.
252 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
253 bool DisableVerify, MCContext *&OutCtx);
255 virtual void setCodeModelForJIT();
256 virtual void setCodeModelForStatic();
260 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
261 /// specified file emitted. Typically this will involve several steps of code
262 /// generation. If OptLevel is None, the code generator should emit code as
263 /// fast as possible, though the generated code may be less efficient.
264 virtual bool addPassesToEmitFile(PassManagerBase &PM,
265 formatted_raw_ostream &Out,
266 CodeGenFileType FileType,
268 bool DisableVerify = true);
270 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
271 /// get machine code emitted. This uses a JITCodeEmitter object to handle
272 /// actually outputting the machine code and resolving things like the address
273 /// of functions. This method returns true if machine code emission is
276 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
279 bool DisableVerify = true);
281 /// Target-Independent Code Generator Pass Configuration Options.
283 /// addInstSelector - This method should add any "last minute" LLVM->LLVM
284 /// passes, then install an instruction selector pass, which converts from
285 /// LLVM code to machine instructions.
286 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
290 /// addPreRegAlloc - This method may be implemented by targets that want to
291 /// run passes immediately before register allocation. This should return
292 /// true if -print-machineinstrs should print after these passes.
293 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
297 /// addPostRegAlloc - This method may be implemented by targets that want
298 /// to run passes after register allocation but before prolog-epilog
299 /// insertion. This should return true if -print-machineinstrs should print
300 /// after these passes.
301 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
305 /// addPreSched2 - This method may be implemented by targets that want to
306 /// run passes after prolog-epilog insertion and before the second instruction
307 /// scheduling pass. This should return true if -print-machineinstrs should
308 /// print after these passes.
309 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
313 /// addPreEmitPass - This pass may be implemented by targets that want to run
314 /// passes immediately before machine code is emitted. This should return
315 /// true if -print-machineinstrs should print out the code after the passes.
316 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
321 /// addCodeEmitter - This pass should be overridden by the target to add a
322 /// code emitter, if supported. If this is not supported, 'true' should be
324 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
329 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
330 /// on this target. User flag overrides.
331 virtual bool getEnableTailMergeDefault() const { return true; }
334 } // End llvm namespace