1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/Target/TargetOptions.h"
18 #include "llvm/MC/MCCodeGenInfo.h"
19 #include "llvm/ADT/StringRef.h"
25 class InstrItineraryData;
32 class PassManagerBase;
35 class TargetELFWriterInfo;
36 class TargetFrameLowering;
37 class TargetInstrInfo;
38 class TargetIntrinsicInfo;
41 class TargetRegisterInfo;
42 class TargetSelectionDAGInfo;
43 class TargetSubtargetInfo;
44 class formatted_raw_ostream;
49 None, // No preference
50 RegPressure, // Scheduling for lowest register pressure.
51 Hybrid, // Scheduling for both latency and register pressure.
52 ILP // Scheduling for ILP in low register pressure mode.
56 //===----------------------------------------------------------------------===//
58 /// TargetMachine - Primary interface to the complete machine description for
59 /// the target machine. All target-specific information should be accessible
60 /// through this interface.
63 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
64 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
65 protected: // Can only create subclasses.
66 TargetMachine(const Target &T, StringRef TargetTriple,
67 StringRef CPU, StringRef FS, const TargetOptions &Options);
69 /// getSubtargetImpl - virtual method implemented by subclasses that returns
70 /// a reference to that target's TargetSubtargetInfo-derived member variable.
71 virtual const TargetSubtargetInfo *getSubtargetImpl() const { return 0; }
73 /// TheTarget - The Target that this machine was created for.
74 const Target &TheTarget;
76 /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target
77 /// feature strings the TargetMachine instance is created with.
78 std::string TargetTriple;
79 std::string TargetCPU;
82 /// CodeGenInfo - Low level target information such as relocation model.
83 const MCCodeGenInfo *CodeGenInfo;
85 /// AsmInfo - Contains target specific asm information.
87 const MCAsmInfo *AsmInfo;
89 unsigned MCRelaxAll : 1;
90 unsigned MCNoExecStack : 1;
91 unsigned MCSaveTempLabels : 1;
92 unsigned MCUseLoc : 1;
93 unsigned MCUseCFI : 1;
94 unsigned MCUseDwarfDirectory : 1;
97 virtual ~TargetMachine();
99 const Target &getTarget() const { return TheTarget; }
101 const StringRef getTargetTriple() const { return TargetTriple; }
102 const StringRef getTargetCPU() const { return TargetCPU; }
103 const StringRef getTargetFeatureString() const { return TargetFS; }
105 TargetOptions Options;
107 // Interfaces to the major aspects of target machine information:
108 // -- Instruction opcode and operand information
109 // -- Pipelines and scheduling information
110 // -- Stack frame information
111 // -- Selection DAG lowering information
113 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
114 virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
115 virtual const TargetLowering *getTargetLowering() const { return 0; }
116 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
117 virtual const TargetData *getTargetData() const { return 0; }
119 /// getMCAsmInfo - Return target specific asm information.
121 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
123 /// getSubtarget - This method returns a pointer to the specified type of
124 /// TargetSubtargetInfo. In debug builds, it verifies that the object being
125 /// returned is of the correct type.
126 template<typename STC> const STC &getSubtarget() const {
127 return *static_cast<const STC*>(getSubtargetImpl());
130 /// getRegisterInfo - If register information is available, return it. If
131 /// not, return null. This is kept separate from RegInfo until RegInfo has
132 /// details of graph coloring register allocation removed from it.
134 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
136 /// getIntrinsicInfo - If intrinsic information is available, return it. If
137 /// not, return null.
139 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
141 /// getJITInfo - If this target supports a JIT, return information for it,
142 /// otherwise return null.
144 virtual TargetJITInfo *getJITInfo() { return 0; }
146 /// getInstrItineraryData - Returns instruction itinerary data for the target
147 /// or specific subtarget.
149 virtual const InstrItineraryData *getInstrItineraryData() const {
153 /// getELFWriterInfo - If this target supports an ELF writer, return
154 /// information for it, otherwise return null.
156 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
158 /// hasMCRelaxAll - Check whether all machine code instructions should be
160 bool hasMCRelaxAll() const { return MCRelaxAll; }
162 /// setMCRelaxAll - Set whether all machine code instructions should be
164 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
166 /// hasMCSaveTempLabels - Check whether temporary labels will be preserved
167 /// (i.e., not treated as temporary).
168 bool hasMCSaveTempLabels() const { return MCSaveTempLabels; }
170 /// setMCSaveTempLabels - Set whether temporary labels will be preserved
171 /// (i.e., not treated as temporary).
172 void setMCSaveTempLabels(bool Value) { MCSaveTempLabels = Value; }
174 /// hasMCNoExecStack - Check whether an executable stack is not needed.
175 bool hasMCNoExecStack() const { return MCNoExecStack; }
177 /// setMCNoExecStack - Set whether an executabel stack is not needed.
178 void setMCNoExecStack(bool Value) { MCNoExecStack = Value; }
180 /// hasMCUseLoc - Check whether we should use dwarf's .loc directive.
181 bool hasMCUseLoc() const { return MCUseLoc; }
183 /// setMCUseLoc - Set whether all we should use dwarf's .loc directive.
184 void setMCUseLoc(bool Value) { MCUseLoc = Value; }
186 /// hasMCUseCFI - Check whether we should use dwarf's .cfi_* directives.
187 bool hasMCUseCFI() const { return MCUseCFI; }
189 /// setMCUseCFI - Set whether all we should use dwarf's .cfi_* directives.
190 void setMCUseCFI(bool Value) { MCUseCFI = Value; }
192 /// hasMCUseDwarfDirectory - Check whether we should use .file directives with
193 /// explicit directories.
194 bool hasMCUseDwarfDirectory() const { return MCUseDwarfDirectory; }
196 /// setMCUseDwarfDirectory - Set whether all we should use .file directives
197 /// with explicit directories.
198 void setMCUseDwarfDirectory(bool Value) { MCUseDwarfDirectory = Value; }
200 /// getRelocationModel - Returns the code generation relocation model. The
201 /// choices are static, PIC, and dynamic-no-pic, and target default.
202 Reloc::Model getRelocationModel() const;
204 /// getCodeModel - Returns the code model. The choices are small, kernel,
205 /// medium, large, and target default.
206 CodeModel::Model getCodeModel() const;
208 /// getOptLevel - Returns the optimization level: None, Less,
209 /// Default, or Aggressive.
210 CodeGenOpt::Level getOptLevel() const;
212 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
214 static bool getAsmVerbosityDefault();
216 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
218 static void setAsmVerbosityDefault(bool);
220 /// getDataSections - Return true if data objects should be emitted into their
221 /// own section, corresponds to -fdata-sections.
222 static bool getDataSections();
224 /// getFunctionSections - Return true if functions should be emitted into
225 /// their own section, corresponding to -ffunction-sections.
226 static bool getFunctionSections();
228 /// setDataSections - Set if the data are emit into separate sections.
229 static void setDataSections(bool);
231 /// setFunctionSections - Set if the functions are emit into separate
233 static void setFunctionSections(bool);
235 /// CodeGenFileType - These enums are meant to be passed into
236 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
237 /// it to indicate what type of file could actually be made.
238 enum CodeGenFileType {
241 CGFT_Null // Do not emit any output.
244 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
245 /// on this target. User flag overrides.
246 virtual bool getEnableTailMergeDefault() const { return true; }
248 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
249 /// specified file emitted. Typically this will involve several steps of code
250 /// generation. This method should return true if emission of this file type
251 /// is not supported, or false on success.
252 virtual bool addPassesToEmitFile(PassManagerBase &,
253 formatted_raw_ostream &,
255 bool /*DisableVerify*/ = true) {
259 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
260 /// get machine code emitted. This uses a JITCodeEmitter object to handle
261 /// actually outputting the machine code and resolving things like the address
262 /// of functions. This method returns true if machine code emission is
265 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
267 bool /*DisableVerify*/ = true) {
271 /// addPassesToEmitMC - Add passes to the specified pass manager to get
272 /// machine code emitted with the MCJIT. This method returns true if machine
273 /// code is not supported. It fills the MCContext Ctx pointer which can be
274 /// used to build custom MCStreamer.
276 virtual bool addPassesToEmitMC(PassManagerBase &,
279 bool /*DisableVerify*/ = true) {
284 /// LLVMTargetMachine - This class describes a target machine that is
285 /// implemented with the LLVM target-independent code generator.
287 class LLVMTargetMachine : public TargetMachine {
288 protected: // Can only create subclasses.
289 LLVMTargetMachine(const Target &T, StringRef TargetTriple,
290 StringRef CPU, StringRef FS, TargetOptions Options,
291 Reloc::Model RM, CodeModel::Model CM,
292 CodeGenOpt::Level OL);
294 /// printNoVerify - Add a pass to dump the machine function, if debugging is
297 void printNoVerify(PassManagerBase &PM, const char *Banner) const;
299 /// printAndVerify - Add a pass to dump then verify the machine function, if
300 /// those steps are enabled.
302 void printAndVerify(PassManagerBase &PM, const char *Banner) const;
305 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
306 /// both emitting to assembly files or machine code output.
308 bool addCommonCodeGenPasses(PassManagerBase &,
309 bool DisableVerify, MCContext *&OutCtx);
312 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
313 /// specified file emitted. Typically this will involve several steps of code
315 virtual bool addPassesToEmitFile(PassManagerBase &PM,
316 formatted_raw_ostream &Out,
317 CodeGenFileType FileType,
318 bool DisableVerify = true);
320 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
321 /// get machine code emitted. This uses a JITCodeEmitter object to handle
322 /// actually outputting the machine code and resolving things like the address
323 /// of functions. This method returns true if machine code emission is
326 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
328 bool DisableVerify = true);
330 /// addPassesToEmitMC - Add passes to the specified pass manager to get
331 /// machine code emitted with the MCJIT. This method returns true if machine
332 /// code is not supported. It fills the MCContext Ctx pointer which can be
333 /// used to build custom MCStreamer.
335 virtual bool addPassesToEmitMC(PassManagerBase &PM,
338 bool DisableVerify = true);
340 /// Target-Independent Code Generator Pass Configuration Options.
342 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
343 /// passes (which are run just before instruction selector).
344 virtual bool addPreISel(PassManagerBase &) {
348 /// addInstSelector - This method should install an instruction selector pass,
349 /// which converts from LLVM code to machine instructions.
350 virtual bool addInstSelector(PassManagerBase &) {
354 /// addPreRegAlloc - This method may be implemented by targets that want to
355 /// run passes immediately before register allocation. This should return
356 /// true if -print-machineinstrs should print after these passes.
357 virtual bool addPreRegAlloc(PassManagerBase &) {
361 /// addPostRegAlloc - This method may be implemented by targets that want
362 /// to run passes after register allocation but before prolog-epilog
363 /// insertion. This should return true if -print-machineinstrs should print
364 /// after these passes.
365 virtual bool addPostRegAlloc(PassManagerBase &) {
369 /// addPreSched2 - This method may be implemented by targets that want to
370 /// run passes after prolog-epilog insertion and before the second instruction
371 /// scheduling pass. This should return true if -print-machineinstrs should
372 /// print after these passes.
373 virtual bool addPreSched2(PassManagerBase &) {
377 /// addPreEmitPass - This pass may be implemented by targets that want to run
378 /// passes immediately before machine code is emitted. This should return
379 /// true if -print-machineinstrs should print out the code after the passes.
380 virtual bool addPreEmitPass(PassManagerBase &) {
385 /// addCodeEmitter - This pass should be overridden by the target to add a
386 /// code emitter, if supported. If this is not supported, 'true' should be
388 virtual bool addCodeEmitter(PassManagerBase &,
393 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
394 /// on this target. User flag overrides.
395 virtual bool getEnableTailMergeDefault() const { return true; }
398 } // End llvm namespace