1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/Target/TargetInstrItineraries.h"
26 class TargetSubtarget;
27 class TargetInstrInfo;
28 class TargetIntrinsicInfo;
31 class TargetSelectionDAGInfo;
32 class TargetFrameInfo;
35 class TargetRegisterInfo;
36 class PassManagerBase;
39 class TargetELFWriterInfo;
40 class formatted_raw_ostream;
42 // Relocation model types.
47 PIC_, // Cannot be named PIC due to collision with -DPIC
63 // Code generation optimization level.
64 namespace CodeGenOpt {
73 //===----------------------------------------------------------------------===//
75 /// TargetMachine - Primary interface to the complete machine description for
76 /// the target machine. All target-specific information should be accessible
77 /// through this interface.
80 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
81 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
82 protected: // Can only create subclasses.
83 TargetMachine(const Target &);
85 /// getSubtargetImpl - virtual method implemented by subclasses that returns
86 /// a reference to that target's TargetSubtarget-derived member variable.
87 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
89 /// TheTarget - The Target that this machine was created for.
90 const Target &TheTarget;
92 /// AsmInfo - Contains target specific asm information.
94 const MCAsmInfo *AsmInfo;
97 virtual ~TargetMachine();
99 const Target &getTarget() const { return TheTarget; }
101 // Interfaces to the major aspects of target machine information:
102 // -- Instruction opcode and operand information
103 // -- Pipelines and scheduling information
104 // -- Stack frame information
105 // -- Selection DAG lowering information
107 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
108 virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
109 virtual const TargetLowering *getTargetLowering() const { return 0; }
110 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
111 virtual const TargetData *getTargetData() const { return 0; }
113 /// getMCAsmInfo - Return target specific asm information.
115 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
117 /// getSubtarget - This method returns a pointer to the specified type of
118 /// TargetSubtarget. In debug builds, it verifies that the object being
119 /// returned is of the correct type.
120 template<typename STC> const STC &getSubtarget() const {
121 return *static_cast<const STC*>(getSubtargetImpl());
124 /// getRegisterInfo - If register information is available, return it. If
125 /// not, return null. This is kept separate from RegInfo until RegInfo has
126 /// details of graph coloring register allocation removed from it.
128 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
130 /// getIntrinsicInfo - If intrinsic information is available, return it. If
131 /// not, return null.
133 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
135 /// getJITInfo - If this target supports a JIT, return information for it,
136 /// otherwise return null.
138 virtual TargetJITInfo *getJITInfo() { return 0; }
140 /// getInstrItineraryData - Returns instruction itinerary data for the target
141 /// or specific subtarget.
143 virtual const InstrItineraryData getInstrItineraryData() const {
144 return InstrItineraryData();
147 /// getELFWriterInfo - If this target supports an ELF writer, return
148 /// information for it, otherwise return null.
150 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
152 /// getRelocationModel - Returns the code generation relocation model. The
153 /// choices are static, PIC, and dynamic-no-pic, and target default.
154 static Reloc::Model getRelocationModel();
156 /// setRelocationModel - Sets the code generation relocation model.
158 static void setRelocationModel(Reloc::Model Model);
160 /// getCodeModel - Returns the code model. The choices are small, kernel,
161 /// medium, large, and target default.
162 static CodeModel::Model getCodeModel();
164 /// setCodeModel - Sets the code model.
166 static void setCodeModel(CodeModel::Model Model);
168 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
170 static bool getAsmVerbosityDefault();
172 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
174 static void setAsmVerbosityDefault(bool);
176 /// getDataSections - Return true if data objects should be emitted into their
177 /// own section, corresponds to -fdata-sections.
178 static bool getDataSections();
180 /// getFunctionSections - Return true if functions should be emitted into
181 /// their own section, corresponding to -ffunction-sections.
182 static bool getFunctionSections();
184 /// setDataSections - Set if the data are emit into separate sections.
185 static void setDataSections(bool);
187 /// setFunctionSections - Set if the functions are emit into separate
189 static void setFunctionSections(bool);
191 /// CodeGenFileType - These enums are meant to be passed into
192 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
193 /// it to indicate what type of file could actually be made.
194 enum CodeGenFileType {
197 CGFT_Null // Do not emit any output.
200 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
201 /// on this target. User flag overrides.
202 virtual bool getEnableTailMergeDefault() const { return true; }
204 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
205 /// specified file emitted. Typically this will involve several steps of code
206 /// generation. This method should return true if emission of this file type
207 /// is not supported, or false on success.
208 virtual bool addPassesToEmitFile(PassManagerBase &,
209 formatted_raw_ostream &,
216 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
217 /// get machine code emitted. This uses a JITCodeEmitter object to handle
218 /// actually outputting the machine code and resolving things like the address
219 /// of functions. This method returns true if machine code emission is
222 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
229 /// addPassesToEmitWholeFile - This method can be implemented by targets that
230 /// require having the entire module at once. This is not recommended, do not
232 virtual bool WantsWholeFile() const { return false; }
233 virtual bool addPassesToEmitWholeFile(PassManager &, formatted_raw_ostream &,
241 /// LLVMTargetMachine - This class describes a target machine that is
242 /// implemented with the LLVM target-independent code generator.
244 class LLVMTargetMachine : public TargetMachine {
245 std::string TargetTriple;
247 protected: // Can only create subclasses.
248 LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
251 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
252 /// both emitting to assembly files or machine code output.
254 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
255 bool DisableVerify, MCContext *&OutCtx);
257 virtual void setCodeModelForJIT();
258 virtual void setCodeModelForStatic();
262 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
263 /// specified file emitted. Typically this will involve several steps of code
264 /// generation. If OptLevel is None, the code generator should emit code as
265 /// fast as possible, though the generated code may be less efficient.
266 virtual bool addPassesToEmitFile(PassManagerBase &PM,
267 formatted_raw_ostream &Out,
268 CodeGenFileType FileType,
270 bool DisableVerify = true);
272 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
273 /// get machine code emitted. This uses a JITCodeEmitter object to handle
274 /// actually outputting the machine code and resolving things like the address
275 /// of functions. This method returns true if machine code emission is
278 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
281 bool DisableVerify = true);
283 /// Target-Independent Code Generator Pass Configuration Options.
285 /// addInstSelector - This method should add any "last minute" LLVM->LLVM
286 /// passes, then install an instruction selector pass, which converts from
287 /// LLVM code to machine instructions.
288 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
292 /// addPreRegAlloc - This method may be implemented by targets that want to
293 /// run passes immediately before register allocation. This should return
294 /// true if -print-machineinstrs should print after these passes.
295 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
299 /// addPostRegAlloc - This method may be implemented by targets that want
300 /// to run passes after register allocation but before prolog-epilog
301 /// insertion. This should return true if -print-machineinstrs should print
302 /// after these passes.
303 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
307 /// addPreSched2 - This method may be implemented by targets that want to
308 /// run passes after prolog-epilog insertion and before the second instruction
309 /// scheduling pass. This should return true if -print-machineinstrs should
310 /// print after these passes.
311 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
315 /// addPreEmitPass - This pass may be implemented by targets that want to run
316 /// passes immediately before machine code is emitted. This should return
317 /// true if -print-machineinstrs should print out the code after the passes.
318 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
323 /// addCodeEmitter - This pass should be overridden by the target to add a
324 /// code emitter, if supported. If this is not supported, 'true' should be
326 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
331 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
332 /// on this target. User flag overrides.
333 virtual bool getEnableTailMergeDefault() const { return true; }
336 } // End llvm namespace