1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/Target/TargetInstrItineraries.h"
26 class TargetSubtarget;
27 class TargetInstrInfo;
28 class TargetIntrinsicInfo;
31 class TargetFrameInfo;
34 class TargetRegisterInfo;
35 class PassManagerBase;
38 class TargetELFWriterInfo;
39 class formatted_raw_ostream;
41 // Relocation model types.
46 PIC_, // Cannot be named PIC due to collision with -DPIC
62 // Code generation optimization level.
63 namespace CodeGenOpt {
72 //===----------------------------------------------------------------------===//
74 /// TargetMachine - Primary interface to the complete machine description for
75 /// the target machine. All target-specific information should be accessible
76 /// through this interface.
79 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
80 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
81 protected: // Can only create subclasses.
82 TargetMachine(const Target &);
84 /// getSubtargetImpl - virtual method implemented by subclasses that returns
85 /// a reference to that target's TargetSubtarget-derived member variable.
86 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
88 /// TheTarget - The Target that this machine was created for.
89 const Target &TheTarget;
91 /// AsmInfo - Contains target specific asm information.
93 const MCAsmInfo *AsmInfo;
96 virtual ~TargetMachine();
98 const Target &getTarget() const { return TheTarget; }
100 // Interfaces to the major aspects of target machine information:
101 // -- Instruction opcode and operand information
102 // -- Pipelines and scheduling information
103 // -- Stack frame information
104 // -- Selection DAG lowering information
106 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
107 virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
108 virtual TargetLowering *getTargetLowering() const { return 0; }
109 virtual const TargetData *getTargetData() const { return 0; }
111 /// getMCAsmInfo - Return target specific asm information.
113 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
115 /// getSubtarget - This method returns a pointer to the specified type of
116 /// TargetSubtarget. In debug builds, it verifies that the object being
117 /// returned is of the correct type.
118 template<typename STC> const STC &getSubtarget() const {
119 return *static_cast<const STC*>(getSubtargetImpl());
122 /// getRegisterInfo - If register information is available, return it. If
123 /// not, return null. This is kept separate from RegInfo until RegInfo has
124 /// details of graph coloring register allocation removed from it.
126 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
128 /// getIntrinsicInfo - If intrinsic information is available, return it. If
129 /// not, return null.
131 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
133 /// getJITInfo - If this target supports a JIT, return information for it,
134 /// otherwise return null.
136 virtual TargetJITInfo *getJITInfo() { return 0; }
138 /// getInstrItineraryData - Returns instruction itinerary data for the target
139 /// or specific subtarget.
141 virtual const InstrItineraryData getInstrItineraryData() const {
142 return InstrItineraryData();
145 /// getELFWriterInfo - If this target supports an ELF writer, return
146 /// information for it, otherwise return null.
148 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
150 /// getRelocationModel - Returns the code generation relocation model. The
151 /// choices are static, PIC, and dynamic-no-pic, and target default.
152 static Reloc::Model getRelocationModel();
154 /// setRelocationModel - Sets the code generation relocation model.
156 static void setRelocationModel(Reloc::Model Model);
158 /// getCodeModel - Returns the code model. The choices are small, kernel,
159 /// medium, large, and target default.
160 static CodeModel::Model getCodeModel();
162 /// setCodeModel - Sets the code model.
164 static void setCodeModel(CodeModel::Model Model);
166 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
168 static bool getAsmVerbosityDefault();
170 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
172 static void setAsmVerbosityDefault(bool);
174 /// CodeGenFileType - These enums are meant to be passed into
175 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
176 /// it to indicate what type of file could actually be made.
177 enum CodeGenFileType {
180 CGFT_Null // Do not emit any output.
183 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
184 /// on this target. User flag overrides.
185 virtual bool getEnableTailMergeDefault() const { return true; }
187 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
188 /// specified file emitted. Typically this will involve several steps of code
189 /// generation. This method should return true if emission of this file type
190 /// is not supported, or false on success.
191 virtual bool addPassesToEmitFile(PassManagerBase &,
192 formatted_raw_ostream &,
199 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
200 /// get machine code emitted. This uses a JITCodeEmitter object to handle
201 /// actually outputting the machine code and resolving things like the address
202 /// of functions. This method returns true if machine code emission is
205 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
212 /// addPassesToEmitWholeFile - This method can be implemented by targets that
213 /// require having the entire module at once. This is not recommended, do not
215 virtual bool WantsWholeFile() const { return false; }
216 virtual bool addPassesToEmitWholeFile(PassManager &, formatted_raw_ostream &,
224 /// LLVMTargetMachine - This class describes a target machine that is
225 /// implemented with the LLVM target-independent code generator.
227 class LLVMTargetMachine : public TargetMachine {
228 std::string TargetTriple;
230 protected: // Can only create subclasses.
231 LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
234 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
235 /// both emitting to assembly files or machine code output.
237 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
238 bool DisableVerify, MCContext *&OutCtx);
240 virtual void setCodeModelForJIT();
241 virtual void setCodeModelForStatic();
245 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
246 /// specified file emitted. Typically this will involve several steps of code
247 /// generation. If OptLevel is None, the code generator should emit code as
248 /// fast as possible, though the generated code may be less efficient.
249 virtual bool addPassesToEmitFile(PassManagerBase &PM,
250 formatted_raw_ostream &Out,
251 CodeGenFileType FileType,
253 bool DisableVerify = true);
255 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
256 /// get machine code emitted. This uses a JITCodeEmitter object to handle
257 /// actually outputting the machine code and resolving things like the address
258 /// of functions. This method returns true if machine code emission is
261 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
264 bool DisableVerify = true);
266 /// Target-Independent Code Generator Pass Configuration Options.
268 /// addInstSelector - This method should add any "last minute" LLVM->LLVM
269 /// passes, then install an instruction selector pass, which converts from
270 /// LLVM code to machine instructions.
271 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
275 /// addPreRegAlloc - This method may be implemented by targets that want to
276 /// run passes immediately before register allocation. This should return
277 /// true if -print-machineinstrs should print after these passes.
278 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
282 /// addPostRegAlloc - This method may be implemented by targets that want
283 /// to run passes after register allocation but before prolog-epilog
284 /// insertion. This should return true if -print-machineinstrs should print
285 /// after these passes.
286 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
290 /// addPreSched2 - This method may be implemented by targets that want to
291 /// run passes after prolog-epilog insertion and before the second instruction
292 /// scheduling pass. This should return true if -print-machineinstrs should
293 /// print after these passes.
294 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
298 /// addPreEmitPass - This pass may be implemented by targets that want to run
299 /// passes immediately before machine code is emitted. This should return
300 /// true if -print-machineinstrs should print out the code after the passes.
301 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
306 /// addCodeEmitter - This pass should be overridden by the target to add a
307 /// code emitter, if supported. If this is not supported, 'true' should be
309 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
314 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
315 /// on this target. User flag overrides.
316 virtual bool getEnableTailMergeDefault() const { return true; }
319 } // End llvm namespace