1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the general parts of a Target machine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/Target/TargetData.h"
22 class TargetInstrInfo;
23 class TargetInstrDescriptor;
25 class TargetSchedInfo;
27 class TargetFrameInfo;
28 class TargetCacheInfo;
29 class MachineCodeEmitter;
31 class FunctionPassManager;
35 //===----------------------------------------------------------------------===//
37 /// TargetMachine - Primary interface to the complete machine description for
38 /// the target machine. All target-specific information should be accessible
39 /// through this interface.
42 const std::string Name;
43 const TargetData DataLayout; // Calculates type size & alignment
45 TargetMachine(const TargetMachine&); // DO NOT IMPLEMENT
46 void operator=(const TargetMachine&); // DO NOT IMPLEMENT
48 TargetMachine(const std::string &name, // Can only create subclasses...
49 bool LittleEndian = false,
50 unsigned char PtrSize = 8, unsigned char PtrAl = 8,
51 unsigned char DoubleAl = 8, unsigned char FloatAl = 4,
52 unsigned char LongAl = 8, unsigned char IntAl = 4,
53 unsigned char ShortAl = 2, unsigned char ByteAl = 1)
54 : Name(name), DataLayout(name, LittleEndian,
55 PtrSize, PtrAl, DoubleAl, FloatAl, LongAl,
56 IntAl, ShortAl, ByteAl) {}
58 virtual ~TargetMachine() {}
60 const std::string &getName() const { return Name; }
62 // Interfaces to the major aspects of target machine information:
63 // -- Instruction opcode and operand information
64 // -- Pipelines and scheduling information
65 // -- Register information
66 // -- Stack frame information
67 // -- Cache hierarchy information
68 // -- Machine-level optimization information (peephole only)
70 virtual const TargetInstrInfo& getInstrInfo() const = 0;
71 virtual const TargetSchedInfo& getSchedInfo() const = 0;
72 virtual const TargetRegInfo& getRegInfo() const = 0;
73 virtual const TargetFrameInfo& getFrameInfo() const = 0;
74 virtual const TargetCacheInfo& getCacheInfo() const = 0;
75 const TargetData &getTargetData() const { return DataLayout; }
77 /// getRegisterInfo - If register information is available, return it. If
78 /// not, return null. This is kept separate from RegInfo until RegInfo has
79 /// details of graph coloring register allocation removed from it.
81 virtual const MRegisterInfo* getRegisterInfo() const { return 0; }
83 /// getJITInfo - If this target supports a JIT, return information for it,
84 /// otherwise return null.
86 virtual TargetJITInfo *getJITInfo() { return 0; }
88 // Data storage information. FIXME, this should be moved out to sparc
91 virtual unsigned findOptimalStorageSize(const Type* ty) const;
93 /// addPassesToEmitAssembly - Add passes to the specified pass manager to get
94 /// assembly langage code emitted. Typically this will involve several steps
95 /// of code generation. This method should return true if assembly emission
98 virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out) {
102 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
103 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
104 /// actually outputting the machine code and resolving things like the address
105 /// of functions. This method should returns true if machine code emission is
108 virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
109 MachineCodeEmitter &MCE) {
114 } // End llvm namespace