1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/Target/TargetInstrItineraries.h"
26 class TargetSubtarget;
27 class TargetInstrInfo;
28 class TargetIntrinsicInfo;
31 class TargetSelectionDAGInfo;
32 class TargetFrameLowering;
35 class TargetRegisterInfo;
36 class PassManagerBase;
39 class TargetELFWriterInfo;
40 class formatted_raw_ostream;
42 // Relocation model types.
47 PIC_, // Cannot be named PIC due to collision with -DPIC
63 // Code generation optimization level.
64 namespace CodeGenOpt {
75 None, // No preference
76 Latency, // Scheduling for shortest total latency.
77 RegPressure, // Scheduling for lowest register pressure.
78 Hybrid, // Scheduling for both latency and register pressure.
79 ILP // Scheduling for ILP in low register pressure mode.
83 //===----------------------------------------------------------------------===//
85 /// TargetMachine - Primary interface to the complete machine description for
86 /// the target machine. All target-specific information should be accessible
87 /// through this interface.
90 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
91 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
92 protected: // Can only create subclasses.
93 TargetMachine(const Target &);
95 /// getSubtargetImpl - virtual method implemented by subclasses that returns
96 /// a reference to that target's TargetSubtarget-derived member variable.
97 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
99 /// TheTarget - The Target that this machine was created for.
100 const Target &TheTarget;
102 /// AsmInfo - Contains target specific asm information.
104 const MCAsmInfo *AsmInfo;
106 unsigned MCRelaxAll : 1;
107 unsigned MCUseLoc : 1;
110 virtual ~TargetMachine();
112 const Target &getTarget() const { return TheTarget; }
114 // Interfaces to the major aspects of target machine information:
115 // -- Instruction opcode and operand information
116 // -- Pipelines and scheduling information
117 // -- Stack frame information
118 // -- Selection DAG lowering information
120 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
121 virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
122 virtual const TargetLowering *getTargetLowering() const { return 0; }
123 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
124 virtual const TargetData *getTargetData() const { return 0; }
126 /// getMCAsmInfo - Return target specific asm information.
128 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
130 /// getSubtarget - This method returns a pointer to the specified type of
131 /// TargetSubtarget. In debug builds, it verifies that the object being
132 /// returned is of the correct type.
133 template<typename STC> const STC &getSubtarget() const {
134 return *static_cast<const STC*>(getSubtargetImpl());
137 /// getRegisterInfo - If register information is available, return it. If
138 /// not, return null. This is kept separate from RegInfo until RegInfo has
139 /// details of graph coloring register allocation removed from it.
141 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
143 /// getIntrinsicInfo - If intrinsic information is available, return it. If
144 /// not, return null.
146 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
148 /// getJITInfo - If this target supports a JIT, return information for it,
149 /// otherwise return null.
151 virtual TargetJITInfo *getJITInfo() { return 0; }
153 /// getInstrItineraryData - Returns instruction itinerary data for the target
154 /// or specific subtarget.
156 virtual const InstrItineraryData *getInstrItineraryData() const {
160 /// getELFWriterInfo - If this target supports an ELF writer, return
161 /// information for it, otherwise return null.
163 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
165 /// hasMCRelaxAll - Check whether all machine code instructions should be
167 bool hasMCRelaxAll() const { return MCRelaxAll; }
169 /// setMCRelaxAll - Set whether all machine code instructions should be
171 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
173 /// hasMCUseLoc - Check whether we should use dwarf's .loc directive.
174 bool hasMCUseLoc() const { return MCUseLoc; }
176 /// setMCUseLoc - Set whether all we should use dwarf's .loc directive.
177 void setMCUseLoc(bool Value) { MCUseLoc = Value; }
179 /// getRelocationModel - Returns the code generation relocation model. The
180 /// choices are static, PIC, and dynamic-no-pic, and target default.
181 static Reloc::Model getRelocationModel();
183 /// setRelocationModel - Sets the code generation relocation model.
185 static void setRelocationModel(Reloc::Model Model);
187 /// getCodeModel - Returns the code model. The choices are small, kernel,
188 /// medium, large, and target default.
189 static CodeModel::Model getCodeModel();
191 /// setCodeModel - Sets the code model.
193 static void setCodeModel(CodeModel::Model Model);
195 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
197 static bool getAsmVerbosityDefault();
199 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
201 static void setAsmVerbosityDefault(bool);
203 /// getDataSections - Return true if data objects should be emitted into their
204 /// own section, corresponds to -fdata-sections.
205 static bool getDataSections();
207 /// getFunctionSections - Return true if functions should be emitted into
208 /// their own section, corresponding to -ffunction-sections.
209 static bool getFunctionSections();
211 /// setDataSections - Set if the data are emit into separate sections.
212 static void setDataSections(bool);
214 /// setFunctionSections - Set if the functions are emit into separate
216 static void setFunctionSections(bool);
218 /// CodeGenFileType - These enums are meant to be passed into
219 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
220 /// it to indicate what type of file could actually be made.
221 enum CodeGenFileType {
224 CGFT_Null // Do not emit any output.
227 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
228 /// on this target. User flag overrides.
229 virtual bool getEnableTailMergeDefault() const { return true; }
231 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
232 /// specified file emitted. Typically this will involve several steps of code
233 /// generation. This method should return true if emission of this file type
234 /// is not supported, or false on success.
235 virtual bool addPassesToEmitFile(PassManagerBase &,
236 formatted_raw_ostream &,
243 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
244 /// get machine code emitted. This uses a JITCodeEmitter object to handle
245 /// actually outputting the machine code and resolving things like the address
246 /// of functions. This method returns true if machine code emission is
249 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
256 /// addPassesToEmitMC - Add passes to the specified pass manager to get
257 /// machine code emitted with the MCJIT. This method returns true if machine
258 /// code is not supported. It fills the MCContext Ctx pointer which can be
259 /// used to build custom MCStreamer.
261 virtual bool addPassesToEmitMC(PassManagerBase &,
269 /// LLVMTargetMachine - This class describes a target machine that is
270 /// implemented with the LLVM target-independent code generator.
272 class LLVMTargetMachine : public TargetMachine {
273 std::string TargetTriple;
275 protected: // Can only create subclasses.
276 LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
279 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
280 /// both emitting to assembly files or machine code output.
282 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
283 bool DisableVerify, MCContext *&OutCtx);
285 virtual void setCodeModelForJIT();
286 virtual void setCodeModelForStatic();
290 const std::string &getTargetTriple() const { return TargetTriple; }
292 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
293 /// specified file emitted. Typically this will involve several steps of code
294 /// generation. If OptLevel is None, the code generator should emit code as
295 /// fast as possible, though the generated code may be less efficient.
296 virtual bool addPassesToEmitFile(PassManagerBase &PM,
297 formatted_raw_ostream &Out,
298 CodeGenFileType FileType,
300 bool DisableVerify = true);
302 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
303 /// get machine code emitted. This uses a JITCodeEmitter object to handle
304 /// actually outputting the machine code and resolving things like the address
305 /// of functions. This method returns true if machine code emission is
308 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
311 bool DisableVerify = true);
313 /// addPassesToEmitMC - Add passes to the specified pass manager to get
314 /// machine code emitted with the MCJIT. This method returns true if machine
315 /// code is not supported. It fills the MCContext Ctx pointer which can be
316 /// used to build custom MCStreamer.
318 virtual bool addPassesToEmitMC(PassManagerBase &PM,
320 CodeGenOpt::Level OptLevel,
321 bool DisableVerify = true);
323 /// Target-Independent Code Generator Pass Configuration Options.
325 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
326 /// passes (which are run just before instruction selector).
327 virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
331 /// addInstSelector - This method should install an instruction selector pass,
332 /// which converts from LLVM code to machine instructions.
333 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
337 /// addPreRegAlloc - This method may be implemented by targets that want to
338 /// run passes immediately before register allocation. This should return
339 /// true if -print-machineinstrs should print after these passes.
340 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
344 /// addPostRegAlloc - This method may be implemented by targets that want
345 /// to run passes after register allocation but before prolog-epilog
346 /// insertion. This should return true if -print-machineinstrs should print
347 /// after these passes.
348 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
352 /// addPreSched2 - This method may be implemented by targets that want to
353 /// run passes after prolog-epilog insertion and before the second instruction
354 /// scheduling pass. This should return true if -print-machineinstrs should
355 /// print after these passes.
356 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
360 /// addPreEmitPass - This pass may be implemented by targets that want to run
361 /// passes immediately before machine code is emitted. This should return
362 /// true if -print-machineinstrs should print out the code after the passes.
363 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
368 /// addCodeEmitter - This pass should be overridden by the target to add a
369 /// code emitter, if supported. If this is not supported, 'true' should be
371 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
376 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
377 /// on this target. User flag overrides.
378 virtual bool getEnableTailMergeDefault() const { return true; }
381 } // End llvm namespace