1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/Target/TargetInstrItineraries.h"
26 class TargetSubtarget;
27 class TargetInstrInfo;
28 class TargetIntrinsicInfo;
31 class TargetSelectionDAGInfo;
32 class TargetFrameLowering;
35 class TargetRegisterInfo;
36 class PassManagerBase;
39 class TargetELFWriterInfo;
40 class formatted_raw_ostream;
43 // Relocation model types.
48 PIC_, // Cannot be named PIC due to collision with -DPIC
64 // Code generation optimization level.
65 namespace CodeGenOpt {
76 None, // No preference
77 Latency, // Scheduling for shortest total latency.
78 RegPressure, // Scheduling for lowest register pressure.
79 Hybrid, // Scheduling for both latency and register pressure.
80 ILP // Scheduling for ILP in low register pressure mode.
84 //===----------------------------------------------------------------------===//
86 /// TargetMachine - Primary interface to the complete machine description for
87 /// the target machine. All target-specific information should be accessible
88 /// through this interface.
91 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
92 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
93 protected: // Can only create subclasses.
94 TargetMachine(const Target &);
96 /// getSubtargetImpl - virtual method implemented by subclasses that returns
97 /// a reference to that target's TargetSubtarget-derived member variable.
98 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
100 /// TheTarget - The Target that this machine was created for.
101 const Target &TheTarget;
103 /// AsmInfo - Contains target specific asm information.
105 const MCAsmInfo *AsmInfo;
107 unsigned MCRelaxAll : 1;
108 unsigned MCNoExecStack : 1;
109 unsigned MCUseLoc : 1;
112 virtual ~TargetMachine();
114 const Target &getTarget() const { return TheTarget; }
116 // Interfaces to the major aspects of target machine information:
117 // -- Instruction opcode and operand information
118 // -- Pipelines and scheduling information
119 // -- Stack frame information
120 // -- Selection DAG lowering information
122 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
123 virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
124 virtual const TargetLowering *getTargetLowering() const { return 0; }
125 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
126 virtual const TargetData *getTargetData() const { return 0; }
128 /// getMCAsmInfo - Return target specific asm information.
130 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
132 /// getSubtarget - This method returns a pointer to the specified type of
133 /// TargetSubtarget. In debug builds, it verifies that the object being
134 /// returned is of the correct type.
135 template<typename STC> const STC &getSubtarget() const {
136 return *static_cast<const STC*>(getSubtargetImpl());
139 /// getRegisterInfo - If register information is available, return it. If
140 /// not, return null. This is kept separate from RegInfo until RegInfo has
141 /// details of graph coloring register allocation removed from it.
143 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
145 /// getIntrinsicInfo - If intrinsic information is available, return it. If
146 /// not, return null.
148 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
150 /// getJITInfo - If this target supports a JIT, return information for it,
151 /// otherwise return null.
153 virtual TargetJITInfo *getJITInfo() { return 0; }
155 /// getInstrItineraryData - Returns instruction itinerary data for the target
156 /// or specific subtarget.
158 virtual const InstrItineraryData *getInstrItineraryData() const {
162 /// getELFWriterInfo - If this target supports an ELF writer, return
163 /// information for it, otherwise return null.
165 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
167 /// hasMCRelaxAll - Check whether all machine code instructions should be
169 bool hasMCRelaxAll() const { return MCRelaxAll; }
171 /// setMCRelaxAll - Set whether all machine code instructions should be
173 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
175 /// hasMCNoExecStack - Check whether an executable stack is not needed.
176 bool hasMCNoExecStack() const { return MCNoExecStack; }
178 /// setMCNoExecStack - Set whether an executabel stack is not needed.
179 void setMCNoExecStack(bool Value) { MCNoExecStack = Value; }
181 /// hasMCUseLoc - Check whether we should use dwarf's .loc directive.
182 bool hasMCUseLoc() const { return MCUseLoc; }
184 /// setMCUseLoc - Set whether all we should use dwarf's .loc directive.
185 void setMCUseLoc(bool Value) { MCUseLoc = Value; }
187 /// getRelocationModel - Returns the code generation relocation model. The
188 /// choices are static, PIC, and dynamic-no-pic, and target default.
189 static Reloc::Model getRelocationModel();
191 /// setRelocationModel - Sets the code generation relocation model.
193 static void setRelocationModel(Reloc::Model Model);
195 /// getCodeModel - Returns the code model. The choices are small, kernel,
196 /// medium, large, and target default.
197 static CodeModel::Model getCodeModel();
199 /// setCodeModel - Sets the code model.
201 static void setCodeModel(CodeModel::Model Model);
203 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
205 static bool getAsmVerbosityDefault();
207 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
209 static void setAsmVerbosityDefault(bool);
211 /// getDataSections - Return true if data objects should be emitted into their
212 /// own section, corresponds to -fdata-sections.
213 static bool getDataSections();
215 /// getFunctionSections - Return true if functions should be emitted into
216 /// their own section, corresponding to -ffunction-sections.
217 static bool getFunctionSections();
219 /// setDataSections - Set if the data are emit into separate sections.
220 static void setDataSections(bool);
222 /// setFunctionSections - Set if the functions are emit into separate
224 static void setFunctionSections(bool);
226 /// CodeGenFileType - These enums are meant to be passed into
227 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
228 /// it to indicate what type of file could actually be made.
229 enum CodeGenFileType {
232 CGFT_Null // Do not emit any output.
235 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
236 /// on this target. User flag overrides.
237 virtual bool getEnableTailMergeDefault() const { return true; }
239 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
240 /// specified file emitted. Typically this will involve several steps of code
241 /// generation. This method should return true if emission of this file type
242 /// is not supported, or false on success.
243 virtual bool addPassesToEmitFile(PassManagerBase &,
244 formatted_raw_ostream &,
251 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
252 /// get machine code emitted. This uses a JITCodeEmitter object to handle
253 /// actually outputting the machine code and resolving things like the address
254 /// of functions. This method returns true if machine code emission is
257 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
264 /// addPassesToEmitMC - Add passes to the specified pass manager to get
265 /// machine code emitted with the MCJIT. This method returns true if machine
266 /// code is not supported. It fills the MCContext Ctx pointer which can be
267 /// used to build custom MCStreamer.
269 virtual bool addPassesToEmitMC(PassManagerBase &,
278 /// LLVMTargetMachine - This class describes a target machine that is
279 /// implemented with the LLVM target-independent code generator.
281 class LLVMTargetMachine : public TargetMachine {
282 std::string TargetTriple;
284 protected: // Can only create subclasses.
285 LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
288 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
289 /// both emitting to assembly files or machine code output.
291 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
292 bool DisableVerify, MCContext *&OutCtx);
294 virtual void setCodeModelForJIT();
295 virtual void setCodeModelForStatic();
299 const std::string &getTargetTriple() const { return TargetTriple; }
301 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
302 /// specified file emitted. Typically this will involve several steps of code
303 /// generation. If OptLevel is None, the code generator should emit code as
304 /// fast as possible, though the generated code may be less efficient.
305 virtual bool addPassesToEmitFile(PassManagerBase &PM,
306 formatted_raw_ostream &Out,
307 CodeGenFileType FileType,
309 bool DisableVerify = true);
311 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
312 /// get machine code emitted. This uses a JITCodeEmitter object to handle
313 /// actually outputting the machine code and resolving things like the address
314 /// of functions. This method returns true if machine code emission is
317 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
320 bool DisableVerify = true);
322 /// addPassesToEmitMC - Add passes to the specified pass manager to get
323 /// machine code emitted with the MCJIT. This method returns true if machine
324 /// code is not supported. It fills the MCContext Ctx pointer which can be
325 /// used to build custom MCStreamer.
327 virtual bool addPassesToEmitMC(PassManagerBase &PM,
330 CodeGenOpt::Level OptLevel,
331 bool DisableVerify = true);
333 /// Target-Independent Code Generator Pass Configuration Options.
335 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
336 /// passes (which are run just before instruction selector).
337 virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
341 /// addInstSelector - This method should install an instruction selector pass,
342 /// which converts from LLVM code to machine instructions.
343 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
347 /// addPreRegAlloc - This method may be implemented by targets that want to
348 /// run passes immediately before register allocation. This should return
349 /// true if -print-machineinstrs should print after these passes.
350 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
354 /// addPostRegAlloc - This method may be implemented by targets that want
355 /// to run passes after register allocation but before prolog-epilog
356 /// insertion. This should return true if -print-machineinstrs should print
357 /// after these passes.
358 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
362 /// addPreSched2 - This method may be implemented by targets that want to
363 /// run passes after prolog-epilog insertion and before the second instruction
364 /// scheduling pass. This should return true if -print-machineinstrs should
365 /// print after these passes.
366 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
370 /// addPreEmitPass - This pass may be implemented by targets that want to run
371 /// passes immediately before machine code is emitted. This should return
372 /// true if -print-machineinstrs should print out the code after the passes.
373 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
378 /// addCodeEmitter - This pass should be overridden by the target to add a
379 /// code emitter, if supported. If this is not supported, 'true' should be
381 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
386 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
387 /// on this target. User flag overrides.
388 virtual bool getEnableTailMergeDefault() const { return true; }
391 } // End llvm namespace