1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/MC/MCCodeGenInfo.h"
18 #include "llvm/ADT/StringRef.h"
24 class InstrItineraryData;
31 class PassManagerBase;
34 class TargetELFWriterInfo;
35 class TargetFrameLowering;
36 class TargetInstrInfo;
37 class TargetIntrinsicInfo;
40 class TargetRegisterInfo;
41 class TargetSelectionDAGInfo;
42 class TargetSubtargetInfo;
43 class formatted_raw_ostream;
57 // Code generation optimization level.
58 namespace CodeGenOpt {
69 None, // No preference
70 Latency, // Scheduling for shortest total latency.
71 RegPressure, // Scheduling for lowest register pressure.
72 Hybrid, // Scheduling for both latency and register pressure.
73 ILP // Scheduling for ILP in low register pressure mode.
77 //===----------------------------------------------------------------------===//
79 /// TargetMachine - Primary interface to the complete machine description for
80 /// the target machine. All target-specific information should be accessible
81 /// through this interface.
84 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
85 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
86 protected: // Can only create subclasses.
87 TargetMachine(const Target &T, StringRef TargetTriple,
88 StringRef CPU, StringRef FS);
90 /// getSubtargetImpl - virtual method implemented by subclasses that returns
91 /// a reference to that target's TargetSubtargetInfo-derived member variable.
92 virtual const TargetSubtargetInfo *getSubtargetImpl() const { return 0; }
94 /// TheTarget - The Target that this machine was created for.
95 const Target &TheTarget;
97 /// TargetTriple, TargetCPU, TargetFS - Triple string, CPU name, and target
98 /// feature strings the TargetMachine instance is created with.
99 std::string TargetTriple;
100 std::string TargetCPU;
101 std::string TargetFS;
103 /// CodeGenInfo - Low level target information such as relocation model.
105 const MCCodeGenInfo *CodeGenInfo;
107 /// AsmInfo - Contains target specific asm information.
109 const MCAsmInfo *AsmInfo;
111 unsigned MCRelaxAll : 1;
112 unsigned MCNoExecStack : 1;
113 unsigned MCSaveTempLabels : 1;
114 unsigned MCUseLoc : 1;
115 unsigned MCUseCFI : 1;
118 virtual ~TargetMachine();
120 const Target &getTarget() const { return TheTarget; }
122 const StringRef getTargetTriple() const { return TargetTriple; }
123 const StringRef getTargetCPU() const { return TargetCPU; }
124 const StringRef getTargetFeatureString() const { return TargetFS; }
126 // Interfaces to the major aspects of target machine information:
127 // -- Instruction opcode and operand information
128 // -- Pipelines and scheduling information
129 // -- Stack frame information
130 // -- Selection DAG lowering information
132 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
133 virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
134 virtual const TargetLowering *getTargetLowering() const { return 0; }
135 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
136 virtual const TargetData *getTargetData() const { return 0; }
138 /// getMCAsmInfo - Return target specific asm information.
140 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
142 /// getSubtarget - This method returns a pointer to the specified type of
143 /// TargetSubtargetInfo. In debug builds, it verifies that the object being
144 /// returned is of the correct type.
145 template<typename STC> const STC &getSubtarget() const {
146 return *static_cast<const STC*>(getSubtargetImpl());
149 /// getRegisterInfo - If register information is available, return it. If
150 /// not, return null. This is kept separate from RegInfo until RegInfo has
151 /// details of graph coloring register allocation removed from it.
153 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
155 /// getIntrinsicInfo - If intrinsic information is available, return it. If
156 /// not, return null.
158 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
160 /// getJITInfo - If this target supports a JIT, return information for it,
161 /// otherwise return null.
163 virtual TargetJITInfo *getJITInfo() { return 0; }
165 /// getInstrItineraryData - Returns instruction itinerary data for the target
166 /// or specific subtarget.
168 virtual const InstrItineraryData *getInstrItineraryData() const {
172 /// getELFWriterInfo - If this target supports an ELF writer, return
173 /// information for it, otherwise return null.
175 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
177 /// hasMCRelaxAll - Check whether all machine code instructions should be
179 bool hasMCRelaxAll() const { return MCRelaxAll; }
181 /// setMCRelaxAll - Set whether all machine code instructions should be
183 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
185 /// hasMCSaveTempLabels - Check whether temporary labels will be preserved
186 /// (i.e., not treated as temporary).
187 bool hasMCSaveTempLabels() const { return MCSaveTempLabels; }
189 /// setMCSaveTempLabels - Set whether temporary labels will be preserved
190 /// (i.e., not treated as temporary).
191 void setMCSaveTempLabels(bool Value) { MCSaveTempLabels = Value; }
193 /// hasMCNoExecStack - Check whether an executable stack is not needed.
194 bool hasMCNoExecStack() const { return MCNoExecStack; }
196 /// setMCNoExecStack - Set whether an executabel stack is not needed.
197 void setMCNoExecStack(bool Value) { MCNoExecStack = Value; }
199 /// hasMCUseLoc - Check whether we should use dwarf's .loc directive.
200 bool hasMCUseLoc() const { return MCUseLoc; }
202 /// setMCUseLoc - Set whether all we should use dwarf's .loc directive.
203 void setMCUseLoc(bool Value) { MCUseLoc = Value; }
205 /// hasMCUseCFI - Check whether we should use dwarf's .cfi_* directives.
206 bool hasMCUseCFI() const { return MCUseCFI; }
208 /// setMCUseCFI - Set whether all we should use dwarf's .cfi_* directives.
209 void setMCUseCFI(bool Value) { MCUseCFI = Value; }
211 /// getRelocationModel - Returns the code generation relocation model. The
212 /// choices are static, PIC, and dynamic-no-pic, and target default.
213 Reloc::Model getRelocationModel() const;
215 /// getCodeModel - Returns the code model. The choices are small, kernel,
216 /// medium, large, and target default.
217 static CodeModel::Model getCodeModel();
219 /// setCodeModel - Sets the code model.
221 static void setCodeModel(CodeModel::Model Model);
223 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
225 static bool getAsmVerbosityDefault();
227 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
229 static void setAsmVerbosityDefault(bool);
231 /// getDataSections - Return true if data objects should be emitted into their
232 /// own section, corresponds to -fdata-sections.
233 static bool getDataSections();
235 /// getFunctionSections - Return true if functions should be emitted into
236 /// their own section, corresponding to -ffunction-sections.
237 static bool getFunctionSections();
239 /// setDataSections - Set if the data are emit into separate sections.
240 static void setDataSections(bool);
242 /// setFunctionSections - Set if the functions are emit into separate
244 static void setFunctionSections(bool);
246 /// CodeGenFileType - These enums are meant to be passed into
247 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
248 /// it to indicate what type of file could actually be made.
249 enum CodeGenFileType {
252 CGFT_Null // Do not emit any output.
255 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
256 /// on this target. User flag overrides.
257 virtual bool getEnableTailMergeDefault() const { return true; }
259 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
260 /// specified file emitted. Typically this will involve several steps of code
261 /// generation. This method should return true if emission of this file type
262 /// is not supported, or false on success.
263 virtual bool addPassesToEmitFile(PassManagerBase &,
264 formatted_raw_ostream &,
271 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
272 /// get machine code emitted. This uses a JITCodeEmitter object to handle
273 /// actually outputting the machine code and resolving things like the address
274 /// of functions. This method returns true if machine code emission is
277 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
284 /// addPassesToEmitMC - Add passes to the specified pass manager to get
285 /// machine code emitted with the MCJIT. This method returns true if machine
286 /// code is not supported. It fills the MCContext Ctx pointer which can be
287 /// used to build custom MCStreamer.
289 virtual bool addPassesToEmitMC(PassManagerBase &,
298 /// LLVMTargetMachine - This class describes a target machine that is
299 /// implemented with the LLVM target-independent code generator.
301 class LLVMTargetMachine : public TargetMachine {
302 protected: // Can only create subclasses.
303 LLVMTargetMachine(const Target &T, StringRef TargetTriple,
304 StringRef CPU, StringRef FS, Reloc::Model RM);
307 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
308 /// both emitting to assembly files or machine code output.
310 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
311 bool DisableVerify, MCContext *&OutCtx);
313 virtual void setCodeModelForJIT();
314 virtual void setCodeModelForStatic();
317 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
318 /// specified file emitted. Typically this will involve several steps of code
319 /// generation. If OptLevel is None, the code generator should emit code as
320 /// fast as possible, though the generated code may be less efficient.
321 virtual bool addPassesToEmitFile(PassManagerBase &PM,
322 formatted_raw_ostream &Out,
323 CodeGenFileType FileType,
325 bool DisableVerify = true);
327 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
328 /// get machine code emitted. This uses a JITCodeEmitter object to handle
329 /// actually outputting the machine code and resolving things like the address
330 /// of functions. This method returns true if machine code emission is
333 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
336 bool DisableVerify = true);
338 /// addPassesToEmitMC - Add passes to the specified pass manager to get
339 /// machine code emitted with the MCJIT. This method returns true if machine
340 /// code is not supported. It fills the MCContext Ctx pointer which can be
341 /// used to build custom MCStreamer.
343 virtual bool addPassesToEmitMC(PassManagerBase &PM,
346 CodeGenOpt::Level OptLevel,
347 bool DisableVerify = true);
349 /// Target-Independent Code Generator Pass Configuration Options.
351 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
352 /// passes (which are run just before instruction selector).
353 virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
357 /// addInstSelector - This method should install an instruction selector pass,
358 /// which converts from LLVM code to machine instructions.
359 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
363 /// addPreRegAlloc - This method may be implemented by targets that want to
364 /// run passes immediately before register allocation. This should return
365 /// true if -print-machineinstrs should print after these passes.
366 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
370 /// addPostRegAlloc - This method may be implemented by targets that want
371 /// to run passes after register allocation but before prolog-epilog
372 /// insertion. This should return true if -print-machineinstrs should print
373 /// after these passes.
374 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
378 /// addPreSched2 - This method may be implemented by targets that want to
379 /// run passes after prolog-epilog insertion and before the second instruction
380 /// scheduling pass. This should return true if -print-machineinstrs should
381 /// print after these passes.
382 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
386 /// addPreEmitPass - This pass may be implemented by targets that want to run
387 /// passes immediately before machine code is emitted. This should return
388 /// true if -print-machineinstrs should print out the code after the passes.
389 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
394 /// addCodeEmitter - This pass should be overridden by the target to add a
395 /// code emitter, if supported. If this is not supported, 'true' should be
397 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
402 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
403 /// on this target. User flag overrides.
404 virtual bool getEnableTailMergeDefault() const { return true; }
407 } // End llvm namespace