1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/Target/TargetInstrItineraries.h"
26 class TargetSubtarget;
27 class TargetInstrInfo;
28 class TargetIntrinsicInfo;
31 class TargetFrameInfo;
33 class TargetRegisterInfo;
34 class PassManagerBase;
37 class TargetELFWriterInfo;
38 class formatted_raw_ostream;
40 // Relocation model types.
45 PIC_, // Cannot be named PIC due to collision with -DPIC
61 // Code generation optimization level.
62 namespace CodeGenOpt {
71 //===----------------------------------------------------------------------===//
73 /// TargetMachine - Primary interface to the complete machine description for
74 /// the target machine. All target-specific information should be accessible
75 /// through this interface.
78 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
79 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
80 protected: // Can only create subclasses.
81 TargetMachine(const Target &);
83 /// getSubtargetImpl - virtual method implemented by subclasses that returns
84 /// a reference to that target's TargetSubtarget-derived member variable.
85 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
87 /// TheTarget - The Target that this machine was created for.
88 const Target &TheTarget;
90 /// AsmInfo - Contains target specific asm information.
92 const MCAsmInfo *AsmInfo;
95 virtual ~TargetMachine();
97 const Target &getTarget() const { return TheTarget; }
99 // Interfaces to the major aspects of target machine information:
100 // -- Instruction opcode and operand information
101 // -- Pipelines and scheduling information
102 // -- Stack frame information
103 // -- Selection DAG lowering information
105 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
106 virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
107 virtual TargetLowering *getTargetLowering() const { return 0; }
108 virtual const TargetData *getTargetData() const { return 0; }
110 /// getMCAsmInfo - Return target specific asm information.
112 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
114 /// getSubtarget - This method returns a pointer to the specified type of
115 /// TargetSubtarget. In debug builds, it verifies that the object being
116 /// returned is of the correct type.
117 template<typename STC> const STC &getSubtarget() const {
118 return *static_cast<const STC*>(getSubtargetImpl());
121 /// getRegisterInfo - If register information is available, return it. If
122 /// not, return null. This is kept separate from RegInfo until RegInfo has
123 /// details of graph coloring register allocation removed from it.
125 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
127 /// getIntrinsicInfo - If intrinsic information is available, return it. If
128 /// not, return null.
130 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
132 /// getJITInfo - If this target supports a JIT, return information for it,
133 /// otherwise return null.
135 virtual TargetJITInfo *getJITInfo() { return 0; }
137 /// getInstrItineraryData - Returns instruction itinerary data for the target
138 /// or specific subtarget.
140 virtual const InstrItineraryData getInstrItineraryData() const {
141 return InstrItineraryData();
144 /// getELFWriterInfo - If this target supports an ELF writer, return
145 /// information for it, otherwise return null.
147 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
149 /// getRelocationModel - Returns the code generation relocation model. The
150 /// choices are static, PIC, and dynamic-no-pic, and target default.
151 static Reloc::Model getRelocationModel();
153 /// setRelocationModel - Sets the code generation relocation model.
155 static void setRelocationModel(Reloc::Model Model);
157 /// getCodeModel - Returns the code model. The choices are small, kernel,
158 /// medium, large, and target default.
159 static CodeModel::Model getCodeModel();
161 /// setCodeModel - Sets the code model.
163 static void setCodeModel(CodeModel::Model Model);
165 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
167 static bool getAsmVerbosityDefault();
169 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
171 static void setAsmVerbosityDefault(bool);
173 /// CodeGenFileType - These enums are meant to be passed into
174 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
175 /// it to indicate what type of file could actually be made.
176 enum CodeGenFileType {
179 CGFT_Null // Do not emit any output.
182 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
183 /// on this target. User flag overrides.
184 virtual bool getEnableTailMergeDefault() const { return true; }
186 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
187 /// specified file emitted. Typically this will involve several steps of code
188 /// generation. This method should return true if emission of this file type
189 /// is not supported, or false on success.
190 virtual bool addPassesToEmitFile(PassManagerBase &,
191 formatted_raw_ostream &,
192 CodeGenFileType Filetype,
197 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
198 /// get machine code emitted. This uses a JITCodeEmitter object to handle
199 /// actually outputting the machine code and resolving things like the address
200 /// of functions. This method returns true if machine code emission is
203 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
209 /// addPassesToEmitWholeFile - This method can be implemented by targets that
210 /// require having the entire module at once. This is not recommended, do not
212 virtual bool WantsWholeFile() const { return false; }
213 virtual bool addPassesToEmitWholeFile(PassManager &, formatted_raw_ostream &,
220 /// LLVMTargetMachine - This class describes a target machine that is
221 /// implemented with the LLVM target-independent code generator.
223 class LLVMTargetMachine : public TargetMachine {
224 protected: // Can only create subclasses.
225 LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
227 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
228 /// both emitting to assembly files or machine code output.
230 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level);
233 virtual void setCodeModelForJIT();
234 virtual void setCodeModelForStatic();
238 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
239 /// specified file emitted. Typically this will involve several steps of code
240 /// generation. If OptLevel is None, the code generator should emit code as
241 /// fast as possible, though the generated code may be less efficient.
242 virtual bool addPassesToEmitFile(PassManagerBase &PM,
243 formatted_raw_ostream &Out,
244 CodeGenFileType FileType,
247 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
248 /// get machine code emitted. This uses a JITCodeEmitter object to handle
249 /// actually outputting the machine code and resolving things like the address
250 /// of functions. This method returns true if machine code emission is
253 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
257 /// Target-Independent Code Generator Pass Configuration Options.
259 /// addInstSelector - This method should add any "last minute" LLVM->LLVM
260 /// passes, then install an instruction selector pass, which converts from
261 /// LLVM code to machine instructions.
262 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
266 /// addPreRegAlloc - This method may be implemented by targets that want to
267 /// run passes immediately before register allocation. This should return
268 /// true if -print-machineinstrs should print after these passes.
269 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
273 /// addPostRegAlloc - This method may be implemented by targets that want
274 /// to run passes after register allocation but before prolog-epilog
275 /// insertion. This should return true if -print-machineinstrs should print
276 /// after these passes.
277 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
281 /// addPreSched2 - This method may be implemented by targets that want to
282 /// run passes after prolog-epilog insertion and before the second instruction
283 /// scheduling pass. This should return true if -print-machineinstrs should
284 /// print after these passes.
285 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
289 /// addPreEmitPass - This pass may be implemented by targets that want to run
290 /// passes immediately before machine code is emitted. This should return
291 /// true if -print-machineinstrs should print out the code after the passes.
292 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
297 /// addCodeEmitter - This pass should be overridden by the target to add a
298 /// code emitter, if supported. If this is not supported, 'true' should be
300 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
305 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
306 /// on this target. User flag overrides.
307 virtual bool getEnableTailMergeDefault() const { return true; }
310 } // End llvm namespace