1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
22 class InstrItineraryData;
28 class PassManagerBase;
31 class TargetELFWriterInfo;
32 class TargetFrameLowering;
33 class TargetInstrInfo;
34 class TargetIntrinsicInfo;
37 class TargetRegisterInfo;
38 class TargetSelectionDAGInfo;
39 class TargetSubtarget;
40 class formatted_raw_ostream;
43 // Relocation model types.
48 PIC_, // Cannot be named PIC due to collision with -DPIC
64 // Code generation optimization level.
65 namespace CodeGenOpt {
76 None, // No preference
77 Latency, // Scheduling for shortest total latency.
78 RegPressure, // Scheduling for lowest register pressure.
79 Hybrid, // Scheduling for both latency and register pressure.
80 ILP // Scheduling for ILP in low register pressure mode.
84 //===----------------------------------------------------------------------===//
86 /// TargetMachine - Primary interface to the complete machine description for
87 /// the target machine. All target-specific information should be accessible
88 /// through this interface.
91 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
92 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
93 protected: // Can only create subclasses.
94 TargetMachine(const Target &);
96 /// getSubtargetImpl - virtual method implemented by subclasses that returns
97 /// a reference to that target's TargetSubtarget-derived member variable.
98 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
100 /// TheTarget - The Target that this machine was created for.
101 const Target &TheTarget;
103 /// AsmInfo - Contains target specific asm information.
105 const MCAsmInfo *AsmInfo;
107 unsigned MCRelaxAll : 1;
108 unsigned MCNoExecStack : 1;
109 unsigned MCSaveTempLabels : 1;
110 unsigned MCUseLoc : 1;
111 unsigned MCUseCFI : 1;
114 virtual ~TargetMachine();
116 const Target &getTarget() const { return TheTarget; }
118 // Interfaces to the major aspects of target machine information:
119 // -- Instruction opcode and operand information
120 // -- Pipelines and scheduling information
121 // -- Stack frame information
122 // -- Selection DAG lowering information
124 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
125 virtual const TargetFrameLowering *getFrameLowering() const { return 0; }
126 virtual const TargetLowering *getTargetLowering() const { return 0; }
127 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; }
128 virtual const TargetData *getTargetData() const { return 0; }
130 /// getMCAsmInfo - Return target specific asm information.
132 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
134 /// getSubtarget - This method returns a pointer to the specified type of
135 /// TargetSubtarget. In debug builds, it verifies that the object being
136 /// returned is of the correct type.
137 template<typename STC> const STC &getSubtarget() const {
138 return *static_cast<const STC*>(getSubtargetImpl());
141 /// getRegisterInfo - If register information is available, return it. If
142 /// not, return null. This is kept separate from RegInfo until RegInfo has
143 /// details of graph coloring register allocation removed from it.
145 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
147 /// getIntrinsicInfo - If intrinsic information is available, return it. If
148 /// not, return null.
150 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
152 /// getJITInfo - If this target supports a JIT, return information for it,
153 /// otherwise return null.
155 virtual TargetJITInfo *getJITInfo() { return 0; }
157 /// getInstrItineraryData - Returns instruction itinerary data for the target
158 /// or specific subtarget.
160 virtual const InstrItineraryData *getInstrItineraryData() const {
164 /// getELFWriterInfo - If this target supports an ELF writer, return
165 /// information for it, otherwise return null.
167 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
169 /// hasMCRelaxAll - Check whether all machine code instructions should be
171 bool hasMCRelaxAll() const { return MCRelaxAll; }
173 /// setMCRelaxAll - Set whether all machine code instructions should be
175 void setMCRelaxAll(bool Value) { MCRelaxAll = Value; }
177 /// hasMCSaveTempLabels - Check whether temporary labels will be preserved
178 /// (i.e., not treated as temporary).
179 bool hasMCSaveTempLabels() const { return MCSaveTempLabels; }
181 /// setMCSaveTempLabels - Set whether temporary labels will be preserved
182 /// (i.e., not treated as temporary).
183 void setMCSaveTempLabels(bool Value) { MCSaveTempLabels = Value; }
185 /// hasMCNoExecStack - Check whether an executable stack is not needed.
186 bool hasMCNoExecStack() const { return MCNoExecStack; }
188 /// setMCNoExecStack - Set whether an executabel stack is not needed.
189 void setMCNoExecStack(bool Value) { MCNoExecStack = Value; }
191 /// hasMCUseLoc - Check whether we should use dwarf's .loc directive.
192 bool hasMCUseLoc() const { return MCUseLoc; }
194 /// setMCUseLoc - Set whether all we should use dwarf's .loc directive.
195 void setMCUseLoc(bool Value) { MCUseLoc = Value; }
197 /// hasMCUseCFI - Check whether we should use dwarf's .cfi_* directives.
198 bool hasMCUseCFI() const { return MCUseCFI; }
200 /// setMCUseCFI - Set whether all we should use dwarf's .cfi_* directives.
201 void setMCUseCFI(bool Value) { MCUseCFI = Value; }
203 /// getRelocationModel - Returns the code generation relocation model. The
204 /// choices are static, PIC, and dynamic-no-pic, and target default.
205 static Reloc::Model getRelocationModel();
207 /// setRelocationModel - Sets the code generation relocation model.
209 static void setRelocationModel(Reloc::Model Model);
211 /// getCodeModel - Returns the code model. The choices are small, kernel,
212 /// medium, large, and target default.
213 static CodeModel::Model getCodeModel();
215 /// setCodeModel - Sets the code model.
217 static void setCodeModel(CodeModel::Model Model);
219 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
221 static bool getAsmVerbosityDefault();
223 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
225 static void setAsmVerbosityDefault(bool);
227 /// getDataSections - Return true if data objects should be emitted into their
228 /// own section, corresponds to -fdata-sections.
229 static bool getDataSections();
231 /// getFunctionSections - Return true if functions should be emitted into
232 /// their own section, corresponding to -ffunction-sections.
233 static bool getFunctionSections();
235 /// setDataSections - Set if the data are emit into separate sections.
236 static void setDataSections(bool);
238 /// setFunctionSections - Set if the functions are emit into separate
240 static void setFunctionSections(bool);
242 /// CodeGenFileType - These enums are meant to be passed into
243 /// addPassesToEmitFile to indicate what type of file to emit, and returned by
244 /// it to indicate what type of file could actually be made.
245 enum CodeGenFileType {
248 CGFT_Null // Do not emit any output.
251 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
252 /// on this target. User flag overrides.
253 virtual bool getEnableTailMergeDefault() const { return true; }
255 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
256 /// specified file emitted. Typically this will involve several steps of code
257 /// generation. This method should return true if emission of this file type
258 /// is not supported, or false on success.
259 virtual bool addPassesToEmitFile(PassManagerBase &,
260 formatted_raw_ostream &,
267 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
268 /// get machine code emitted. This uses a JITCodeEmitter object to handle
269 /// actually outputting the machine code and resolving things like the address
270 /// of functions. This method returns true if machine code emission is
273 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
280 /// addPassesToEmitMC - Add passes to the specified pass manager to get
281 /// machine code emitted with the MCJIT. This method returns true if machine
282 /// code is not supported. It fills the MCContext Ctx pointer which can be
283 /// used to build custom MCStreamer.
285 virtual bool addPassesToEmitMC(PassManagerBase &,
294 /// LLVMTargetMachine - This class describes a target machine that is
295 /// implemented with the LLVM target-independent code generator.
297 class LLVMTargetMachine : public TargetMachine {
298 std::string TargetTriple;
300 protected: // Can only create subclasses.
301 LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
304 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
305 /// both emitting to assembly files or machine code output.
307 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
308 bool DisableVerify, MCContext *&OutCtx);
310 virtual void setCodeModelForJIT();
311 virtual void setCodeModelForStatic();
315 const std::string &getTargetTriple() const { return TargetTriple; }
317 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
318 /// specified file emitted. Typically this will involve several steps of code
319 /// generation. If OptLevel is None, the code generator should emit code as
320 /// fast as possible, though the generated code may be less efficient.
321 virtual bool addPassesToEmitFile(PassManagerBase &PM,
322 formatted_raw_ostream &Out,
323 CodeGenFileType FileType,
325 bool DisableVerify = true);
327 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
328 /// get machine code emitted. This uses a JITCodeEmitter object to handle
329 /// actually outputting the machine code and resolving things like the address
330 /// of functions. This method returns true if machine code emission is
333 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
336 bool DisableVerify = true);
338 /// addPassesToEmitMC - Add passes to the specified pass manager to get
339 /// machine code emitted with the MCJIT. This method returns true if machine
340 /// code is not supported. It fills the MCContext Ctx pointer which can be
341 /// used to build custom MCStreamer.
343 virtual bool addPassesToEmitMC(PassManagerBase &PM,
346 CodeGenOpt::Level OptLevel,
347 bool DisableVerify = true);
349 /// Target-Independent Code Generator Pass Configuration Options.
351 /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM
352 /// passes (which are run just before instruction selector).
353 virtual bool addPreISel(PassManagerBase &, CodeGenOpt::Level) {
357 /// addInstSelector - This method should install an instruction selector pass,
358 /// which converts from LLVM code to machine instructions.
359 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
363 /// addPreRegAlloc - This method may be implemented by targets that want to
364 /// run passes immediately before register allocation. This should return
365 /// true if -print-machineinstrs should print after these passes.
366 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
370 /// addPostRegAlloc - This method may be implemented by targets that want
371 /// to run passes after register allocation but before prolog-epilog
372 /// insertion. This should return true if -print-machineinstrs should print
373 /// after these passes.
374 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
378 /// addPreSched2 - This method may be implemented by targets that want to
379 /// run passes after prolog-epilog insertion and before the second instruction
380 /// scheduling pass. This should return true if -print-machineinstrs should
381 /// print after these passes.
382 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
386 /// addPreEmitPass - This pass may be implemented by targets that want to run
387 /// passes immediately before machine code is emitted. This should return
388 /// true if -print-machineinstrs should print out the code after the passes.
389 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
394 /// addCodeEmitter - This pass should be overridden by the target to add a
395 /// code emitter, if supported. If this is not supported, 'true' should be
397 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
402 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
403 /// on this target. User flag overrides.
404 virtual bool getEnableTailMergeDefault() const { return true; }
407 } // End llvm namespace