1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the TargetMachine and LLVMTargetMachine classes.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETMACHINE_H
15 #define LLVM_TARGET_TARGETMACHINE_H
17 #include "llvm/Target/TargetInstrItineraries.h"
26 class TargetSubtarget;
27 class TargetInstrInfo;
28 class TargetIntrinsicInfo;
31 class TargetFrameInfo;
32 class MachineCodeEmitter;
34 class ObjectCodeEmitter;
35 class TargetRegisterInfo;
36 class PassManagerBase;
39 class TargetMachOWriterInfo;
40 class TargetELFWriterInfo;
41 class formatted_raw_ostream;
43 // Relocation model types.
48 PIC_, // Cannot be named PIC due to collision with -DPIC
74 // Code generation optimization level.
75 namespace CodeGenOpt {
84 // Specify if we should encode the LSDA pointer in the FDE as 4- or 8-bytes.
85 namespace DwarfLSDAEncoding {
93 //===----------------------------------------------------------------------===//
95 /// TargetMachine - Primary interface to the complete machine description for
96 /// the target machine. All target-specific information should be accessible
97 /// through this interface.
100 TargetMachine(const TargetMachine &); // DO NOT IMPLEMENT
101 void operator=(const TargetMachine &); // DO NOT IMPLEMENT
102 protected: // Can only create subclasses.
103 TargetMachine(const Target &);
105 /// getSubtargetImpl - virtual method implemented by subclasses that returns
106 /// a reference to that target's TargetSubtarget-derived member variable.
107 virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
109 /// TheTarget - The Target that this machine was created for.
110 const Target &TheTarget;
112 /// AsmInfo - Contains target specific asm information.
114 const MCAsmInfo *AsmInfo;
117 virtual ~TargetMachine();
119 const Target &getTarget() const { return TheTarget; }
121 // Interfaces to the major aspects of target machine information:
122 // -- Instruction opcode and operand information
123 // -- Pipelines and scheduling information
124 // -- Stack frame information
125 // -- Selection DAG lowering information
127 virtual const TargetInstrInfo *getInstrInfo() const { return 0; }
128 virtual const TargetFrameInfo *getFrameInfo() const { return 0; }
129 virtual TargetLowering *getTargetLowering() const { return 0; }
130 virtual const TargetData *getTargetData() const { return 0; }
132 /// getMCAsmInfo - Return target specific asm information.
134 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
136 /// getSubtarget - This method returns a pointer to the specified type of
137 /// TargetSubtarget. In debug builds, it verifies that the object being
138 /// returned is of the correct type.
139 template<typename STC> const STC &getSubtarget() const {
140 return *static_cast<const STC*>(getSubtargetImpl());
143 /// getRegisterInfo - If register information is available, return it. If
144 /// not, return null. This is kept separate from RegInfo until RegInfo has
145 /// details of graph coloring register allocation removed from it.
147 virtual const TargetRegisterInfo *getRegisterInfo() const { return 0; }
149 /// getIntrinsicInfo - If intrinsic information is available, return it. If
150 /// not, return null.
152 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { return 0; }
154 /// getJITInfo - If this target supports a JIT, return information for it,
155 /// otherwise return null.
157 virtual TargetJITInfo *getJITInfo() { return 0; }
159 /// getInstrItineraryData - Returns instruction itinerary data for the target
160 /// or specific subtarget.
162 virtual const InstrItineraryData getInstrItineraryData() const {
163 return InstrItineraryData();
166 /// getMachOWriterInfo - If this target supports a Mach-O writer, return
167 /// information for it, otherwise return null.
169 virtual const TargetMachOWriterInfo *getMachOWriterInfo() const { return 0; }
171 /// getELFWriterInfo - If this target supports an ELF writer, return
172 /// information for it, otherwise return null.
174 virtual const TargetELFWriterInfo *getELFWriterInfo() const { return 0; }
176 /// getRelocationModel - Returns the code generation relocation model. The
177 /// choices are static, PIC, and dynamic-no-pic, and target default.
178 static Reloc::Model getRelocationModel();
180 /// setRelocationModel - Sets the code generation relocation model.
182 static void setRelocationModel(Reloc::Model Model);
184 /// getCodeModel - Returns the code model. The choices are small, kernel,
185 /// medium, large, and target default.
186 static CodeModel::Model getCodeModel();
188 /// setCodeModel - Sets the code model.
190 static void setCodeModel(CodeModel::Model Model);
192 /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
194 static bool getAsmVerbosityDefault();
196 /// setAsmVerbosityDefault - Set the default value of asm verbosity. Default
198 static void setAsmVerbosityDefault(bool);
200 /// getLSDAEncoding - Returns the LSDA pointer encoding. The choices are
201 /// 4-byte, 8-byte, and target default. The CIE is hard-coded to indicate that
202 /// the LSDA pointer in the FDE section is an "sdata4", and should be encoded
203 /// as a 4-byte pointer by default. However, some systems may require a
204 /// different size due to bugs or other conditions. We will default to a
205 /// 4-byte encoding unless the system tells us otherwise.
207 /// FIXME: This call-back isn't good! We should be using the correct encoding
208 /// regardless of the system. However, there are some systems which have bugs
209 /// that prevent this from occuring.
210 virtual DwarfLSDAEncoding::Encoding getLSDAEncoding() const {
211 return DwarfLSDAEncoding::Default;
214 /// CodeGenFileType - These enums are meant to be passed into
215 /// addPassesToEmitFile to indicate what type of file to emit.
216 enum CodeGenFileType {
217 AssemblyFile, ObjectFile, DynamicLibrary
220 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
221 /// on this target. User flag overrides.
222 virtual bool getEnableTailMergeDefault() const { return true; }
224 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
225 /// specified file emitted. Typically this will involve several steps of code
227 /// This method should return FileModel::Error if emission of this file type
228 /// is not supported.
230 virtual FileModel::Model addPassesToEmitFile(PassManagerBase &,
231 formatted_raw_ostream &,
234 return FileModel::None;
237 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
238 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
239 /// actually outputting the machine code and resolving things like the address
240 /// of functions. This method returns true if machine code emission is
243 virtual bool addPassesToEmitMachineCode(PassManagerBase &,
249 /// addPassesToEmitWholeFile - This method can be implemented by targets that
250 /// require having the entire module at once. This is not recommended, do not
252 virtual bool WantsWholeFile() const { return false; }
253 virtual bool addPassesToEmitWholeFile(PassManager &, formatted_raw_ostream &,
260 /// LLVMTargetMachine - This class describes a target machine that is
261 /// implemented with the LLVM target-independent code generator.
263 class LLVMTargetMachine : public TargetMachine {
264 protected: // Can only create subclasses.
265 LLVMTargetMachine(const Target &T, const std::string &TargetTriple);
267 /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
268 /// both emitting to assembly files or machine code output.
270 bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level);
273 virtual void setCodeModelForJIT();
274 virtual void setCodeModelForStatic();
278 /// addPassesToEmitFile - Add passes to the specified pass manager to get the
279 /// specified file emitted. Typically this will involve several steps of code
280 /// generation. If OptLevel is None, the code generator should emit code as fast
281 /// as possible, though the generated code may be less efficient. This method
282 /// should return FileModel::Error if emission of this file type is not
285 /// The default implementation of this method adds components from the
286 /// LLVM retargetable code generator, invoking the methods below to get
287 /// target-specific passes in standard locations.
289 virtual FileModel::Model addPassesToEmitFile(PassManagerBase &PM,
290 formatted_raw_ostream &Out,
291 CodeGenFileType FileType,
294 /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
295 /// get machine code emitted. This uses a MachineCodeEmitter object to handle
296 /// actually outputting the machine code and resolving things like the address
297 /// of functions. This method returns true if machine code emission is
300 virtual bool addPassesToEmitMachineCode(PassManagerBase &PM,
304 /// Target-Independent Code Generator Pass Configuration Options.
306 /// addInstSelector - This method should add any "last minute" LLVM->LLVM
307 /// passes, then install an instruction selector pass, which converts from
308 /// LLVM code to machine instructions.
309 virtual bool addInstSelector(PassManagerBase &, CodeGenOpt::Level) {
313 /// addPreRegAlloc - This method may be implemented by targets that want to
314 /// run passes immediately before register allocation. This should return
315 /// true if -print-machineinstrs should print after these passes.
316 virtual bool addPreRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
320 /// addPostRegAlloc - This method may be implemented by targets that want
321 /// to run passes after register allocation but before prolog-epilog
322 /// insertion. This should return true if -print-machineinstrs should print
323 /// after these passes.
324 virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level) {
328 /// addPreSched2 - This method may be implemented by targets that want to
329 /// run passes after prolog-epilog insertion and before the second instruction
330 /// scheduling pass. This should return true if -print-machineinstrs should
331 /// print after these passes.
332 virtual bool addPreSched2(PassManagerBase &, CodeGenOpt::Level) {
336 /// addPreEmitPass - This pass may be implemented by targets that want to run
337 /// passes immediately before machine code is emitted. This should return
338 /// true if -print-machineinstrs should print out the code after the passes.
339 virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level) {
344 /// addCodeEmitter - This pass should be overridden by the target to add a
345 /// code emitter, if supported. If this is not supported, 'true' should be
347 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
348 MachineCodeEmitter &) {
352 /// addCodeEmitter - This pass should be overridden by the target to add a
353 /// code emitter, if supported. If this is not supported, 'true' should be
355 virtual bool addCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
360 /// addSimpleCodeEmitter - This pass should be overridden by the target to add
361 /// a code emitter (without setting flags), if supported. If this is not
362 /// supported, 'true' should be returned.
363 virtual bool addSimpleCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
364 MachineCodeEmitter &) {
368 /// addSimpleCodeEmitter - This pass should be overridden by the target to add
369 /// a code emitter (without setting flags), if supported. If this is not
370 /// supported, 'true' should be returned.
371 virtual bool addSimpleCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
376 /// addSimpleCodeEmitter - This pass should be overridden by the target to add
377 /// a code emitter (without setting flags), if supported. If this is not
378 /// supported, 'true' should be returned.
379 virtual bool addSimpleCodeEmitter(PassManagerBase &, CodeGenOpt::Level,
380 ObjectCodeEmitter &) {
384 /// getEnableTailMergeDefault - the default setting for -enable-tail-merge
385 /// on this target. User flag overrides.
386 virtual bool getEnableTailMergeDefault() const { return true; }
389 } // End llvm namespace