1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/DenseSet.h"
28 class MachineFunction;
32 /// TargetRegisterDesc - This record contains all of the information known about
33 /// a particular register. The AliasSet field (if not null) contains a pointer
34 /// to a Zero terminated array of registers that this register aliases. This is
35 /// needed for architectures like X86 which have AL alias AX alias EAX.
36 /// Registers that this does not apply to simply should set this to null.
37 /// The SubRegs field is a zero terminated array of registers that are
38 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
39 /// The SuperRegs field is a zero terminated array of registers that are
40 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
43 struct TargetRegisterDesc {
44 const char *AsmName; // Assembly language name for the register
45 const char *Name; // Printable name for the reg (for debugging)
46 const unsigned *AliasSet; // Register Alias Set, described above
47 const unsigned *SubRegs; // Sub-register set, described above
48 const unsigned *SuperRegs; // Super-register set, described above
51 class TargetRegisterClass {
53 typedef const unsigned* iterator;
54 typedef const unsigned* const_iterator;
56 typedef const MVT* vt_iterator;
57 typedef const TargetRegisterClass* const * sc_iterator;
61 const vt_iterator VTs;
62 const sc_iterator SubClasses;
63 const sc_iterator SuperClasses;
64 const sc_iterator SubRegClasses;
65 const sc_iterator SuperRegClasses;
66 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
68 const iterator RegsBegin, RegsEnd;
69 DenseSet<unsigned> RegSet;
71 TargetRegisterClass(unsigned id,
74 const TargetRegisterClass * const *subcs,
75 const TargetRegisterClass * const *supcs,
76 const TargetRegisterClass * const *subregcs,
77 const TargetRegisterClass * const *superregcs,
78 unsigned RS, unsigned Al, int CC,
79 iterator RB, iterator RE)
80 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
81 SubRegClasses(subregcs), SuperRegClasses(superregcs),
82 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {
83 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
86 virtual ~TargetRegisterClass() {} // Allow subclasses
88 /// getID() - Return the register class ID number.
90 unsigned getID() const { return ID; }
92 /// getName() - Return the register class name for debugging.
94 const char *getName() const { return Name; }
96 /// begin/end - Return all of the registers in this class.
98 iterator begin() const { return RegsBegin; }
99 iterator end() const { return RegsEnd; }
101 /// getNumRegs - Return the number of registers in this class.
103 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
105 /// getRegister - Return the specified register in the class.
107 unsigned getRegister(unsigned i) const {
108 assert(i < getNumRegs() && "Register number out of range!");
112 /// contains - Return true if the specified register is included in this
114 bool contains(unsigned Reg) const {
115 return RegSet.count(Reg);
118 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
120 bool hasType(MVT vt) const {
121 for(int i = 0; VTs[i] != MVT::Other; ++i)
127 /// vt_begin / vt_end - Loop over all of the value types that can be
128 /// represented by values in this register class.
129 vt_iterator vt_begin() const {
133 vt_iterator vt_end() const {
135 while (*I != MVT::Other) ++I;
139 /// subregclasses_begin / subregclasses_end - Loop over all of
140 /// the subreg register classes of this register class.
141 sc_iterator subregclasses_begin() const {
142 return SubRegClasses;
145 sc_iterator subregclasses_end() const {
146 sc_iterator I = SubRegClasses;
147 while (*I != NULL) ++I;
151 /// getSubRegisterRegClass - Return the register class of subregisters with
152 /// index SubIdx, or NULL if no such class exists.
153 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
154 assert(SubIdx>0 && "Invalid subregister index");
155 for (unsigned s = 0; s != SubIdx-1; ++s)
156 if (!SubRegClasses[s])
158 return SubRegClasses[SubIdx-1];
161 /// superregclasses_begin / superregclasses_end - Loop over all of
162 /// the superreg register classes of this register class.
163 sc_iterator superregclasses_begin() const {
164 return SuperRegClasses;
167 sc_iterator superregclasses_end() const {
168 sc_iterator I = SuperRegClasses;
169 while (*I != NULL) ++I;
173 /// hasSubClass - return true if the the specified TargetRegisterClass
174 /// is a proper subset of this TargetRegisterClass.
175 bool hasSubClass(const TargetRegisterClass *cs) const {
176 for (int i = 0; SubClasses[i] != NULL; ++i)
177 if (SubClasses[i] == cs)
182 /// subclasses_begin / subclasses_end - Loop over all of the classes
183 /// that are proper subsets of this register class.
184 sc_iterator subclasses_begin() const {
188 sc_iterator subclasses_end() const {
189 sc_iterator I = SubClasses;
190 while (*I != NULL) ++I;
194 /// hasSuperClass - return true if the specified TargetRegisterClass is a
195 /// proper superset of this TargetRegisterClass.
196 bool hasSuperClass(const TargetRegisterClass *cs) const {
197 for (int i = 0; SuperClasses[i] != NULL; ++i)
198 if (SuperClasses[i] == cs)
203 /// superclasses_begin / superclasses_end - Loop over all of the classes
204 /// that are proper supersets of this register class.
205 sc_iterator superclasses_begin() const {
209 sc_iterator superclasses_end() const {
210 sc_iterator I = SuperClasses;
211 while (*I != NULL) ++I;
215 /// isASubClass - return true if this TargetRegisterClass is a subset
216 /// class of at least one other TargetRegisterClass.
217 bool isASubClass() const {
218 return SuperClasses[0] != 0;
221 /// allocation_order_begin/end - These methods define a range of registers
222 /// which specify the registers in this class that are valid to register
223 /// allocate, and the preferred order to allocate them in. For example,
224 /// callee saved registers should be at the end of the list, because it is
225 /// cheaper to allocate caller saved registers.
227 /// These methods take a MachineFunction argument, which can be used to tune
228 /// the allocatable registers based on the characteristics of the function.
229 /// One simple example is that the frame pointer register can be used if
230 /// frame-pointer-elimination is performed.
232 /// By default, these methods return all registers in the class.
234 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
237 virtual iterator allocation_order_end(const MachineFunction &MF) const {
243 /// getSize - Return the size of the register in bytes, which is also the size
244 /// of a stack slot allocated to hold a spilled copy of this register.
245 unsigned getSize() const { return RegSize; }
247 /// getAlignment - Return the minimum required alignment for a register of
249 unsigned getAlignment() const { return Alignment; }
251 /// getCopyCost - Return the cost of copying a value between two registers in
252 /// this class. A negative number means the register class is very expensive
253 /// to copy e.g. status flag register classes.
254 int getCopyCost() const { return CopyCost; }
258 /// TargetRegisterInfo base class - We assume that the target defines a static
259 /// array of TargetRegisterDesc objects that represent all of the machine
260 /// registers that the target has. As such, we simply have to track a pointer
261 /// to this array so that we can turn register number into a register
264 class TargetRegisterInfo {
266 const unsigned* SubregHash;
267 const unsigned SubregHashSize;
268 const unsigned* SuperregHash;
269 const unsigned SuperregHashSize;
270 const unsigned* AliasesHash;
271 const unsigned AliasesHashSize;
273 typedef const TargetRegisterClass * const * regclass_iterator;
275 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
276 unsigned NumRegs; // Number of entries in the array
278 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
280 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
282 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
283 regclass_iterator RegClassBegin,
284 regclass_iterator RegClassEnd,
285 int CallFrameSetupOpcode = -1,
286 int CallFrameDestroyOpcode = -1,
287 const unsigned* subregs = 0,
288 const unsigned subregsize = 0,
289 const unsigned* superregs = 0,
290 const unsigned superregsize = 0,
291 const unsigned* aliases = 0,
292 const unsigned aliasessize = 0);
293 virtual ~TargetRegisterInfo();
296 enum { // Define some target independent constants
297 /// NoRegister - This physical register is not a real target register. It
298 /// is useful as a sentinal.
301 /// FirstVirtualRegister - This is the first register number that is
302 /// considered to be a 'virtual' register, which is part of the SSA
303 /// namespace. This must be the same for all targets, which means that each
304 /// target is limited to 1024 registers.
305 FirstVirtualRegister = 1024
308 /// isPhysicalRegister - Return true if the specified register number is in
309 /// the physical register namespace.
310 static bool isPhysicalRegister(unsigned Reg) {
311 assert(Reg && "this is not a register!");
312 return Reg < FirstVirtualRegister;
315 /// isVirtualRegister - Return true if the specified register number is in
316 /// the virtual register namespace.
317 static bool isVirtualRegister(unsigned Reg) {
318 assert(Reg && "this is not a register!");
319 return Reg >= FirstVirtualRegister;
322 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
323 /// register of the given type. If type is MVT::Other, then just return any
324 /// register class the register belongs to.
325 virtual const TargetRegisterClass *
326 getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
328 /// getAllocatableSet - Returns a bitset indexed by register number
329 /// indicating if a register is allocatable or not. If a register class is
330 /// specified, returns the subset for the class.
331 BitVector getAllocatableSet(MachineFunction &MF,
332 const TargetRegisterClass *RC = NULL) const;
334 const TargetRegisterDesc &operator[](unsigned RegNo) const {
335 assert(RegNo < NumRegs &&
336 "Attempting to access record for invalid register number!");
340 /// Provide a get method, equivalent to [], but more useful if we have a
341 /// pointer to this object.
343 const TargetRegisterDesc &get(unsigned RegNo) const {
344 return operator[](RegNo);
347 /// getAliasSet - Return the set of registers aliased by the specified
348 /// register, or a null list of there are none. The list returned is zero
351 const unsigned *getAliasSet(unsigned RegNo) const {
352 return get(RegNo).AliasSet;
355 /// getSubRegisters - Return the list of registers that are sub-registers of
356 /// the specified register, or a null list of there are none. The list
357 /// returned is zero terminated and sorted according to super-sub register
358 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
360 const unsigned *getSubRegisters(unsigned RegNo) const {
361 return get(RegNo).SubRegs;
364 /// getSuperRegisters - Return the list of registers that are super-registers
365 /// of the specified register, or a null list of there are none. The list
366 /// returned is zero terminated and sorted according to super-sub register
367 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
369 const unsigned *getSuperRegisters(unsigned RegNo) const {
370 return get(RegNo).SuperRegs;
373 /// getAsmName - Return the symbolic target-specific name for the
374 /// specified physical register.
375 const char *getAsmName(unsigned RegNo) const {
376 return get(RegNo).AsmName;
379 /// getName - Return the human-readable symbolic target-specific name for the
380 /// specified physical register.
381 const char *getName(unsigned RegNo) const {
382 return get(RegNo).Name;
385 /// getNumRegs - Return the number of registers this target has (useful for
386 /// sizing arrays holding per register information)
387 unsigned getNumRegs() const {
391 /// areAliases - Returns true if the two registers alias each other, false
393 bool areAliases(unsigned regA, unsigned regB) const {
394 size_t index = (regA + regB * 37) & (AliasesHashSize-1);
395 unsigned ProbeAmt = 0;
396 while (AliasesHash[index*2] != 0 &&
397 AliasesHash[index*2+1] != 0) {
398 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB)
401 index = (index + ProbeAmt) & (AliasesHashSize-1);
408 /// regsOverlap - Returns true if the two registers are equal or alias each
409 /// other. The registers may be virtual register.
410 bool regsOverlap(unsigned regA, unsigned regB) const {
414 if (isVirtualRegister(regA) || isVirtualRegister(regB))
416 return areAliases(regA, regB);
419 /// isSubRegister - Returns true if regB is a sub-register of regA.
421 bool isSubRegister(unsigned regA, unsigned regB) const {
422 // SubregHash is a simple quadratically probed hash table.
423 size_t index = (regA + regB * 37) & (SubregHashSize-1);
424 unsigned ProbeAmt = 2;
425 while (SubregHash[index*2] != 0 &&
426 SubregHash[index*2+1] != 0) {
427 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
430 index = (index + ProbeAmt) & (SubregHashSize-1);
437 /// isSuperRegister - Returns true if regB is a super-register of regA.
439 bool isSuperRegister(unsigned regA, unsigned regB) const {
440 // SuperregHash is a simple quadratically probed hash table.
441 size_t index = (regA + regB * 37) & (SuperregHashSize-1);
442 unsigned ProbeAmt = 2;
443 while (SuperregHash[index*2] != 0 &&
444 SuperregHash[index*2+1] != 0) {
445 if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB)
448 index = (index + ProbeAmt) & (SuperregHashSize-1);
455 /// getCalleeSavedRegs - Return a null-terminated list of all of the
456 /// callee saved registers on this target. The register should be in the
457 /// order of desired callee-save stack frame offset. The first register is
458 /// closed to the incoming stack pointer if stack grows down, and vice versa.
459 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
462 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
463 /// register classes to spill each callee saved register with. The order and
464 /// length of this list match the getCalleeSaveRegs() list.
465 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
466 const MachineFunction *MF) const =0;
468 /// getReservedRegs - Returns a bitset indexed by physical register number
469 /// indicating if a register is a special register that has particular uses
470 /// and should be considered unavailable at all times, e.g. SP, RA. This is
471 /// used by register scavenger to determine what registers are free.
472 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
474 /// getSubReg - Returns the physical register number of sub-register "Index"
475 /// for physical register RegNo. Return zero if the sub-register does not
477 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
479 /// getMatchingSuperReg - Return a super-register of the specified register
480 /// Reg so its sub-register of index SubIdx is Reg.
481 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
482 const TargetRegisterClass *RC) const {
483 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
484 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
489 //===--------------------------------------------------------------------===//
490 // Register Class Information
493 /// Register class iterators
495 regclass_iterator regclass_begin() const { return RegClassBegin; }
496 regclass_iterator regclass_end() const { return RegClassEnd; }
498 unsigned getNumRegClasses() const {
499 return (unsigned)(regclass_end()-regclass_begin());
502 /// getRegClass - Returns the register class associated with the enumeration
503 /// value. See class TargetOperandInfo.
504 const TargetRegisterClass *getRegClass(unsigned i) const {
505 assert(i <= getNumRegClasses() && "Register Class ID out of range");
506 return i ? RegClassBegin[i - 1] : NULL;
509 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
511 virtual const TargetRegisterClass *getPointerRegClass() const {
512 assert(0 && "Target didn't implement getPointerRegClass!");
513 return 0; // Must return a value in order to compile with VS 2005
516 /// getCrossCopyRegClass - Returns a legal register class to copy a register
517 /// in the specified class to or from. Returns NULL if it is possible to copy
518 /// between a two registers of the specified class.
519 virtual const TargetRegisterClass *
520 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
524 /// targetHandlesStackFrameRounding - Returns true if the target is
525 /// responsible for rounding up the stack frame (probably at emitPrologue
527 virtual bool targetHandlesStackFrameRounding() const {
531 /// requiresRegisterScavenging - returns true if the target requires (and can
532 /// make use of) the register scavenger.
533 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
537 /// hasFP - Return true if the specified function should have a dedicated
538 /// frame pointer register. For most targets this is true only if the function
539 /// has variable sized allocas or if frame pointer elimination is disabled.
540 virtual bool hasFP(const MachineFunction &MF) const = 0;
542 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
543 // not required, we reserve argument space for call sites in the function
544 // immediately on entry to the current function. This eliminates the need for
545 // add/sub sp brackets around call sites. Returns true if the call frame is
546 // included as part of the stack frame.
547 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
551 // needsStackRealignment - true if storage within the function requires the
552 // stack pointer to be aligned more than the normal calling convention calls
554 virtual bool needsStackRealignment(const MachineFunction &MF) const {
558 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
559 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
560 /// targets use pseudo instructions in order to abstract away the difference
561 /// between operating with a frame pointer and operating without, through the
562 /// use of these two instructions.
564 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
565 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
567 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
568 /// code insertion to eliminate call frame setup and destroy pseudo
569 /// instructions (but only if the Target is using them). It is responsible
570 /// for eliminating these instructions, replacing them with concrete
571 /// instructions. This method need only be implemented if using call frame
572 /// setup/destroy pseudo instructions.
575 eliminateCallFramePseudoInstr(MachineFunction &MF,
576 MachineBasicBlock &MBB,
577 MachineBasicBlock::iterator MI) const {
578 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
579 "eliminateCallFramePseudoInstr must be implemented if using"
580 " call frame setup/destroy pseudo instructions!");
581 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
584 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
585 /// before PrologEpilogInserter scans the physical registers used to determine
586 /// what callee saved registers should be spilled. This method is optional.
587 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
588 RegScavenger *RS = NULL) const {
592 /// processFunctionBeforeFrameFinalized - This method is called immediately
593 /// before the specified functions frame layout (MF.getFrameInfo()) is
594 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
595 /// replaced with direct constants. This method is optional.
597 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
600 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
601 /// frame indices from instructions which may use them. The instruction
602 /// referenced by the iterator contains an MO_FrameIndex operand which must be
603 /// eliminated by this method. This method may modify or replace the
604 /// specified instruction, as long as it keeps the iterator pointing the the
605 /// finished product. SPAdj is the SP adjustment due to call frame setup
607 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
608 int SPAdj, RegScavenger *RS=NULL) const = 0;
610 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
612 virtual void emitPrologue(MachineFunction &MF) const = 0;
613 virtual void emitEpilogue(MachineFunction &MF,
614 MachineBasicBlock &MBB) const = 0;
616 //===--------------------------------------------------------------------===//
617 /// Debug information queries.
619 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
620 /// number. Returns -1 if there is no equivalent value. The second
621 /// parameter allows targets to use different numberings for EH info and
623 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
625 /// getFrameRegister - This method should return the register used as a base
626 /// for values allocated in the current stack frame.
627 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
629 /// getFrameIndexOffset - Returns the displacement from the frame register to
630 /// the stack frame of the specified index.
631 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
633 /// getRARegister - This method should return the register where the return
634 /// address can be found.
635 virtual unsigned getRARegister() const = 0;
637 /// getInitialFrameState - Returns a list of machine moves that are assumed
638 /// on entry to all functions. Note that LabelID is ignored (assumed to be
639 /// the beginning of the function.)
640 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
643 // This is useful when building IndexedMaps keyed on virtual registers
644 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
645 unsigned operator()(unsigned Reg) const {
646 return Reg - TargetRegisterInfo::FirstVirtualRegister;
650 } // End llvm namespace