1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/DenseSet.h"
28 class MachineFunction;
32 /// TargetRegisterDesc - This record contains all of the information known about
33 /// a particular register. The AliasSet field (if not null) contains a pointer
34 /// to a Zero terminated array of registers that this register aliases. This is
35 /// needed for architectures like X86 which have AL alias AX alias EAX.
36 /// Registers that this does not apply to simply should set this to null.
37 /// The SubRegs field is a zero terminated array of registers that are
38 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
39 /// The SuperRegs field is a zero terminated array of registers that are
40 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
43 struct TargetRegisterDesc {
44 const char *AsmName; // Assembly language name for the register
45 const char *Name; // Printable name for the reg (for debugging)
46 const unsigned *AliasSet; // Register Alias Set, described above
47 const unsigned *SubRegs; // Sub-register set, described above
48 const unsigned *SuperRegs; // Super-register set, described above
51 class TargetRegisterClass {
53 typedef const unsigned* iterator;
54 typedef const unsigned* const_iterator;
56 typedef const MVT* vt_iterator;
57 typedef const TargetRegisterClass* const * sc_iterator;
61 const vt_iterator VTs;
62 const sc_iterator SubClasses;
63 const sc_iterator SuperClasses;
64 const sc_iterator SubRegClasses;
65 const sc_iterator SuperRegClasses;
66 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
68 const iterator RegsBegin, RegsEnd;
69 DenseSet<unsigned> RegSet;
71 TargetRegisterClass(unsigned id,
74 const TargetRegisterClass * const *subcs,
75 const TargetRegisterClass * const *supcs,
76 const TargetRegisterClass * const *subregcs,
77 const TargetRegisterClass * const *superregcs,
78 unsigned RS, unsigned Al, int CC,
79 iterator RB, iterator RE)
80 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
81 SubRegClasses(subregcs), SuperRegClasses(superregcs),
82 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {
83 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
86 virtual ~TargetRegisterClass() {} // Allow subclasses
88 /// getID() - Return the register class ID number.
90 unsigned getID() const { return ID; }
92 /// getName() - Return the register class name for debugging.
94 const char *getName() const { return Name; }
96 /// begin/end - Return all of the registers in this class.
98 iterator begin() const { return RegsBegin; }
99 iterator end() const { return RegsEnd; }
101 /// getNumRegs - Return the number of registers in this class.
103 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
105 /// getRegister - Return the specified register in the class.
107 unsigned getRegister(unsigned i) const {
108 assert(i < getNumRegs() && "Register number out of range!");
112 /// contains - Return true if the specified register is included in this
114 bool contains(unsigned Reg) const {
115 return RegSet.count(Reg);
118 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
120 bool hasType(MVT vt) const {
121 for(int i = 0; VTs[i] != MVT::Other; ++i)
127 /// vt_begin / vt_end - Loop over all of the value types that can be
128 /// represented by values in this register class.
129 vt_iterator vt_begin() const {
133 vt_iterator vt_end() const {
135 while (*I != MVT::Other) ++I;
139 /// subregclasses_begin / subregclasses_end - Loop over all of
140 /// the subreg register classes of this register class.
141 sc_iterator subregclasses_begin() const {
142 return SubRegClasses;
145 sc_iterator subregclasses_end() const {
146 sc_iterator I = SubRegClasses;
147 while (*I != NULL) ++I;
151 /// getSubRegisterRegClass - Return the register class of subregisters with
152 /// index SubIdx, or NULL if no such class exists.
153 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
154 assert(SubIdx>0 && "Invalid subregister index");
155 for (unsigned s = 0; s != SubIdx-1; ++s)
156 if (!SubRegClasses[s])
158 return SubRegClasses[SubIdx-1];
161 /// superregclasses_begin / superregclasses_end - Loop over all of
162 /// the superreg register classes of this register class.
163 sc_iterator superregclasses_begin() const {
164 return SuperRegClasses;
167 sc_iterator superregclasses_end() const {
168 sc_iterator I = SuperRegClasses;
169 while (*I != NULL) ++I;
173 /// hasSubClass - return true if the the specified TargetRegisterClass
174 /// is a proper subset of this TargetRegisterClass.
175 bool hasSubClass(const TargetRegisterClass *cs) const {
176 for (int i = 0; SubClasses[i] != NULL; ++i)
177 if (SubClasses[i] == cs)
182 /// subclasses_begin / subclasses_end - Loop over all of the classes
183 /// that are proper subsets of this register class.
184 sc_iterator subclasses_begin() const {
188 sc_iterator subclasses_end() const {
189 sc_iterator I = SubClasses;
190 while (*I != NULL) ++I;
194 /// hasSuperClass - return true if the specified TargetRegisterClass is a
195 /// proper superset of this TargetRegisterClass.
196 bool hasSuperClass(const TargetRegisterClass *cs) const {
197 for (int i = 0; SuperClasses[i] != NULL; ++i)
198 if (SuperClasses[i] == cs)
203 /// superclasses_begin / superclasses_end - Loop over all of the classes
204 /// that are proper supersets of this register class.
205 sc_iterator superclasses_begin() const {
209 sc_iterator superclasses_end() const {
210 sc_iterator I = SuperClasses;
211 while (*I != NULL) ++I;
215 /// isASubClass - return true if this TargetRegisterClass is a subset
216 /// class of at least one other TargetRegisterClass.
217 bool isASubClass() const {
218 return SuperClasses[0] != 0;
221 /// allocation_order_begin/end - These methods define a range of registers
222 /// which specify the registers in this class that are valid to register
223 /// allocate, and the preferred order to allocate them in. For example,
224 /// callee saved registers should be at the end of the list, because it is
225 /// cheaper to allocate caller saved registers.
227 /// These methods take a MachineFunction argument, which can be used to tune
228 /// the allocatable registers based on the characteristics of the function.
229 /// One simple example is that the frame pointer register can be used if
230 /// frame-pointer-elimination is performed.
232 /// By default, these methods return all registers in the class.
234 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
237 virtual iterator allocation_order_end(const MachineFunction &MF) const {
241 /// getSize - Return the size of the register in bytes, which is also the size
242 /// of a stack slot allocated to hold a spilled copy of this register.
243 unsigned getSize() const { return RegSize; }
245 /// getAlignment - Return the minimum required alignment for a register of
247 unsigned getAlignment() const { return Alignment; }
249 /// getCopyCost - Return the cost of copying a value between two registers in
250 /// this class. A negative number means the register class is very expensive
251 /// to copy e.g. status flag register classes.
252 int getCopyCost() const { return CopyCost; }
256 /// TargetRegisterInfo base class - We assume that the target defines a static
257 /// array of TargetRegisterDesc objects that represent all of the machine
258 /// registers that the target has. As such, we simply have to track a pointer
259 /// to this array so that we can turn register number into a register
262 class TargetRegisterInfo {
264 const unsigned* SubregHash;
265 const unsigned SubregHashSize;
266 const unsigned* SuperregHash;
267 const unsigned SuperregHashSize;
268 const unsigned* AliasesHash;
269 const unsigned AliasesHashSize;
271 typedef const TargetRegisterClass * const * regclass_iterator;
273 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
274 unsigned NumRegs; // Number of entries in the array
276 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
278 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
280 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
281 regclass_iterator RegClassBegin,
282 regclass_iterator RegClassEnd,
283 int CallFrameSetupOpcode = -1,
284 int CallFrameDestroyOpcode = -1,
285 const unsigned* subregs = 0,
286 const unsigned subregsize = 0,
287 const unsigned* superregs = 0,
288 const unsigned superregsize = 0,
289 const unsigned* aliases = 0,
290 const unsigned aliasessize = 0);
291 virtual ~TargetRegisterInfo();
294 enum { // Define some target independent constants
295 /// NoRegister - This physical register is not a real target register. It
296 /// is useful as a sentinal.
299 /// FirstVirtualRegister - This is the first register number that is
300 /// considered to be a 'virtual' register, which is part of the SSA
301 /// namespace. This must be the same for all targets, which means that each
302 /// target is limited to 1024 registers.
303 FirstVirtualRegister = 1024
306 /// isPhysicalRegister - Return true if the specified register number is in
307 /// the physical register namespace.
308 static bool isPhysicalRegister(unsigned Reg) {
309 assert(Reg && "this is not a register!");
310 return Reg < FirstVirtualRegister;
313 /// isVirtualRegister - Return true if the specified register number is in
314 /// the virtual register namespace.
315 static bool isVirtualRegister(unsigned Reg) {
316 assert(Reg && "this is not a register!");
317 return Reg >= FirstVirtualRegister;
320 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
321 /// register of the given type. If type is MVT::Other, then just return any
322 /// register class the register belongs to.
323 virtual const TargetRegisterClass *
324 getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
326 /// getAllocatableSet - Returns a bitset indexed by register number
327 /// indicating if a register is allocatable or not. If a register class is
328 /// specified, returns the subset for the class.
329 BitVector getAllocatableSet(MachineFunction &MF,
330 const TargetRegisterClass *RC = NULL) const;
332 const TargetRegisterDesc &operator[](unsigned RegNo) const {
333 assert(RegNo < NumRegs &&
334 "Attempting to access record for invalid register number!");
338 /// Provide a get method, equivalent to [], but more useful if we have a
339 /// pointer to this object.
341 const TargetRegisterDesc &get(unsigned RegNo) const {
342 return operator[](RegNo);
345 /// getAliasSet - Return the set of registers aliased by the specified
346 /// register, or a null list of there are none. The list returned is zero
349 const unsigned *getAliasSet(unsigned RegNo) const {
350 return get(RegNo).AliasSet;
353 /// getSubRegisters - Return the list of registers that are sub-registers of
354 /// the specified register, or a null list of there are none. The list
355 /// returned is zero terminated and sorted according to super-sub register
356 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
358 const unsigned *getSubRegisters(unsigned RegNo) const {
359 return get(RegNo).SubRegs;
362 /// getSuperRegisters - Return the list of registers that are super-registers
363 /// of the specified register, or a null list of there are none. The list
364 /// returned is zero terminated and sorted according to super-sub register
365 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
367 const unsigned *getSuperRegisters(unsigned RegNo) const {
368 return get(RegNo).SuperRegs;
371 /// getAsmName - Return the symbolic target-specific name for the
372 /// specified physical register.
373 const char *getAsmName(unsigned RegNo) const {
374 return get(RegNo).AsmName;
377 /// getName - Return the human-readable symbolic target-specific name for the
378 /// specified physical register.
379 const char *getName(unsigned RegNo) const {
380 return get(RegNo).Name;
383 /// getNumRegs - Return the number of registers this target has (useful for
384 /// sizing arrays holding per register information)
385 unsigned getNumRegs() const {
389 /// areAliases - Returns true if the two registers alias each other, false
391 bool areAliases(unsigned regA, unsigned regB) const {
392 size_t index = (regA + regB * 37) & (AliasesHashSize-1);
393 unsigned ProbeAmt = 0;
394 while (AliasesHash[index*2] != 0 &&
395 AliasesHash[index*2+1] != 0) {
396 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB)
399 index = (index + ProbeAmt) & (AliasesHashSize-1);
406 /// regsOverlap - Returns true if the two registers are equal or alias each
407 /// other. The registers may be virtual register.
408 bool regsOverlap(unsigned regA, unsigned regB) const {
412 if (isVirtualRegister(regA) || isVirtualRegister(regB))
414 return areAliases(regA, regB);
417 /// isSubRegister - Returns true if regB is a sub-register of regA.
419 bool isSubRegister(unsigned regA, unsigned regB) const {
420 // SubregHash is a simple quadratically probed hash table.
421 size_t index = (regA + regB * 37) & (SubregHashSize-1);
422 unsigned ProbeAmt = 2;
423 while (SubregHash[index*2] != 0 &&
424 SubregHash[index*2+1] != 0) {
425 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
428 index = (index + ProbeAmt) & (SubregHashSize-1);
435 /// isSuperRegister - Returns true if regB is a super-register of regA.
437 bool isSuperRegister(unsigned regA, unsigned regB) const {
438 // SuperregHash is a simple quadratically probed hash table.
439 size_t index = (regA + regB * 37) & (SuperregHashSize-1);
440 unsigned ProbeAmt = 2;
441 while (SuperregHash[index*2] != 0 &&
442 SuperregHash[index*2+1] != 0) {
443 if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB)
446 index = (index + ProbeAmt) & (SuperregHashSize-1);
453 /// getCalleeSavedRegs - Return a null-terminated list of all of the
454 /// callee saved registers on this target. The register should be in the
455 /// order of desired callee-save stack frame offset. The first register is
456 /// closed to the incoming stack pointer if stack grows down, and vice versa.
457 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
460 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
461 /// register classes to spill each callee saved register with. The order and
462 /// length of this list match the getCalleeSaveRegs() list.
463 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
464 const MachineFunction *MF) const =0;
466 /// getReservedRegs - Returns a bitset indexed by physical register number
467 /// indicating if a register is a special register that has particular uses
468 /// and should be considered unavailable at all times, e.g. SP, RA. This is
469 /// used by register scavenger to determine what registers are free.
470 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
472 /// getSubReg - Returns the physical register number of sub-register "Index"
473 /// for physical register RegNo. Return zero if the sub-register does not
475 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
477 /// getMatchingSuperReg - Return a super-register of the specified register
478 /// Reg so its sub-register of index SubIdx is Reg.
479 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
480 const TargetRegisterClass *RC) const {
481 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
482 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
487 //===--------------------------------------------------------------------===//
488 // Register Class Information
491 /// Register class iterators
493 regclass_iterator regclass_begin() const { return RegClassBegin; }
494 regclass_iterator regclass_end() const { return RegClassEnd; }
496 unsigned getNumRegClasses() const {
497 return (unsigned)(regclass_end()-regclass_begin());
500 /// getRegClass - Returns the register class associated with the enumeration
501 /// value. See class TargetOperandInfo.
502 const TargetRegisterClass *getRegClass(unsigned i) const {
503 assert(i <= getNumRegClasses() && "Register Class ID out of range");
504 return i ? RegClassBegin[i - 1] : NULL;
507 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
509 virtual const TargetRegisterClass *getPointerRegClass() const {
510 assert(0 && "Target didn't implement getPointerRegClass!");
511 return 0; // Must return a value in order to compile with VS 2005
514 /// getCrossCopyRegClass - Returns a legal register class to copy a register
515 /// in the specified class to or from. Returns NULL if it is possible to copy
516 /// between a two registers of the specified class.
517 virtual const TargetRegisterClass *
518 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
522 /// getAllocationOrder - Returns the register allocation order for a specified
523 /// register class in the form of a pair of TargetRegisterClass iterators.
524 virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
525 getAllocationOrder(const TargetRegisterClass *RC,
526 unsigned HintType, unsigned HintReg,
527 const MachineFunction &MF) const {
528 return std::make_pair(RC->allocation_order_begin(MF),
529 RC->allocation_order_end(MF));
532 /// ResolveRegAllocHint - Resolves the specified register allocation hint
533 /// to a physical register. Returns the physical register if it is successful.
534 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
535 const MachineFunction &MF) const {
536 if (Type == 0 && Reg && isPhysicalRegister(Reg))
541 /// UpdateRegAllocHint - A callback to allow target a chance to update
542 /// register allocation hints when a register is "changed" (e.g. coalesced)
543 /// to another register. e.g. On ARM, some virtual registers should target
544 /// register pairs, if one of pair is coalesced to another register, the
545 /// allocation hint of the other half of the pair should be changed to point
546 /// to the new register.
547 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
548 MachineFunction &MF) const {
552 /// targetHandlesStackFrameRounding - Returns true if the target is
553 /// responsible for rounding up the stack frame (probably at emitPrologue
555 virtual bool targetHandlesStackFrameRounding() const {
559 /// requiresRegisterScavenging - returns true if the target requires (and can
560 /// make use of) the register scavenger.
561 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
565 /// hasFP - Return true if the specified function should have a dedicated
566 /// frame pointer register. For most targets this is true only if the function
567 /// has variable sized allocas or if frame pointer elimination is disabled.
568 virtual bool hasFP(const MachineFunction &MF) const = 0;
570 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
571 /// not required, we reserve argument space for call sites in the function
572 /// immediately on entry to the current function. This eliminates the need for
573 /// add/sub sp brackets around call sites. Returns true if the call frame is
574 /// included as part of the stack frame.
575 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
579 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
580 /// the stack frame of the given function for the specified register. e.g. On
581 /// x86, if the frame register is required, the first fixed stack object is
582 /// reserved as its spill slot. This tells PEI not to create a new stack frame
583 /// object for the given register. It should be called only after
584 /// processFunctionBeforeCalleeSavedScan().
585 virtual bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
586 int &FrameIdx) const {
590 /// needsStackRealignment - true if storage within the function requires the
591 /// stack pointer to be aligned more than the normal calling convention calls
593 virtual bool needsStackRealignment(const MachineFunction &MF) const {
597 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
598 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
599 /// targets use pseudo instructions in order to abstract away the difference
600 /// between operating with a frame pointer and operating without, through the
601 /// use of these two instructions.
603 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
604 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
606 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
607 /// code insertion to eliminate call frame setup and destroy pseudo
608 /// instructions (but only if the Target is using them). It is responsible
609 /// for eliminating these instructions, replacing them with concrete
610 /// instructions. This method need only be implemented if using call frame
611 /// setup/destroy pseudo instructions.
614 eliminateCallFramePseudoInstr(MachineFunction &MF,
615 MachineBasicBlock &MBB,
616 MachineBasicBlock::iterator MI) const {
617 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
618 "eliminateCallFramePseudoInstr must be implemented if using"
619 " call frame setup/destroy pseudo instructions!");
620 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
623 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
624 /// before PrologEpilogInserter scans the physical registers used to determine
625 /// what callee saved registers should be spilled. This method is optional.
626 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
627 RegScavenger *RS = NULL) const {
631 /// processFunctionBeforeFrameFinalized - This method is called immediately
632 /// before the specified functions frame layout (MF.getFrameInfo()) is
633 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
634 /// replaced with direct constants. This method is optional.
636 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
639 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
640 /// frame indices from instructions which may use them. The instruction
641 /// referenced by the iterator contains an MO_FrameIndex operand which must be
642 /// eliminated by this method. This method may modify or replace the
643 /// specified instruction, as long as it keeps the iterator pointing the the
644 /// finished product. SPAdj is the SP adjustment due to call frame setup
646 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
647 int SPAdj, RegScavenger *RS=NULL) const = 0;
649 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
651 virtual void emitPrologue(MachineFunction &MF) const = 0;
652 virtual void emitEpilogue(MachineFunction &MF,
653 MachineBasicBlock &MBB) const = 0;
655 //===--------------------------------------------------------------------===//
656 /// Debug information queries.
658 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
659 /// number. Returns -1 if there is no equivalent value. The second
660 /// parameter allows targets to use different numberings for EH info and
662 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
664 /// getFrameRegister - This method should return the register used as a base
665 /// for values allocated in the current stack frame.
666 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
668 /// getFrameIndexOffset - Returns the displacement from the frame register to
669 /// the stack frame of the specified index.
670 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
672 /// getRARegister - This method should return the register where the return
673 /// address can be found.
674 virtual unsigned getRARegister() const = 0;
676 /// getInitialFrameState - Returns a list of machine moves that are assumed
677 /// on entry to all functions. Note that LabelID is ignored (assumed to be
678 /// the beginning of the function.)
679 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
683 // This is useful when building IndexedMaps keyed on virtual registers
684 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
685 unsigned operator()(unsigned Reg) const {
686 return Reg - TargetRegisterInfo::FirstVirtualRegister;
690 /// getCommonSubClass - find the largest common subclass of A and B. Return NULL
691 /// if there is no common subclass.
692 const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
693 const TargetRegisterClass *B);
695 } // End llvm namespace