1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/IR/CallingConv.h"
23 #include "llvm/MC/MCRegisterInfo.h"
30 class MachineFunction;
32 template<class T> class SmallVectorImpl;
36 class TargetRegisterClass {
38 typedef const MCPhysReg* iterator;
39 typedef const MCPhysReg* const_iterator;
40 typedef const MVT::SimpleValueType* vt_iterator;
41 typedef const TargetRegisterClass* const * sc_iterator;
43 // Instance variables filled by tablegen, do not use!
44 const MCRegisterClass *MC;
45 const vt_iterator VTs;
46 const uint32_t *SubClassMask;
47 const uint16_t *SuperRegIndices;
48 const sc_iterator SuperClasses;
49 ArrayRef<MCPhysReg> (*OrderFunc)(const MachineFunction&);
51 /// getID() - Return the register class ID number.
53 unsigned getID() const { return MC->getID(); }
55 /// getName() - Return the register class name for debugging.
57 const char *getName() const { return MC->getName(); }
59 /// begin/end - Return all of the registers in this class.
61 iterator begin() const { return MC->begin(); }
62 iterator end() const { return MC->end(); }
64 /// getNumRegs - Return the number of registers in this class.
66 unsigned getNumRegs() const { return MC->getNumRegs(); }
68 /// getRegister - Return the specified register in the class.
70 unsigned getRegister(unsigned i) const {
71 return MC->getRegister(i);
74 /// contains - Return true if the specified register is included in this
75 /// register class. This does not include virtual registers.
76 bool contains(unsigned Reg) const {
77 return MC->contains(Reg);
80 /// contains - Return true if both registers are in this class.
81 bool contains(unsigned Reg1, unsigned Reg2) const {
82 return MC->contains(Reg1, Reg2);
85 /// getSize - Return the size of the register in bytes, which is also the size
86 /// of a stack slot allocated to hold a spilled copy of this register.
87 unsigned getSize() const { return MC->getSize(); }
89 /// getAlignment - Return the minimum required alignment for a register of
91 unsigned getAlignment() const { return MC->getAlignment(); }
93 /// getCopyCost - Return the cost of copying a value between two registers in
94 /// this class. A negative number means the register class is very expensive
95 /// to copy e.g. status flag register classes.
96 int getCopyCost() const { return MC->getCopyCost(); }
98 /// isAllocatable - Return true if this register class may be used to create
99 /// virtual registers.
100 bool isAllocatable() const { return MC->isAllocatable(); }
102 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
104 bool hasType(EVT vt) const {
105 for(int i = 0; VTs[i] != MVT::Other; ++i)
106 if (EVT(VTs[i]) == vt)
111 /// vt_begin / vt_end - Loop over all of the value types that can be
112 /// represented by values in this register class.
113 vt_iterator vt_begin() const {
117 vt_iterator vt_end() const {
119 while (*I != MVT::Other) ++I;
123 /// hasSubClass - return true if the specified TargetRegisterClass
124 /// is a proper sub-class of this TargetRegisterClass.
125 bool hasSubClass(const TargetRegisterClass *RC) const {
126 return RC != this && hasSubClassEq(RC);
129 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
131 bool hasSubClassEq(const TargetRegisterClass *RC) const {
132 unsigned ID = RC->getID();
133 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
136 /// hasSuperClass - return true if the specified TargetRegisterClass is a
137 /// proper super-class of this TargetRegisterClass.
138 bool hasSuperClass(const TargetRegisterClass *RC) const {
139 return RC->hasSubClass(this);
142 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
144 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
145 return RC->hasSubClassEq(this);
148 /// getSubClassMask - Returns a bit vector of subclasses, including this one.
149 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
151 const uint32_t *getSubClassMask() const {
155 /// getSuperRegIndices - Returns a 0-terminated list of sub-register indices
156 /// that project some super-register class into this register class. The list
157 /// has an entry for each Idx such that:
159 /// There exists SuperRC where:
160 /// For all Reg in SuperRC:
161 /// this->contains(Reg:Idx)
163 const uint16_t *getSuperRegIndices() const {
164 return SuperRegIndices;
167 /// getSuperClasses - Returns a NULL terminated list of super-classes. The
168 /// classes are ordered by ID which is also a topological ordering from large
169 /// to small classes. The list does NOT include the current class.
170 sc_iterator getSuperClasses() const {
174 /// isASubClass - return true if this TargetRegisterClass is a subset
175 /// class of at least one other TargetRegisterClass.
176 bool isASubClass() const {
177 return SuperClasses[0] != 0;
180 /// getRawAllocationOrder - Returns the preferred order for allocating
181 /// registers from this register class in MF. The raw order comes directly
182 /// from the .td file and may include reserved registers that are not
183 /// allocatable. Register allocators should also make sure to allocate
184 /// callee-saved registers only after all the volatiles are used. The
185 /// RegisterClassInfo class provides filtered allocation orders with
186 /// callee-saved registers moved to the end.
188 /// The MachineFunction argument can be used to tune the allocatable
189 /// registers based on the characteristics of the function, subtarget, or
192 /// By default, this method returns all registers in the class.
194 ArrayRef<MCPhysReg> getRawAllocationOrder(const MachineFunction &MF) const {
195 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
199 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
200 /// registers. These are used by codegen, not by MC.
201 struct TargetRegisterInfoDesc {
202 unsigned CostPerUse; // Extra cost of instructions using register.
203 bool inAllocatableClass; // Register belongs to an allocatable regclass.
206 /// Each TargetRegisterClass has a per register weight, and weight
207 /// limit which must be less than the limits of its pressure sets.
208 struct RegClassWeight {
210 unsigned WeightLimit;
213 /// TargetRegisterInfo base class - We assume that the target defines a static
214 /// array of TargetRegisterDesc objects that represent all of the machine
215 /// registers that the target has. As such, we simply have to track a pointer
216 /// to this array so that we can turn register number into a register
219 class TargetRegisterInfo : public MCRegisterInfo {
221 typedef const TargetRegisterClass * const * regclass_iterator;
223 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
224 const char *const *SubRegIndexNames; // Names of subreg indexes.
225 // Pointer to array of lane masks, one per sub-reg index.
226 const unsigned *SubRegIndexLaneMasks;
228 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
229 unsigned CoveringLanes;
232 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
233 regclass_iterator RegClassBegin,
234 regclass_iterator RegClassEnd,
235 const char *const *SRINames,
236 const unsigned *SRILaneMasks,
237 unsigned CoveringLanes);
238 virtual ~TargetRegisterInfo();
241 // Register numbers can represent physical registers, virtual registers, and
242 // sometimes stack slots. The unsigned values are divided into these ranges:
244 // 0 Not a register, can be used as a sentinel.
245 // [1;2^30) Physical registers assigned by TableGen.
246 // [2^30;2^31) Stack slots. (Rarely used.)
247 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
249 // Further sentinels can be allocated from the small negative integers.
250 // DenseMapInfo<unsigned> uses -1u and -2u.
252 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
253 /// frame index in a variable that normally holds a register. isStackSlot()
254 /// returns true if Reg is in the range used for stack slots.
256 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
257 /// slots, so if a variable may contains a stack slot, always check
258 /// isStackSlot() first.
260 static bool isStackSlot(unsigned Reg) {
261 return int(Reg) >= (1 << 30);
264 /// stackSlot2Index - Compute the frame index from a register value
265 /// representing a stack slot.
266 static int stackSlot2Index(unsigned Reg) {
267 assert(isStackSlot(Reg) && "Not a stack slot");
268 return int(Reg - (1u << 30));
271 /// index2StackSlot - Convert a non-negative frame index to a stack slot
273 static unsigned index2StackSlot(int FI) {
274 assert(FI >= 0 && "Cannot hold a negative frame index.");
275 return FI + (1u << 30);
278 /// isPhysicalRegister - Return true if the specified register number is in
279 /// the physical register namespace.
280 static bool isPhysicalRegister(unsigned Reg) {
281 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
285 /// isVirtualRegister - Return true if the specified register number is in
286 /// the virtual register namespace.
287 static bool isVirtualRegister(unsigned Reg) {
288 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
292 /// virtReg2Index - Convert a virtual register number to a 0-based index.
293 /// The first virtual register in a function will get the index 0.
294 static unsigned virtReg2Index(unsigned Reg) {
295 assert(isVirtualRegister(Reg) && "Not a virtual register");
296 return Reg & ~(1u << 31);
299 /// index2VirtReg - Convert a 0-based index to a virtual register number.
300 /// This is the inverse operation of VirtReg2IndexFunctor below.
301 static unsigned index2VirtReg(unsigned Index) {
302 return Index | (1u << 31);
305 /// getMinimalPhysRegClass - Returns the Register Class of a physical
306 /// register of the given type, picking the most sub register class of
307 /// the right type that contains this physreg.
308 const TargetRegisterClass *
309 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
311 /// getAllocatableClass - Return the maximal subclass of the given register
312 /// class that is alloctable, or NULL.
313 const TargetRegisterClass *
314 getAllocatableClass(const TargetRegisterClass *RC) const;
316 /// getAllocatableSet - Returns a bitset indexed by register number
317 /// indicating if a register is allocatable or not. If a register class is
318 /// specified, returns the subset for the class.
319 BitVector getAllocatableSet(const MachineFunction &MF,
320 const TargetRegisterClass *RC = NULL) const;
322 /// getCostPerUse - Return the additional cost of using this register instead
323 /// of other registers in its class.
324 unsigned getCostPerUse(unsigned RegNo) const {
325 return InfoDesc[RegNo].CostPerUse;
328 /// isInAllocatableClass - Return true if the register is in the allocation
329 /// of any register class.
330 bool isInAllocatableClass(unsigned RegNo) const {
331 return InfoDesc[RegNo].inAllocatableClass;
334 /// getSubRegIndexName - Return the human-readable symbolic target-specific
335 /// name for the specified SubRegIndex.
336 const char *getSubRegIndexName(unsigned SubIdx) const {
337 assert(SubIdx && SubIdx < getNumSubRegIndices() &&
338 "This is not a subregister index");
339 return SubRegIndexNames[SubIdx-1];
342 /// getSubRegIndexLaneMask - Return a bitmask representing the parts of a
343 /// register that are covered by SubIdx.
345 /// Lane masks for sub-register indices are similar to register units for
346 /// physical registers. The individual bits in a lane mask can't be assigned
347 /// any specific meaning. They can be used to check if two sub-register
350 /// If the target has a register such that:
352 /// getSubReg(Reg, A) overlaps getSubReg(Reg, B)
356 /// getSubRegIndexLaneMask(A) & getSubRegIndexLaneMask(B) != 0
358 /// The converse is not necessarily true. If two lane masks have a common
359 /// bit, the corresponding sub-registers may not overlap, but it can be
360 /// assumed that they usually will.
361 unsigned getSubRegIndexLaneMask(unsigned SubIdx) const {
362 // SubIdx == 0 is allowed, it has the lane mask ~0u.
363 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index");
364 return SubRegIndexLaneMasks[SubIdx];
367 /// The lane masks returned by getSubRegIndexLaneMask() above can only be
368 /// used to determine if sub-registers overlap - they can't be used to
369 /// determine if a set of sub-registers completely cover another
372 /// The X86 general purpose registers have two lanes corresponding to the
373 /// sub_8bit and sub_8bit_hi sub-registers. Both sub_32bit and sub_16bit have
374 /// lane masks '3', but the sub_16bit sub-register doesn't fully cover the
375 /// sub_32bit sub-register.
377 /// On the other hand, the ARM NEON lanes fully cover their registers: The
378 /// dsub_0 sub-register is completely covered by the ssub_0 and ssub_1 lanes.
379 /// This is related to the CoveredBySubRegs property on register definitions.
381 /// This function returns a bit mask of lanes that completely cover their
382 /// sub-registers. More precisely, given:
384 /// Covering = getCoveringLanes();
385 /// MaskA = getSubRegIndexLaneMask(SubA);
386 /// MaskB = getSubRegIndexLaneMask(SubB);
388 /// If (MaskA & ~(MaskB & Covering)) == 0, then SubA is completely covered by
390 unsigned getCoveringLanes() const { return CoveringLanes; }
392 /// regsOverlap - Returns true if the two registers are equal or alias each
393 /// other. The registers may be virtual register.
394 bool regsOverlap(unsigned regA, unsigned regB) const {
395 if (regA == regB) return true;
396 if (isVirtualRegister(regA) || isVirtualRegister(regB))
399 // Regunits are numerically ordered. Find a common unit.
400 MCRegUnitIterator RUA(regA, this);
401 MCRegUnitIterator RUB(regB, this);
403 if (*RUA == *RUB) return true;
404 if (*RUA < *RUB) ++RUA;
406 } while (RUA.isValid() && RUB.isValid());
410 /// hasRegUnit - Returns true if Reg contains RegUnit.
411 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const {
412 for (MCRegUnitIterator Units(Reg, this); Units.isValid(); ++Units)
413 if (*Units == RegUnit)
418 /// getCalleeSavedRegs - Return a null-terminated list of all of the
419 /// callee saved registers on this target. The register should be in the
420 /// order of desired callee-save stack frame offset. The first register is
421 /// closest to the incoming stack pointer if stack grows down, and vice versa.
423 virtual const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF = 0)
426 /// getCallPreservedMask - Return a mask of call-preserved registers for the
427 /// given calling convention on the current sub-target. The mask should
428 /// include all call-preserved aliases. This is used by the register
429 /// allocator to determine which registers can be live across a call.
431 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
432 /// A set bit indicates that all bits of the corresponding register are
433 /// preserved across the function call. The bit mask is expected to be
434 /// sub-register complete, i.e. if A is preserved, so are all its
437 /// Bits are numbered from the LSB, so the bit for physical register Reg can
438 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
440 /// A NULL pointer means that no register mask will be used, and call
441 /// instructions should use implicit-def operands to indicate call clobbered
444 virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const {
445 // The default mask clobbers everything. All targets should override.
449 /// getReservedRegs - Returns a bitset indexed by physical register number
450 /// indicating if a register is a special register that has particular uses
451 /// and should be considered unavailable at all times, e.g. SP, RA. This is
452 /// used by register scavenger to determine what registers are free.
453 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
455 /// getMatchingSuperReg - Return a super-register of the specified register
456 /// Reg so its sub-register of index SubIdx is Reg.
457 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
458 const TargetRegisterClass *RC) const {
459 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
462 /// getMatchingSuperRegClass - Return a subclass of the specified register
463 /// class A so that each register in it has a sub-register of the
464 /// specified sub-register index which is in the specified register class B.
466 /// TableGen will synthesize missing A sub-classes.
467 virtual const TargetRegisterClass *
468 getMatchingSuperRegClass(const TargetRegisterClass *A,
469 const TargetRegisterClass *B, unsigned Idx) const;
471 /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that
472 /// supports the sub-register index Idx.
473 /// If no such sub-class exists, return NULL.
474 /// If all registers in RC already have an Idx sub-register, return RC.
476 /// TableGen generates a version of this function that is good enough in most
477 /// cases. Targets can override if they have constraints that TableGen
478 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
479 /// supported by the full GR32 register class in 64-bit mode, but only by the
480 /// GR32_ABCD regiister class in 32-bit mode.
482 /// TableGen will synthesize missing RC sub-classes.
483 virtual const TargetRegisterClass *
484 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
485 assert(Idx == 0 && "Target has no sub-registers");
489 /// composeSubRegIndices - Return the subregister index you get from composing
490 /// two subregister indices.
492 /// The special null sub-register index composes as the identity.
494 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
495 /// returns c. Note that composeSubRegIndices does not tell you about illegal
496 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
497 /// b, composeSubRegIndices doesn't tell you.
499 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
500 /// ssub_0:S0 - ssub_3:S3 subregs.
501 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
503 unsigned composeSubRegIndices(unsigned a, unsigned b) const {
506 return composeSubRegIndicesImpl(a, b);
510 /// Overridden by TableGen in targets that have sub-registers.
511 virtual unsigned composeSubRegIndicesImpl(unsigned, unsigned) const {
512 llvm_unreachable("Target has no sub-registers");
516 /// getCommonSuperRegClass - Find a common super-register class if it exists.
518 /// Find a register class, SuperRC and two sub-register indices, PreA and
521 /// 1. PreA + SubA == PreB + SubB (using composeSubRegIndices()), and
523 /// 2. For all Reg in SuperRC: Reg:PreA in RCA and Reg:PreB in RCB, and
525 /// 3. SuperRC->getSize() >= max(RCA->getSize(), RCB->getSize()).
527 /// SuperRC will be chosen such that no super-class of SuperRC satisfies the
528 /// requirements, and there is no register class with a smaller spill size
529 /// that satisfies the requirements.
531 /// SubA and SubB must not be 0. Use getMatchingSuperRegClass() instead.
533 /// Either of the PreA and PreB sub-register indices may be returned as 0. In
534 /// that case, the returned register class will be a sub-class of the
535 /// corresponding argument register class.
537 /// The function returns NULL if no register class can be found.
539 const TargetRegisterClass*
540 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
541 const TargetRegisterClass *RCB, unsigned SubB,
542 unsigned &PreA, unsigned &PreB) const;
544 //===--------------------------------------------------------------------===//
545 // Register Class Information
548 /// Register class iterators
550 regclass_iterator regclass_begin() const { return RegClassBegin; }
551 regclass_iterator regclass_end() const { return RegClassEnd; }
553 unsigned getNumRegClasses() const {
554 return (unsigned)(regclass_end()-regclass_begin());
557 /// getRegClass - Returns the register class associated with the enumeration
558 /// value. See class MCOperandInfo.
559 const TargetRegisterClass *getRegClass(unsigned i) const {
560 assert(i < getNumRegClasses() && "Register Class ID out of range");
561 return RegClassBegin[i];
564 /// getCommonSubClass - find the largest common subclass of A and B. Return
565 /// NULL if there is no common subclass.
566 const TargetRegisterClass *
567 getCommonSubClass(const TargetRegisterClass *A,
568 const TargetRegisterClass *B) const;
570 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
571 /// values. If a target supports multiple different pointer register classes,
572 /// kind specifies which one is indicated.
573 virtual const TargetRegisterClass *
574 getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const {
575 llvm_unreachable("Target didn't implement getPointerRegClass!");
578 /// getCrossCopyRegClass - Returns a legal register class to copy a register
579 /// in the specified class to or from. If it is possible to copy the register
580 /// directly without using a cross register class copy, return the specified
581 /// RC. Returns NULL if it is not possible to copy between a two registers of
582 /// the specified class.
583 virtual const TargetRegisterClass *
584 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
588 /// getLargestLegalSuperClass - Returns the largest super class of RC that is
589 /// legal to use in the current sub-target and has the same spill size.
590 /// The returned register class can be used to create virtual registers which
591 /// means that all its registers can be copied and spilled.
592 virtual const TargetRegisterClass*
593 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
594 /// The default implementation is very conservative and doesn't allow the
595 /// register allocator to inflate register classes.
599 /// getRegPressureLimit - Return the register pressure "high water mark" for
600 /// the specific register class. The scheduler is in high register pressure
601 /// mode (for the specific register class) if it goes over the limit.
603 /// Note: this is the old register pressure model that relies on a manually
604 /// specified representative register class per value type.
605 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
606 MachineFunction &MF) const {
610 /// Get the weight in units of pressure for this register class.
611 virtual const RegClassWeight &getRegClassWeight(
612 const TargetRegisterClass *RC) const = 0;
614 /// Get the weight in units of pressure for this register unit.
615 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
617 /// Get the number of dimensions of register pressure.
618 virtual unsigned getNumRegPressureSets() const = 0;
620 /// Get the name of this register unit pressure set.
621 virtual const char *getRegPressureSetName(unsigned Idx) const = 0;
623 /// Get the register unit pressure limit for this dimension.
624 /// This limit must be adjusted dynamically for reserved registers.
625 virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0;
627 /// Get the dimensions of register pressure impacted by this register class.
628 /// Returns a -1 terminated array of pressure set IDs.
629 virtual const int *getRegClassPressureSets(
630 const TargetRegisterClass *RC) const = 0;
632 /// Get the dimensions of register pressure impacted by this register unit.
633 /// Returns a -1 terminated array of pressure set IDs.
634 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
636 /// Get a list of 'hint' registers that the register allocator should try
637 /// first when allocating a physical register for the virtual register
638 /// VirtReg. These registers are effectively moved to the front of the
639 /// allocation order.
641 /// The Order argument is the allocation order for VirtReg's register class
642 /// as returned from RegisterClassInfo::getOrder(). The hint registers must
643 /// come from Order, and they must not be reserved.
645 /// The default implementation of this function can resolve
646 /// target-independent hints provided to MRI::setRegAllocationHint with
647 /// HintType == 0. Targets that override this function should defer to the
648 /// default implementation if they have no reason to change the allocation
649 /// order for VirtReg. There may be target-independent hints.
650 virtual void getRegAllocationHints(unsigned VirtReg,
651 ArrayRef<MCPhysReg> Order,
652 SmallVectorImpl<MCPhysReg> &Hints,
653 const MachineFunction &MF,
654 const VirtRegMap *VRM = 0) const;
656 /// avoidWriteAfterWrite - Return true if the register allocator should avoid
657 /// writing a register from RC in two consecutive instructions.
658 /// This can avoid pipeline stalls on certain architectures.
659 /// It does cause increased register pressure, though.
660 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
664 /// UpdateRegAllocHint - A callback to allow target a chance to update
665 /// register allocation hints when a register is "changed" (e.g. coalesced)
666 /// to another register. e.g. On ARM, some virtual registers should target
667 /// register pairs, if one of pair is coalesced to another register, the
668 /// allocation hint of the other half of the pair should be changed to point
669 /// to the new register.
670 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
671 MachineFunction &MF) const {
675 /// Allow the target to reverse allocation order of local live ranges. This
676 /// will generally allocate shorter local live ranges first. For targets with
677 /// many registers, this could reduce regalloc compile time by a large
678 /// factor. It is disabled by default for three reasons:
679 /// (1) Top-down allocation is simpler and easier to debug for targets that
680 /// don't benefit from reversing the order.
681 /// (2) Bottom-up allocation could result in poor evicition decisions on some
682 /// targets affecting the performance of compiled code.
683 /// (3) Bottom-up allocation is no longer guaranteed to optimally color.
684 virtual bool reverseLocalAssignment() const { return false; }
686 /// Allow the target to override register assignment heuristics based on the
687 /// live range size. If this returns false, then local live ranges are always
688 /// assigned in order regardless of their size. This is a temporary hook for
689 /// debugging downstream codegen failures exposed by regalloc.
690 virtual bool mayOverrideLocalAssignment() const { return true; }
692 /// Allow the target to override the cost of using a callee-saved register for
693 /// the first time. Default value of 0 means we will use a callee-saved
694 /// register if it is available.
695 virtual unsigned getCSRFirstUseCost() const { return 0; }
697 /// requiresRegisterScavenging - returns true if the target requires (and can
698 /// make use of) the register scavenger.
699 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
703 /// useFPForScavengingIndex - returns true if the target wants to use
704 /// frame pointer based accesses to spill to the scavenger emergency spill
706 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
710 /// requiresFrameIndexScavenging - returns true if the target requires post
711 /// PEI scavenging of registers for materializing frame index constants.
712 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
716 /// requiresVirtualBaseRegisters - Returns true if the target wants the
717 /// LocalStackAllocation pass to be run and virtual base registers
718 /// used for more efficient stack access.
719 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
723 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
724 /// the stack frame of the given function for the specified register. e.g. On
725 /// x86, if the frame register is required, the first fixed stack object is
726 /// reserved as its spill slot. This tells PEI not to create a new stack frame
727 /// object for the given register. It should be called only after
728 /// processFunctionBeforeCalleeSavedScan().
729 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
730 int &FrameIdx) const {
734 /// trackLivenessAfterRegAlloc - returns true if the live-ins should be tracked
735 /// after register allocation.
736 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
740 /// needsStackRealignment - true if storage within the function requires the
741 /// stack pointer to be aligned more than the normal calling convention calls
743 virtual bool needsStackRealignment(const MachineFunction &MF) const {
747 /// getFrameIndexInstrOffset - Get the offset from the referenced frame
748 /// index in the instruction, if there is one.
749 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
754 /// needsFrameBaseReg - Returns true if the instruction's frame index
755 /// reference would be better served by a base register other than FP
756 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
757 /// references it should create new base registers for.
758 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
762 /// materializeFrameBaseRegister - Insert defining instruction(s) for
763 /// BaseReg to be a pointer to FrameIdx before insertion point I.
764 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
765 unsigned BaseReg, int FrameIdx,
766 int64_t Offset) const {
767 llvm_unreachable("materializeFrameBaseRegister does not exist on this "
771 /// resolveFrameIndex - Resolve a frame index operand of an instruction
772 /// to reference the indicated base register plus offset instead.
773 virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
774 unsigned BaseReg, int64_t Offset) const {
775 llvm_unreachable("resolveFrameIndex does not exist on this target");
778 /// isFrameOffsetLegal - Determine whether a given offset immediate is
779 /// encodable to resolve a frame index.
780 virtual bool isFrameOffsetLegal(const MachineInstr *MI,
781 int64_t Offset) const {
782 llvm_unreachable("isFrameOffsetLegal does not exist on this target");
786 /// saveScavengerRegister - Spill the register so it can be used by the
787 /// register scavenger. Return true if the register was spilled, false
788 /// otherwise. If this function does not spill the register, the scavenger
789 /// will instead spill it to the emergency spill slot.
791 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
792 MachineBasicBlock::iterator I,
793 MachineBasicBlock::iterator &UseMI,
794 const TargetRegisterClass *RC,
795 unsigned Reg) const {
799 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
800 /// frame indices from instructions which may use them. The instruction
801 /// referenced by the iterator contains an MO_FrameIndex operand which must be
802 /// eliminated by this method. This method may modify or replace the
803 /// specified instruction, as long as it keeps the iterator pointing at the
804 /// finished product. SPAdj is the SP adjustment due to call frame setup
805 /// instruction. FIOperandNum is the FI operand number.
806 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
807 int SPAdj, unsigned FIOperandNum,
808 RegScavenger *RS = NULL) const = 0;
810 //===--------------------------------------------------------------------===//
811 /// Debug information queries.
813 /// getFrameRegister - This method should return the register used as a base
814 /// for values allocated in the current stack frame.
815 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
817 /// getCompactUnwindRegNum - This function maps the register to the number for
818 /// compact unwind encoding. Return -1 if the register isn't valid.
819 virtual int getCompactUnwindRegNum(unsigned, bool) const {
825 //===----------------------------------------------------------------------===//
826 // SuperRegClassIterator
827 //===----------------------------------------------------------------------===//
829 // Iterate over the possible super-registers for a given register class. The
830 // iterator will visit a list of pairs (Idx, Mask) corresponding to the
831 // possible classes of super-registers.
833 // Each bit mask will have at least one set bit, and each set bit in Mask
834 // corresponds to a SuperRC such that:
836 // For all Reg in SuperRC: Reg:Idx is in RC.
838 // The iterator can include (O, RC->getSubClassMask()) as the first entry which
839 // also satisfies the above requirement, assuming Reg:0 == Reg.
841 class SuperRegClassIterator {
842 const unsigned RCMaskWords;
845 const uint32_t *Mask;
848 /// Create a SuperRegClassIterator that visits all the super-register classes
849 /// of RC. When IncludeSelf is set, also include the (0, sub-classes) entry.
850 SuperRegClassIterator(const TargetRegisterClass *RC,
851 const TargetRegisterInfo *TRI,
852 bool IncludeSelf = false)
853 : RCMaskWords((TRI->getNumRegClasses() + 31) / 32),
855 Idx(RC->getSuperRegIndices()),
856 Mask(RC->getSubClassMask()) {
861 /// Returns true if this iterator is still pointing at a valid entry.
862 bool isValid() const { return Idx; }
864 /// Returns the current sub-register index.
865 unsigned getSubReg() const { return SubReg; }
867 /// Returns the bit mask if register classes that getSubReg() projects into
869 const uint32_t *getMask() const { return Mask; }
871 /// Advance iterator to the next entry.
873 assert(isValid() && "Cannot move iterator past end.");
881 // This is useful when building IndexedMaps keyed on virtual registers
882 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
883 unsigned operator()(unsigned Reg) const {
884 return TargetRegisterInfo::virtReg2Index(Reg);
888 /// PrintReg - Helper class for printing registers on a raw_ostream.
889 /// Prints virtual and physical registers with or without a TRI instance.
892 /// %noreg - NoRegister
893 /// %vreg5 - a virtual register.
894 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
895 /// %EAX - a physical register
896 /// %physreg17 - a physical register when no TRI instance given.
898 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
901 const TargetRegisterInfo *TRI;
905 explicit PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0,
907 : TRI(tri), Reg(reg), SubIdx(subidx) {}
908 void print(raw_ostream&) const;
911 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
916 /// PrintRegUnit - Helper class for printing register units on a raw_ostream.
918 /// Register units are named after their root registers:
920 /// AL - Single root.
921 /// FP0~ST7 - Dual roots.
923 /// Usage: OS << PrintRegUnit(Unit, TRI) << '\n';
927 const TargetRegisterInfo *TRI;
930 PrintRegUnit(unsigned unit, const TargetRegisterInfo *tri)
931 : TRI(tri), Unit(unit) {}
932 void print(raw_ostream&) const;
935 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintRegUnit &PR) {
940 /// PrintVRegOrUnit - It is often convenient to track virtual registers and
941 /// physical register units in the same list.
942 class PrintVRegOrUnit : protected PrintRegUnit {
944 PrintVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *tri)
945 : PrintRegUnit(VRegOrUnit, tri) {}
946 void print(raw_ostream&) const;
949 static inline raw_ostream &operator<<(raw_ostream &OS,
950 const PrintVRegOrUnit &PR) {
955 } // End llvm namespace