1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/DenseSet.h"
28 class MachineFunction;
31 template<class T> class SmallVectorImpl;
34 /// TargetRegisterDesc - This record contains all of the information known about
35 /// a particular register. The AliasSet field (if not null) contains a pointer
36 /// to a Zero terminated array of registers that this register aliases. This is
37 /// needed for architectures like X86 which have AL alias AX alias EAX.
38 /// Registers that this does not apply to simply should set this to null.
39 /// The SubRegs field is a zero terminated array of registers that are
40 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
41 /// The SuperRegs field is a zero terminated array of registers that are
42 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
45 struct TargetRegisterDesc {
46 const char *Name; // Printable name for the reg (for debugging)
47 const unsigned *AliasSet; // Register Alias Set, described above
48 const unsigned *SubRegs; // Sub-register set, described above
49 const unsigned *SuperRegs; // Super-register set, described above
52 class TargetRegisterClass {
54 typedef const unsigned* iterator;
55 typedef const unsigned* const_iterator;
57 typedef const EVT* vt_iterator;
58 typedef const TargetRegisterClass* const * sc_iterator;
62 const vt_iterator VTs;
63 const sc_iterator SubClasses;
64 const sc_iterator SuperClasses;
65 const sc_iterator SubRegClasses;
66 const sc_iterator SuperRegClasses;
67 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
69 const iterator RegsBegin, RegsEnd;
70 DenseSet<unsigned> RegSet;
72 TargetRegisterClass(unsigned id,
75 const TargetRegisterClass * const *subcs,
76 const TargetRegisterClass * const *supcs,
77 const TargetRegisterClass * const *subregcs,
78 const TargetRegisterClass * const *superregcs,
79 unsigned RS, unsigned Al, int CC,
80 iterator RB, iterator RE)
81 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
82 SubRegClasses(subregcs), SuperRegClasses(superregcs),
83 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {
84 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
87 virtual ~TargetRegisterClass() {} // Allow subclasses
89 /// getID() - Return the register class ID number.
91 unsigned getID() const { return ID; }
93 /// getName() - Return the register class name for debugging.
95 const char *getName() const { return Name; }
97 /// begin/end - Return all of the registers in this class.
99 iterator begin() const { return RegsBegin; }
100 iterator end() const { return RegsEnd; }
102 /// getNumRegs - Return the number of registers in this class.
104 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
106 /// getRegister - Return the specified register in the class.
108 unsigned getRegister(unsigned i) const {
109 assert(i < getNumRegs() && "Register number out of range!");
113 /// contains - Return true if the specified register is included in this
114 /// register class. This does not include virtual registers.
115 bool contains(unsigned Reg) const {
116 return RegSet.count(Reg);
119 /// contains - Return true if both registers are in this class.
120 bool contains(unsigned Reg1, unsigned Reg2) const {
121 return contains(Reg1) && contains(Reg2);
124 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
126 bool hasType(EVT vt) const {
127 for(int i = 0; VTs[i] != MVT::Other; ++i)
133 /// vt_begin / vt_end - Loop over all of the value types that can be
134 /// represented by values in this register class.
135 vt_iterator vt_begin() const {
139 vt_iterator vt_end() const {
141 while (*I != MVT::Other) ++I;
145 /// subregclasses_begin / subregclasses_end - Loop over all of
146 /// the subreg register classes of this register class.
147 sc_iterator subregclasses_begin() const {
148 return SubRegClasses;
151 sc_iterator subregclasses_end() const {
152 sc_iterator I = SubRegClasses;
153 while (*I != NULL) ++I;
157 /// getSubRegisterRegClass - Return the register class of subregisters with
158 /// index SubIdx, or NULL if no such class exists.
159 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
160 assert(SubIdx>0 && "Invalid subregister index");
161 return SubRegClasses[SubIdx-1];
164 /// superregclasses_begin / superregclasses_end - Loop over all of
165 /// the superreg register classes of this register class.
166 sc_iterator superregclasses_begin() const {
167 return SuperRegClasses;
170 sc_iterator superregclasses_end() const {
171 sc_iterator I = SuperRegClasses;
172 while (*I != NULL) ++I;
176 /// hasSubClass - return true if the specified TargetRegisterClass
177 /// is a proper subset of this TargetRegisterClass.
178 bool hasSubClass(const TargetRegisterClass *cs) const {
179 for (int i = 0; SubClasses[i] != NULL; ++i)
180 if (SubClasses[i] == cs)
185 /// subclasses_begin / subclasses_end - Loop over all of the classes
186 /// that are proper subsets of this register class.
187 sc_iterator subclasses_begin() const {
191 sc_iterator subclasses_end() const {
192 sc_iterator I = SubClasses;
193 while (*I != NULL) ++I;
197 /// hasSuperClass - return true if the specified TargetRegisterClass is a
198 /// proper superset of this TargetRegisterClass.
199 bool hasSuperClass(const TargetRegisterClass *cs) const {
200 for (int i = 0; SuperClasses[i] != NULL; ++i)
201 if (SuperClasses[i] == cs)
206 /// superclasses_begin / superclasses_end - Loop over all of the classes
207 /// that are proper supersets of this register class.
208 sc_iterator superclasses_begin() const {
212 sc_iterator superclasses_end() const {
213 sc_iterator I = SuperClasses;
214 while (*I != NULL) ++I;
218 /// isASubClass - return true if this TargetRegisterClass is a subset
219 /// class of at least one other TargetRegisterClass.
220 bool isASubClass() const {
221 return SuperClasses[0] != 0;
224 /// allocation_order_begin/end - These methods define a range of registers
225 /// which specify the registers in this class that are valid to register
226 /// allocate, and the preferred order to allocate them in. For example,
227 /// callee saved registers should be at the end of the list, because it is
228 /// cheaper to allocate caller saved registers.
230 /// These methods take a MachineFunction argument, which can be used to tune
231 /// the allocatable registers based on the characteristics of the function,
232 /// subtarget, or other criteria.
234 /// Register allocators should account for the fact that an allocation
235 /// order iterator may return a reserved register and always check
236 /// if the register is allocatable (getAllocatableSet()) before using it.
238 /// By default, these methods return all registers in the class.
240 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
243 virtual iterator allocation_order_end(const MachineFunction &MF) const {
247 /// getSize - Return the size of the register in bytes, which is also the size
248 /// of a stack slot allocated to hold a spilled copy of this register.
249 unsigned getSize() const { return RegSize; }
251 /// getAlignment - Return the minimum required alignment for a register of
253 unsigned getAlignment() const { return Alignment; }
255 /// getCopyCost - Return the cost of copying a value between two registers in
256 /// this class. A negative number means the register class is very expensive
257 /// to copy e.g. status flag register classes.
258 int getCopyCost() const { return CopyCost; }
262 /// TargetRegisterInfo base class - We assume that the target defines a static
263 /// array of TargetRegisterDesc objects that represent all of the machine
264 /// registers that the target has. As such, we simply have to track a pointer
265 /// to this array so that we can turn register number into a register
268 class TargetRegisterInfo {
270 const unsigned* SubregHash;
271 const unsigned SubregHashSize;
272 const unsigned* AliasesHash;
273 const unsigned AliasesHashSize;
275 typedef const TargetRegisterClass * const * regclass_iterator;
277 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
278 const char *const *SubRegIndexNames; // Names of subreg indexes.
279 unsigned NumRegs; // Number of entries in the array
281 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
283 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
286 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
287 regclass_iterator RegClassBegin,
288 regclass_iterator RegClassEnd,
289 const char *const *subregindexnames,
290 int CallFrameSetupOpcode = -1,
291 int CallFrameDestroyOpcode = -1,
292 const unsigned* subregs = 0,
293 const unsigned subregsize = 0,
294 const unsigned* aliases = 0,
295 const unsigned aliasessize = 0);
296 virtual ~TargetRegisterInfo();
299 enum { // Define some target independent constants
300 /// NoRegister - This physical register is not a real target register. It
301 /// is useful as a sentinal.
304 /// FirstVirtualRegister - This is the first register number that is
305 /// considered to be a 'virtual' register, which is part of the SSA
306 /// namespace. This must be the same for all targets, which means that each
307 /// target is limited to this fixed number of registers.
308 FirstVirtualRegister = 16384
311 /// isPhysicalRegister - Return true if the specified register number is in
312 /// the physical register namespace.
313 static bool isPhysicalRegister(unsigned Reg) {
314 assert(Reg && "this is not a register!");
315 return Reg < FirstVirtualRegister;
318 /// isVirtualRegister - Return true if the specified register number is in
319 /// the virtual register namespace.
320 static bool isVirtualRegister(unsigned Reg) {
321 assert(Reg && "this is not a register!");
322 return Reg >= FirstVirtualRegister;
325 /// printReg - Print a virtual or physical register on OS.
326 void printReg(unsigned Reg, raw_ostream &OS) const;
328 /// getMinimalPhysRegClass - Returns the Register Class of a physical
329 /// register of the given type, picking the most sub register class of
330 /// the right type that contains this physreg.
331 const TargetRegisterClass *
332 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
334 /// getAllocatableSet - Returns a bitset indexed by register number
335 /// indicating if a register is allocatable or not. If a register class is
336 /// specified, returns the subset for the class.
337 BitVector getAllocatableSet(const MachineFunction &MF,
338 const TargetRegisterClass *RC = NULL) const;
340 const TargetRegisterDesc &operator[](unsigned RegNo) const {
341 assert(RegNo < NumRegs &&
342 "Attempting to access record for invalid register number!");
346 /// Provide a get method, equivalent to [], but more useful if we have a
347 /// pointer to this object.
349 const TargetRegisterDesc &get(unsigned RegNo) const {
350 return operator[](RegNo);
353 /// getAliasSet - Return the set of registers aliased by the specified
354 /// register, or a null list of there are none. The list returned is zero
357 const unsigned *getAliasSet(unsigned RegNo) const {
358 return get(RegNo).AliasSet;
361 /// getSubRegisters - Return the list of registers that are sub-registers of
362 /// the specified register, or a null list of there are none. The list
363 /// returned is zero terminated and sorted according to super-sub register
364 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
366 const unsigned *getSubRegisters(unsigned RegNo) const {
367 return get(RegNo).SubRegs;
370 /// getSuperRegisters - Return the list of registers that are super-registers
371 /// of the specified register, or a null list of there are none. The list
372 /// returned is zero terminated and sorted according to super-sub register
373 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
375 const unsigned *getSuperRegisters(unsigned RegNo) const {
376 return get(RegNo).SuperRegs;
379 /// getName - Return the human-readable symbolic target-specific name for the
380 /// specified physical register.
381 const char *getName(unsigned RegNo) const {
382 return get(RegNo).Name;
385 /// getNumRegs - Return the number of registers this target has (useful for
386 /// sizing arrays holding per register information)
387 unsigned getNumRegs() const {
391 /// getSubRegIndexName - Return the human-readable symbolic target-specific
392 /// name for the specified SubRegIndex.
393 const char *getSubRegIndexName(unsigned SubIdx) const {
394 assert(SubIdx && "This is not a subregister index");
395 return SubRegIndexNames[SubIdx-1];
398 /// regsOverlap - Returns true if the two registers are equal or alias each
399 /// other. The registers may be virtual register.
400 bool regsOverlap(unsigned regA, unsigned regB) const {
404 if (isVirtualRegister(regA) || isVirtualRegister(regB))
407 // regA and regB are distinct physical registers. Do they alias?
408 size_t index = (regA + regB * 37) & (AliasesHashSize-1);
409 unsigned ProbeAmt = 0;
410 while (AliasesHash[index*2] != 0 &&
411 AliasesHash[index*2+1] != 0) {
412 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB)
415 index = (index + ProbeAmt) & (AliasesHashSize-1);
422 /// isSubRegister - Returns true if regB is a sub-register of regA.
424 bool isSubRegister(unsigned regA, unsigned regB) const {
425 // SubregHash is a simple quadratically probed hash table.
426 size_t index = (regA + regB * 37) & (SubregHashSize-1);
427 unsigned ProbeAmt = 2;
428 while (SubregHash[index*2] != 0 &&
429 SubregHash[index*2+1] != 0) {
430 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
433 index = (index + ProbeAmt) & (SubregHashSize-1);
440 /// isSuperRegister - Returns true if regB is a super-register of regA.
442 bool isSuperRegister(unsigned regA, unsigned regB) const {
443 return isSubRegister(regB, regA);
446 /// getCalleeSavedRegs - Return a null-terminated list of all of the
447 /// callee saved registers on this target. The register should be in the
448 /// order of desired callee-save stack frame offset. The first register is
449 /// closed to the incoming stack pointer if stack grows down, and vice versa.
450 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
454 /// getReservedRegs - Returns a bitset indexed by physical register number
455 /// indicating if a register is a special register that has particular uses
456 /// and should be considered unavailable at all times, e.g. SP, RA. This is
457 /// used by register scavenger to determine what registers are free.
458 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
460 /// getSubReg - Returns the physical register number of sub-register "Index"
461 /// for physical register RegNo. Return zero if the sub-register does not
463 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
465 /// getSubRegIndex - For a given register pair, return the sub-register index
466 /// if the second register is a sub-register of the first. Return zero
468 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
470 /// getMatchingSuperReg - Return a super-register of the specified register
471 /// Reg so its sub-register of index SubIdx is Reg.
472 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
473 const TargetRegisterClass *RC) const {
474 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
475 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
480 /// canCombineSubRegIndices - Given a register class and a list of
481 /// subregister indices, return true if it's possible to combine the
482 /// subregister indices into one that corresponds to a larger
483 /// subregister. Return the new subregister index by reference. Note the
484 /// new index may be zero if the given subregisters can be combined to
485 /// form the whole register.
486 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
487 SmallVectorImpl<unsigned> &SubIndices,
488 unsigned &NewSubIdx) const {
492 /// getMatchingSuperRegClass - Return a subclass of the specified register
493 /// class A so that each register in it has a sub-register of the
494 /// specified sub-register index which is in the specified register class B.
495 virtual const TargetRegisterClass *
496 getMatchingSuperRegClass(const TargetRegisterClass *A,
497 const TargetRegisterClass *B, unsigned Idx) const {
501 /// composeSubRegIndices - Return the subregister index you get from composing
502 /// two subregister indices.
504 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
505 /// returns c. Note that composeSubRegIndices does not tell you about illegal
506 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
507 /// b, composeSubRegIndices doesn't tell you.
509 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
510 /// ssub_0:S0 - ssub_3:S3 subregs.
511 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
513 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
514 // This default implementation is correct for most targets.
518 //===--------------------------------------------------------------------===//
519 // Register Class Information
522 /// Register class iterators
524 regclass_iterator regclass_begin() const { return RegClassBegin; }
525 regclass_iterator regclass_end() const { return RegClassEnd; }
527 unsigned getNumRegClasses() const {
528 return (unsigned)(regclass_end()-regclass_begin());
531 /// getRegClass - Returns the register class associated with the enumeration
532 /// value. See class TargetOperandInfo.
533 const TargetRegisterClass *getRegClass(unsigned i) const {
534 assert(i < getNumRegClasses() && "Register Class ID out of range");
535 return RegClassBegin[i];
538 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
539 /// values. If a target supports multiple different pointer register classes,
540 /// kind specifies which one is indicated.
541 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
542 assert(0 && "Target didn't implement getPointerRegClass!");
543 return 0; // Must return a value in order to compile with VS 2005
546 /// getCrossCopyRegClass - Returns a legal register class to copy a register
547 /// in the specified class to or from. Returns NULL if it is possible to copy
548 /// between a two registers of the specified class.
549 virtual const TargetRegisterClass *
550 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
554 /// getAllocationOrder - Returns the register allocation order for a specified
555 /// register class in the form of a pair of TargetRegisterClass iterators.
556 virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
557 getAllocationOrder(const TargetRegisterClass *RC,
558 unsigned HintType, unsigned HintReg,
559 const MachineFunction &MF) const {
560 return std::make_pair(RC->allocation_order_begin(MF),
561 RC->allocation_order_end(MF));
564 /// ResolveRegAllocHint - Resolves the specified register allocation hint
565 /// to a physical register. Returns the physical register if it is successful.
566 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
567 const MachineFunction &MF) const {
568 if (Type == 0 && Reg && isPhysicalRegister(Reg))
573 /// UpdateRegAllocHint - A callback to allow target a chance to update
574 /// register allocation hints when a register is "changed" (e.g. coalesced)
575 /// to another register. e.g. On ARM, some virtual registers should target
576 /// register pairs, if one of pair is coalesced to another register, the
577 /// allocation hint of the other half of the pair should be changed to point
578 /// to the new register.
579 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
580 MachineFunction &MF) const {
584 /// requiresRegisterScavenging - returns true if the target requires (and can
585 /// make use of) the register scavenger.
586 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
590 /// requiresFrameIndexScavenging - returns true if the target requires post
591 /// PEI scavenging of registers for materializing frame index constants.
592 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
596 /// requiresVirtualBaseRegisters - Returns true if the target wants the
597 /// LocalStackAllocation pass to be run and virtual base registers
598 /// used for more efficient stack access.
599 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
603 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
604 /// the stack frame of the given function for the specified register. e.g. On
605 /// x86, if the frame register is required, the first fixed stack object is
606 /// reserved as its spill slot. This tells PEI not to create a new stack frame
607 /// object for the given register. It should be called only after
608 /// processFunctionBeforeCalleeSavedScan().
609 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
610 int &FrameIdx) const {
614 /// needsStackRealignment - true if storage within the function requires the
615 /// stack pointer to be aligned more than the normal calling convention calls
617 virtual bool needsStackRealignment(const MachineFunction &MF) const {
621 /// getFrameIndexInstrOffset - Get the offset from the referenced frame
622 /// index in the instruction, if the is one.
623 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
628 /// needsFrameBaseReg - Returns true if the instruction's frame index
629 /// reference would be better served by a base register other than FP
630 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
631 /// references it should create new base registers for.
632 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
636 /// materializeFrameBaseRegister - Insert defining instruction(s) for
637 /// BaseReg to be a pointer to FrameIdx before insertion point I.
638 virtual void materializeFrameBaseRegister(MachineBasicBlock::iterator I,
639 unsigned BaseReg, int FrameIdx,
640 int64_t Offset) const {
641 assert(0 && "materializeFrameBaseRegister does not exist on this target");
644 /// resolveFrameIndex - Resolve a frame index operand of an instruction
645 /// to reference the indicated base register plus offset instead.
646 virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
647 unsigned BaseReg, int64_t Offset) const {
648 assert(0 && "resolveFrameIndex does not exist on this target");
651 /// isFrameOffsetLegal - Determine whether a given offset immediate is
652 /// encodable to resolve a frame index.
653 virtual bool isFrameOffsetLegal(const MachineInstr *MI,
654 int64_t Offset) const {
655 assert(0 && "isFrameOffsetLegal does not exist on this target");
656 return false; // Must return a value in order to compile with VS 2005
659 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
660 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
661 /// targets use pseudo instructions in order to abstract away the difference
662 /// between operating with a frame pointer and operating without, through the
663 /// use of these two instructions.
665 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
666 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
668 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
669 /// code insertion to eliminate call frame setup and destroy pseudo
670 /// instructions (but only if the Target is using them). It is responsible
671 /// for eliminating these instructions, replacing them with concrete
672 /// instructions. This method need only be implemented if using call frame
673 /// setup/destroy pseudo instructions.
676 eliminateCallFramePseudoInstr(MachineFunction &MF,
677 MachineBasicBlock &MBB,
678 MachineBasicBlock::iterator MI) const {
679 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
680 "eliminateCallFramePseudoInstr must be implemented if using"
681 " call frame setup/destroy pseudo instructions!");
682 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
686 /// saveScavengerRegister - Spill the register so it can be used by the
687 /// register scavenger. Return true if the register was spilled, false
688 /// otherwise. If this function does not spill the register, the scavenger
689 /// will instead spill it to the emergency spill slot.
691 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
692 MachineBasicBlock::iterator I,
693 MachineBasicBlock::iterator &UseMI,
694 const TargetRegisterClass *RC,
695 unsigned Reg) const {
699 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
700 /// frame indices from instructions which may use them. The instruction
701 /// referenced by the iterator contains an MO_FrameIndex operand which must be
702 /// eliminated by this method. This method may modify or replace the
703 /// specified instruction, as long as it keeps the iterator pointing at the
704 /// finished product. SPAdj is the SP adjustment due to call frame setup
706 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
707 int SPAdj, RegScavenger *RS=NULL) const = 0;
709 //===--------------------------------------------------------------------===//
710 /// Debug information queries.
712 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
713 /// number. Returns -1 if there is no equivalent value. The second
714 /// parameter allows targets to use different numberings for EH info and
716 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
718 /// getFrameRegister - This method should return the register used as a base
719 /// for values allocated in the current stack frame.
720 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
722 /// getRARegister - This method should return the register where the return
723 /// address can be found.
724 virtual unsigned getRARegister() const = 0;
728 // This is useful when building IndexedMaps keyed on virtual registers
729 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
730 unsigned operator()(unsigned Reg) const {
731 return Reg - TargetRegisterInfo::FirstVirtualRegister;
735 /// getCommonSubClass - find the largest common subclass of A and B. Return NULL
736 /// if there is no common subclass.
737 const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
738 const TargetRegisterClass *B);
740 } // End llvm namespace