1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/DenseSet.h"
28 class MachineFunction;
31 template<class T> class SmallVectorImpl;
33 /// TargetRegisterDesc - This record contains all of the information known about
34 /// a particular register. The AliasSet field (if not null) contains a pointer
35 /// to a Zero terminated array of registers that this register aliases. This is
36 /// needed for architectures like X86 which have AL alias AX alias EAX.
37 /// Registers that this does not apply to simply should set this to null.
38 /// The SubRegs field is a zero terminated array of registers that are
39 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
40 /// The SuperRegs field is a zero terminated array of registers that are
41 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
44 struct TargetRegisterDesc {
45 const char *Name; // Printable name for the reg (for debugging)
46 const unsigned *AliasSet; // Register Alias Set, described above
47 const unsigned *SubRegs; // Sub-register set, described above
48 const unsigned *SuperRegs; // Super-register set, described above
51 class TargetRegisterClass {
53 typedef const unsigned* iterator;
54 typedef const unsigned* const_iterator;
56 typedef const EVT* vt_iterator;
57 typedef const TargetRegisterClass* const * sc_iterator;
61 const vt_iterator VTs;
62 const sc_iterator SubClasses;
63 const sc_iterator SuperClasses;
64 const sc_iterator SubRegClasses;
65 const sc_iterator SuperRegClasses;
66 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
68 const iterator RegsBegin, RegsEnd;
69 DenseSet<unsigned> RegSet;
71 TargetRegisterClass(unsigned id,
74 const TargetRegisterClass * const *subcs,
75 const TargetRegisterClass * const *supcs,
76 const TargetRegisterClass * const *subregcs,
77 const TargetRegisterClass * const *superregcs,
78 unsigned RS, unsigned Al, int CC,
79 iterator RB, iterator RE)
80 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
81 SubRegClasses(subregcs), SuperRegClasses(superregcs),
82 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {
83 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
86 virtual ~TargetRegisterClass() {} // Allow subclasses
88 /// getID() - Return the register class ID number.
90 unsigned getID() const { return ID; }
92 /// getName() - Return the register class name for debugging.
94 const char *getName() const { return Name; }
96 /// begin/end - Return all of the registers in this class.
98 iterator begin() const { return RegsBegin; }
99 iterator end() const { return RegsEnd; }
101 /// getNumRegs - Return the number of registers in this class.
103 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
105 /// getRegister - Return the specified register in the class.
107 unsigned getRegister(unsigned i) const {
108 assert(i < getNumRegs() && "Register number out of range!");
112 /// contains - Return true if the specified register is included in this
113 /// register class. This does not include virtual registers.
114 bool contains(unsigned Reg) const {
115 return RegSet.count(Reg);
118 /// contains - Return true if both registers are in this class.
119 bool contains(unsigned Reg1, unsigned Reg2) const {
120 return contains(Reg1) && contains(Reg2);
123 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
125 bool hasType(EVT vt) const {
126 for(int i = 0; VTs[i].getSimpleVT().SimpleTy != MVT::Other; ++i)
132 /// vt_begin / vt_end - Loop over all of the value types that can be
133 /// represented by values in this register class.
134 vt_iterator vt_begin() const {
138 vt_iterator vt_end() const {
140 while (I->getSimpleVT().SimpleTy != MVT::Other) ++I;
144 /// subregclasses_begin / subregclasses_end - Loop over all of
145 /// the subreg register classes of this register class.
146 sc_iterator subregclasses_begin() const {
147 return SubRegClasses;
150 sc_iterator subregclasses_end() const {
151 sc_iterator I = SubRegClasses;
152 while (*I != NULL) ++I;
156 /// getSubRegisterRegClass - Return the register class of subregisters with
157 /// index SubIdx, or NULL if no such class exists.
158 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
159 assert(SubIdx>0 && "Invalid subregister index");
160 return SubRegClasses[SubIdx-1];
163 /// superregclasses_begin / superregclasses_end - Loop over all of
164 /// the superreg register classes of this register class.
165 sc_iterator superregclasses_begin() const {
166 return SuperRegClasses;
169 sc_iterator superregclasses_end() const {
170 sc_iterator I = SuperRegClasses;
171 while (*I != NULL) ++I;
175 /// hasSubClass - return true if the specified TargetRegisterClass
176 /// is a proper subset of this TargetRegisterClass.
177 bool hasSubClass(const TargetRegisterClass *cs) const {
178 for (int i = 0; SubClasses[i] != NULL; ++i)
179 if (SubClasses[i] == cs)
184 /// subclasses_begin / subclasses_end - Loop over all of the classes
185 /// that are proper subsets of this register class.
186 sc_iterator subclasses_begin() const {
190 sc_iterator subclasses_end() const {
191 sc_iterator I = SubClasses;
192 while (*I != NULL) ++I;
196 /// hasSuperClass - return true if the specified TargetRegisterClass is a
197 /// proper superset of this TargetRegisterClass.
198 bool hasSuperClass(const TargetRegisterClass *cs) const {
199 for (int i = 0; SuperClasses[i] != NULL; ++i)
200 if (SuperClasses[i] == cs)
205 /// superclasses_begin / superclasses_end - Loop over all of the classes
206 /// that are proper supersets of this register class.
207 sc_iterator superclasses_begin() const {
211 sc_iterator superclasses_end() const {
212 sc_iterator I = SuperClasses;
213 while (*I != NULL) ++I;
217 /// isASubClass - return true if this TargetRegisterClass is a subset
218 /// class of at least one other TargetRegisterClass.
219 bool isASubClass() const {
220 return SuperClasses[0] != 0;
223 /// allocation_order_begin/end - These methods define a range of registers
224 /// which specify the registers in this class that are valid to register
225 /// allocate, and the preferred order to allocate them in. For example,
226 /// callee saved registers should be at the end of the list, because it is
227 /// cheaper to allocate caller saved registers.
229 /// These methods take a MachineFunction argument, which can be used to tune
230 /// the allocatable registers based on the characteristics of the function.
231 /// One simple example is that the frame pointer register can be used if
232 /// frame-pointer-elimination is performed.
234 /// By default, these methods return all registers in the class.
236 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
239 virtual iterator allocation_order_end(const MachineFunction &MF) const {
243 /// getSize - Return the size of the register in bytes, which is also the size
244 /// of a stack slot allocated to hold a spilled copy of this register.
245 unsigned getSize() const { return RegSize; }
247 /// getAlignment - Return the minimum required alignment for a register of
249 unsigned getAlignment() const { return Alignment; }
251 /// getCopyCost - Return the cost of copying a value between two registers in
252 /// this class. A negative number means the register class is very expensive
253 /// to copy e.g. status flag register classes.
254 int getCopyCost() const { return CopyCost; }
258 /// TargetRegisterInfo base class - We assume that the target defines a static
259 /// array of TargetRegisterDesc objects that represent all of the machine
260 /// registers that the target has. As such, we simply have to track a pointer
261 /// to this array so that we can turn register number into a register
264 class TargetRegisterInfo {
266 const unsigned* SubregHash;
267 const unsigned SubregHashSize;
268 const unsigned* AliasesHash;
269 const unsigned AliasesHashSize;
271 typedef const TargetRegisterClass * const * regclass_iterator;
273 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
274 const char *const *SubRegIndexNames; // Names of subreg indexes.
275 unsigned NumRegs; // Number of entries in the array
277 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
279 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
282 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
283 regclass_iterator RegClassBegin,
284 regclass_iterator RegClassEnd,
285 const char *const *subregindexnames,
286 int CallFrameSetupOpcode = -1,
287 int CallFrameDestroyOpcode = -1,
288 const unsigned* subregs = 0,
289 const unsigned subregsize = 0,
290 const unsigned* aliases = 0,
291 const unsigned aliasessize = 0);
292 virtual ~TargetRegisterInfo();
295 enum { // Define some target independent constants
296 /// NoRegister - This physical register is not a real target register. It
297 /// is useful as a sentinal.
300 /// FirstVirtualRegister - This is the first register number that is
301 /// considered to be a 'virtual' register, which is part of the SSA
302 /// namespace. This must be the same for all targets, which means that each
303 /// target is limited to this fixed number of registers.
304 FirstVirtualRegister = 1024
307 /// isPhysicalRegister - Return true if the specified register number is in
308 /// the physical register namespace.
309 static bool isPhysicalRegister(unsigned Reg) {
310 assert(Reg && "this is not a register!");
311 return Reg < FirstVirtualRegister;
314 /// isVirtualRegister - Return true if the specified register number is in
315 /// the virtual register namespace.
316 static bool isVirtualRegister(unsigned Reg) {
317 assert(Reg && "this is not a register!");
318 return Reg >= FirstVirtualRegister;
321 /// getMinimalPhysRegClass - Returns the Register Class of a physical
322 /// register of the given type, picking the most sub register class of
323 /// the right type that contains this physreg.
324 const TargetRegisterClass *
325 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
327 /// getAllocatableSet - Returns a bitset indexed by register number
328 /// indicating if a register is allocatable or not. If a register class is
329 /// specified, returns the subset for the class.
330 BitVector getAllocatableSet(const MachineFunction &MF,
331 const TargetRegisterClass *RC = NULL) const;
333 const TargetRegisterDesc &operator[](unsigned RegNo) const {
334 assert(RegNo < NumRegs &&
335 "Attempting to access record for invalid register number!");
339 /// Provide a get method, equivalent to [], but more useful if we have a
340 /// pointer to this object.
342 const TargetRegisterDesc &get(unsigned RegNo) const {
343 return operator[](RegNo);
346 /// getAliasSet - Return the set of registers aliased by the specified
347 /// register, or a null list of there are none. The list returned is zero
350 const unsigned *getAliasSet(unsigned RegNo) const {
351 return get(RegNo).AliasSet;
354 /// getSubRegisters - Return the list of registers that are sub-registers of
355 /// the specified register, or a null list of there are none. The list
356 /// returned is zero terminated and sorted according to super-sub register
357 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
359 const unsigned *getSubRegisters(unsigned RegNo) const {
360 return get(RegNo).SubRegs;
363 /// getSuperRegisters - Return the list of registers that are super-registers
364 /// of the specified register, or a null list of there are none. The list
365 /// returned is zero terminated and sorted according to super-sub register
366 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
368 const unsigned *getSuperRegisters(unsigned RegNo) const {
369 return get(RegNo).SuperRegs;
372 /// getName - Return the human-readable symbolic target-specific name for the
373 /// specified physical register.
374 const char *getName(unsigned RegNo) const {
375 return get(RegNo).Name;
378 /// getNumRegs - Return the number of registers this target has (useful for
379 /// sizing arrays holding per register information)
380 unsigned getNumRegs() const {
384 /// getSubRegIndexName - Return the human-readable symbolic target-specific
385 /// name for the specified SubRegIndex.
386 const char *getSubRegIndexName(unsigned SubIdx) const {
387 assert(SubIdx && "This is not a subregister index");
388 return SubRegIndexNames[SubIdx-1];
391 /// regsOverlap - Returns true if the two registers are equal or alias each
392 /// other. The registers may be virtual register.
393 bool regsOverlap(unsigned regA, unsigned regB) const {
397 if (isVirtualRegister(regA) || isVirtualRegister(regB))
400 // regA and regB are distinct physical registers. Do they alias?
401 size_t index = (regA + regB * 37) & (AliasesHashSize-1);
402 unsigned ProbeAmt = 0;
403 while (AliasesHash[index*2] != 0 &&
404 AliasesHash[index*2+1] != 0) {
405 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB)
408 index = (index + ProbeAmt) & (AliasesHashSize-1);
415 /// isSubRegister - Returns true if regB is a sub-register of regA.
417 bool isSubRegister(unsigned regA, unsigned regB) const {
418 // SubregHash is a simple quadratically probed hash table.
419 size_t index = (regA + regB * 37) & (SubregHashSize-1);
420 unsigned ProbeAmt = 2;
421 while (SubregHash[index*2] != 0 &&
422 SubregHash[index*2+1] != 0) {
423 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
426 index = (index + ProbeAmt) & (SubregHashSize-1);
433 /// isSuperRegister - Returns true if regB is a super-register of regA.
435 bool isSuperRegister(unsigned regA, unsigned regB) const {
436 return isSubRegister(regB, regA);
439 /// getCalleeSavedRegs - Return a null-terminated list of all of the
440 /// callee saved registers on this target. The register should be in the
441 /// order of desired callee-save stack frame offset. The first register is
442 /// closed to the incoming stack pointer if stack grows down, and vice versa.
443 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
447 /// getReservedRegs - Returns a bitset indexed by physical register number
448 /// indicating if a register is a special register that has particular uses
449 /// and should be considered unavailable at all times, e.g. SP, RA. This is
450 /// used by register scavenger to determine what registers are free.
451 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
453 /// getSubReg - Returns the physical register number of sub-register "Index"
454 /// for physical register RegNo. Return zero if the sub-register does not
456 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
458 /// getSubRegIndex - For a given register pair, return the sub-register index
459 /// if the second register is a sub-register of the first. Return zero
461 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
463 /// getMatchingSuperReg - Return a super-register of the specified register
464 /// Reg so its sub-register of index SubIdx is Reg.
465 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
466 const TargetRegisterClass *RC) const {
467 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
468 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
473 /// canCombineSubRegIndices - Given a register class and a list of
474 /// subregister indices, return true if it's possible to combine the
475 /// subregister indices into one that corresponds to a larger
476 /// subregister. Return the new subregister index by reference. Note the
477 /// new index may be zero if the given subregisters can be combined to
478 /// form the whole register.
479 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
480 SmallVectorImpl<unsigned> &SubIndices,
481 unsigned &NewSubIdx) const {
485 /// getMatchingSuperRegClass - Return a subclass of the specified register
486 /// class A so that each register in it has a sub-register of the
487 /// specified sub-register index which is in the specified register class B.
488 virtual const TargetRegisterClass *
489 getMatchingSuperRegClass(const TargetRegisterClass *A,
490 const TargetRegisterClass *B, unsigned Idx) const {
494 /// composeSubRegIndices - Return the subregister index you get from composing
495 /// two subregister indices.
497 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
498 /// returns c. Note that composeSubRegIndices does not tell you about illegal
499 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
500 /// b, composeSubRegIndices doesn't tell you.
502 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
503 /// ssub_0:S0 - ssub_3:S3 subregs.
504 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
506 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
507 // This default implementation is correct for most targets.
511 //===--------------------------------------------------------------------===//
512 // Register Class Information
515 /// Register class iterators
517 regclass_iterator regclass_begin() const { return RegClassBegin; }
518 regclass_iterator regclass_end() const { return RegClassEnd; }
520 unsigned getNumRegClasses() const {
521 return (unsigned)(regclass_end()-regclass_begin());
524 /// getRegClass - Returns the register class associated with the enumeration
525 /// value. See class TargetOperandInfo.
526 const TargetRegisterClass *getRegClass(unsigned i) const {
527 assert(i < getNumRegClasses() && "Register Class ID out of range");
528 return RegClassBegin[i];
531 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
532 /// values. If a target supports multiple different pointer register classes,
533 /// kind specifies which one is indicated.
534 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
535 assert(0 && "Target didn't implement getPointerRegClass!");
536 return 0; // Must return a value in order to compile with VS 2005
539 /// getCrossCopyRegClass - Returns a legal register class to copy a register
540 /// in the specified class to or from. Returns NULL if it is possible to copy
541 /// between a two registers of the specified class.
542 virtual const TargetRegisterClass *
543 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
547 /// getAllocationOrder - Returns the register allocation order for a specified
548 /// register class in the form of a pair of TargetRegisterClass iterators.
549 virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
550 getAllocationOrder(const TargetRegisterClass *RC,
551 unsigned HintType, unsigned HintReg,
552 const MachineFunction &MF) const {
553 return std::make_pair(RC->allocation_order_begin(MF),
554 RC->allocation_order_end(MF));
557 /// ResolveRegAllocHint - Resolves the specified register allocation hint
558 /// to a physical register. Returns the physical register if it is successful.
559 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
560 const MachineFunction &MF) const {
561 if (Type == 0 && Reg && isPhysicalRegister(Reg))
566 /// UpdateRegAllocHint - A callback to allow target a chance to update
567 /// register allocation hints when a register is "changed" (e.g. coalesced)
568 /// to another register. e.g. On ARM, some virtual registers should target
569 /// register pairs, if one of pair is coalesced to another register, the
570 /// allocation hint of the other half of the pair should be changed to point
571 /// to the new register.
572 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
573 MachineFunction &MF) const {
577 /// targetHandlesStackFrameRounding - Returns true if the target is
578 /// responsible for rounding up the stack frame (probably at emitPrologue
580 virtual bool targetHandlesStackFrameRounding() const {
584 /// requiresRegisterScavenging - returns true if the target requires (and can
585 /// make use of) the register scavenger.
586 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
590 /// requiresFrameIndexScavenging - returns true if the target requires post
591 /// PEI scavenging of registers for materializing frame index constants.
592 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
596 /// hasFP - Return true if the specified function should have a dedicated
597 /// frame pointer register. For most targets this is true only if the function
598 /// has variable sized allocas or if frame pointer elimination is disabled.
599 virtual bool hasFP(const MachineFunction &MF) const = 0;
601 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
602 /// not required, we reserve argument space for call sites in the function
603 /// immediately on entry to the current function. This eliminates the need for
604 /// add/sub sp brackets around call sites. Returns true if the call frame is
605 /// included as part of the stack frame.
606 virtual bool hasReservedCallFrame(const MachineFunction &MF) const {
610 /// canSimplifyCallFramePseudos - When possible, it's best to simplify the
611 /// call frame pseudo ops before doing frame index elimination. This is
612 /// possible only when frame index references between the pseudos won't
613 /// need adjusting for the call frame adjustments. Normally, that's true
614 /// if the function has a reserved call frame or a frame pointer. Some
615 /// targets (Thumb2, for example) may have more complicated criteria,
616 /// however, and can override this behavior.
617 virtual bool canSimplifyCallFramePseudos(const MachineFunction &MF) const {
618 return hasReservedCallFrame(MF) || hasFP(MF);
621 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
622 /// the stack frame of the given function for the specified register. e.g. On
623 /// x86, if the frame register is required, the first fixed stack object is
624 /// reserved as its spill slot. This tells PEI not to create a new stack frame
625 /// object for the given register. It should be called only after
626 /// processFunctionBeforeCalleeSavedScan().
627 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
628 int &FrameIdx) const {
632 /// needsStackRealignment - true if storage within the function requires the
633 /// stack pointer to be aligned more than the normal calling convention calls
635 virtual bool needsStackRealignment(const MachineFunction &MF) const {
639 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
640 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
641 /// targets use pseudo instructions in order to abstract away the difference
642 /// between operating with a frame pointer and operating without, through the
643 /// use of these two instructions.
645 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
646 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
648 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
649 /// code insertion to eliminate call frame setup and destroy pseudo
650 /// instructions (but only if the Target is using them). It is responsible
651 /// for eliminating these instructions, replacing them with concrete
652 /// instructions. This method need only be implemented if using call frame
653 /// setup/destroy pseudo instructions.
656 eliminateCallFramePseudoInstr(MachineFunction &MF,
657 MachineBasicBlock &MBB,
658 MachineBasicBlock::iterator MI) const {
659 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
660 "eliminateCallFramePseudoInstr must be implemented if using"
661 " call frame setup/destroy pseudo instructions!");
662 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
665 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
666 /// before PrologEpilogInserter scans the physical registers used to determine
667 /// what callee saved registers should be spilled. This method is optional.
668 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
669 RegScavenger *RS = NULL) const {
673 /// processFunctionBeforeFrameFinalized - This method is called immediately
674 /// before the specified functions frame layout (MF.getFrameInfo()) is
675 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
676 /// replaced with direct constants. This method is optional.
678 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
681 /// saveScavengerRegister - Spill the register so it can be used by the
682 /// register scavenger. Return true if the register was spilled, false
683 /// otherwise. If this function does not spill the register, the scavenger
684 /// will instead spill it to the emergency spill slot.
686 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
687 MachineBasicBlock::iterator I,
688 MachineBasicBlock::iterator &UseMI,
689 const TargetRegisterClass *RC,
690 unsigned Reg) const {
694 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
695 /// frame indices from instructions which may use them. The instruction
696 /// referenced by the iterator contains an MO_FrameIndex operand which must be
697 /// eliminated by this method. This method may modify or replace the
698 /// specified instruction, as long as it keeps the iterator pointing at the
699 /// finished product. SPAdj is the SP adjustment due to call frame setup
702 /// When -enable-frame-index-scavenging is enabled, the virtual register
703 /// allocated for this frame index is returned and its value is stored in
705 typedef std::pair<unsigned, int> FrameIndexValue;
706 virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI,
707 int SPAdj, FrameIndexValue *Value = NULL,
708 RegScavenger *RS=NULL) const = 0;
710 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
712 virtual void emitPrologue(MachineFunction &MF) const = 0;
713 virtual void emitEpilogue(MachineFunction &MF,
714 MachineBasicBlock &MBB) const = 0;
716 //===--------------------------------------------------------------------===//
717 /// Debug information queries.
719 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
720 /// number. Returns -1 if there is no equivalent value. The second
721 /// parameter allows targets to use different numberings for EH info and
723 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
725 /// getFrameRegister - This method should return the register used as a base
726 /// for values allocated in the current stack frame.
727 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
729 /// getFrameIndexOffset - Returns the displacement from the frame register to
730 /// the stack frame of the specified index.
731 virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
733 /// getFrameIndexReference - This method should return the base register
734 /// and offset used to reference a frame index location. The offset is
735 /// returned directly, and the base register is returned via FrameReg.
736 virtual int getFrameIndexReference(const MachineFunction &MF, int FI,
737 unsigned &FrameReg) const {
738 // By default, assume all frame indices are referenced via whatever
739 // getFrameRegister() says. The target can override this if it's doing
740 // something different.
741 FrameReg = getFrameRegister(MF);
742 return getFrameIndexOffset(MF, FI);
745 /// getRARegister - This method should return the register where the return
746 /// address can be found.
747 virtual unsigned getRARegister() const = 0;
749 /// getInitialFrameState - Returns a list of machine moves that are assumed
750 /// on entry to all functions. Note that LabelID is ignored (assumed to be
751 /// the beginning of the function.)
752 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
756 // This is useful when building IndexedMaps keyed on virtual registers
757 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
758 unsigned operator()(unsigned Reg) const {
759 return Reg - TargetRegisterInfo::FirstVirtualRegister;
763 /// getCommonSubClass - find the largest common subclass of A and B. Return NULL
764 /// if there is no common subclass.
765 const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
766 const TargetRegisterClass *B);
768 } // End llvm namespace