1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/ADT/ArrayRef.h"
29 class MachineFunction;
31 template<class T> class SmallVectorImpl;
34 class TargetRegisterClass {
36 typedef const unsigned* iterator;
37 typedef const unsigned* const_iterator;
38 typedef const EVT* vt_iterator;
39 typedef const TargetRegisterClass* const * sc_iterator;
41 virtual void anchor();
42 const MCRegisterClass *MC;
43 const vt_iterator VTs;
44 const unsigned *SubClassMask;
45 const sc_iterator SuperClasses;
46 const sc_iterator SuperRegClasses;
48 TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts,
49 const unsigned *subcm,
50 const TargetRegisterClass * const *supcs,
51 const TargetRegisterClass * const *superregcs)
52 : MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs),
53 SuperRegClasses(superregcs) {}
55 virtual ~TargetRegisterClass() {} // Allow subclasses
57 /// getID() - Return the register class ID number.
59 unsigned getID() const { return MC->getID(); }
61 /// getName() - Return the register class name for debugging.
63 const char *getName() const { return MC->getName(); }
65 /// begin/end - Return all of the registers in this class.
67 iterator begin() const { return MC->begin(); }
68 iterator end() const { return MC->end(); }
70 /// getNumRegs - Return the number of registers in this class.
72 unsigned getNumRegs() const { return MC->getNumRegs(); }
74 /// getRegister - Return the specified register in the class.
76 unsigned getRegister(unsigned i) const {
77 return MC->getRegister(i);
80 /// contains - Return true if the specified register is included in this
81 /// register class. This does not include virtual registers.
82 bool contains(unsigned Reg) const {
83 return MC->contains(Reg);
86 /// contains - Return true if both registers are in this class.
87 bool contains(unsigned Reg1, unsigned Reg2) const {
88 return MC->contains(Reg1, Reg2);
91 /// getSize - Return the size of the register in bytes, which is also the size
92 /// of a stack slot allocated to hold a spilled copy of this register.
93 unsigned getSize() const { return MC->getSize(); }
95 /// getAlignment - Return the minimum required alignment for a register of
97 unsigned getAlignment() const { return MC->getAlignment(); }
99 /// getCopyCost - Return the cost of copying a value between two registers in
100 /// this class. A negative number means the register class is very expensive
101 /// to copy e.g. status flag register classes.
102 int getCopyCost() const { return MC->getCopyCost(); }
104 /// isAllocatable - Return true if this register class may be used to create
105 /// virtual registers.
106 bool isAllocatable() const { return MC->isAllocatable(); }
108 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
110 bool hasType(EVT vt) const {
111 for(int i = 0; VTs[i] != MVT::Other; ++i)
117 /// vt_begin / vt_end - Loop over all of the value types that can be
118 /// represented by values in this register class.
119 vt_iterator vt_begin() const {
123 vt_iterator vt_end() const {
125 while (*I != MVT::Other) ++I;
129 /// superregclasses_begin / superregclasses_end - Loop over all of
130 /// the superreg register classes of this register class.
131 sc_iterator superregclasses_begin() const {
132 return SuperRegClasses;
135 sc_iterator superregclasses_end() const {
136 sc_iterator I = SuperRegClasses;
137 while (*I != NULL) ++I;
141 /// hasSubClass - return true if the specified TargetRegisterClass
142 /// is a proper sub-class of this TargetRegisterClass.
143 bool hasSubClass(const TargetRegisterClass *RC) const {
144 return RC != this && hasSubClassEq(RC);
147 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
149 bool hasSubClassEq(const TargetRegisterClass *RC) const {
150 unsigned ID = RC->getID();
151 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
154 /// hasSuperClass - return true if the specified TargetRegisterClass is a
155 /// proper super-class of this TargetRegisterClass.
156 bool hasSuperClass(const TargetRegisterClass *RC) const {
157 return RC->hasSubClass(this);
160 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
162 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
163 return RC->hasSubClassEq(this);
166 /// getSubClassMask - Returns a bit vector of subclasses, including this one.
167 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
169 const unsigned *getSubClassMask() const {
173 /// getSuperClasses - Returns a NULL terminated list of super-classes. The
174 /// classes are ordered by ID which is also a topological ordering from large
175 /// to small classes. The list does NOT include the current class.
176 sc_iterator getSuperClasses() const {
180 /// isASubClass - return true if this TargetRegisterClass is a subset
181 /// class of at least one other TargetRegisterClass.
182 bool isASubClass() const {
183 return SuperClasses[0] != 0;
186 /// getRawAllocationOrder - Returns the preferred order for allocating
187 /// registers from this register class in MF. The raw order comes directly
188 /// from the .td file and may include reserved registers that are not
189 /// allocatable. Register allocators should also make sure to allocate
190 /// callee-saved registers only after all the volatiles are used. The
191 /// RegisterClassInfo class provides filtered allocation orders with
192 /// callee-saved registers moved to the end.
194 /// The MachineFunction argument can be used to tune the allocatable
195 /// registers based on the characteristics of the function, subtarget, or
198 /// By default, this method returns all registers in the class.
201 ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const {
202 return makeArrayRef(begin(), getNumRegs());
206 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
207 /// registers. These are used by codegen, not by MC.
208 struct TargetRegisterInfoDesc {
209 unsigned CostPerUse; // Extra cost of instructions using register.
210 bool inAllocatableClass; // Register belongs to an allocatable regclass.
213 /// TargetRegisterInfo base class - We assume that the target defines a static
214 /// array of TargetRegisterDesc objects that represent all of the machine
215 /// registers that the target has. As such, we simply have to track a pointer
216 /// to this array so that we can turn register number into a register
219 class TargetRegisterInfo : public MCRegisterInfo {
221 typedef const TargetRegisterClass * const * regclass_iterator;
223 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
224 const char *const *SubRegIndexNames; // Names of subreg indexes.
225 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
228 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
229 regclass_iterator RegClassBegin,
230 regclass_iterator RegClassEnd,
231 const char *const *subregindexnames);
232 virtual ~TargetRegisterInfo();
235 // Register numbers can represent physical registers, virtual registers, and
236 // sometimes stack slots. The unsigned values are divided into these ranges:
238 // 0 Not a register, can be used as a sentinel.
239 // [1;2^30) Physical registers assigned by TableGen.
240 // [2^30;2^31) Stack slots. (Rarely used.)
241 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
243 // Further sentinels can be allocated from the small negative integers.
244 // DenseMapInfo<unsigned> uses -1u and -2u.
246 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
247 /// frame index in a variable that normally holds a register. isStackSlot()
248 /// returns true if Reg is in the range used for stack slots.
250 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
251 /// slots, so if a variable may contains a stack slot, always check
252 /// isStackSlot() first.
254 static bool isStackSlot(unsigned Reg) {
255 return int(Reg) >= (1 << 30);
258 /// stackSlot2Index - Compute the frame index from a register value
259 /// representing a stack slot.
260 static int stackSlot2Index(unsigned Reg) {
261 assert(isStackSlot(Reg) && "Not a stack slot");
262 return int(Reg - (1u << 30));
265 /// index2StackSlot - Convert a non-negative frame index to a stack slot
267 static unsigned index2StackSlot(int FI) {
268 assert(FI >= 0 && "Cannot hold a negative frame index.");
269 return FI + (1u << 30);
272 /// isPhysicalRegister - Return true if the specified register number is in
273 /// the physical register namespace.
274 static bool isPhysicalRegister(unsigned Reg) {
275 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
279 /// isVirtualRegister - Return true if the specified register number is in
280 /// the virtual register namespace.
281 static bool isVirtualRegister(unsigned Reg) {
282 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
286 /// virtReg2Index - Convert a virtual register number to a 0-based index.
287 /// The first virtual register in a function will get the index 0.
288 static unsigned virtReg2Index(unsigned Reg) {
289 assert(isVirtualRegister(Reg) && "Not a virtual register");
290 return Reg & ~(1u << 31);
293 /// index2VirtReg - Convert a 0-based index to a virtual register number.
294 /// This is the inverse operation of VirtReg2IndexFunctor below.
295 static unsigned index2VirtReg(unsigned Index) {
296 return Index | (1u << 31);
299 /// getMinimalPhysRegClass - Returns the Register Class of a physical
300 /// register of the given type, picking the most sub register class of
301 /// the right type that contains this physreg.
302 const TargetRegisterClass *
303 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
305 /// getAllocatableSet - Returns a bitset indexed by register number
306 /// indicating if a register is allocatable or not. If a register class is
307 /// specified, returns the subset for the class.
308 BitVector getAllocatableSet(const MachineFunction &MF,
309 const TargetRegisterClass *RC = NULL) const;
311 /// getCostPerUse - Return the additional cost of using this register instead
312 /// of other registers in its class.
313 unsigned getCostPerUse(unsigned RegNo) const {
314 return InfoDesc[RegNo].CostPerUse;
317 /// isInAllocatableClass - Return true if the register is in the allocation
318 /// of any register class.
319 bool isInAllocatableClass(unsigned RegNo) const {
320 return InfoDesc[RegNo].inAllocatableClass;
323 /// getSubRegIndexName - Return the human-readable symbolic target-specific
324 /// name for the specified SubRegIndex.
325 const char *getSubRegIndexName(unsigned SubIdx) const {
326 assert(SubIdx && "This is not a subregister index");
327 return SubRegIndexNames[SubIdx-1];
330 /// regsOverlap - Returns true if the two registers are equal or alias each
331 /// other. The registers may be virtual register.
332 bool regsOverlap(unsigned regA, unsigned regB) const {
333 if (regA == regB) return true;
334 if (isVirtualRegister(regA) || isVirtualRegister(regB))
336 for (const unsigned *regList = getOverlaps(regA)+1; *regList; ++regList) {
337 if (*regList == regB) return true;
342 /// isSubRegister - Returns true if regB is a sub-register of regA.
344 bool isSubRegister(unsigned regA, unsigned regB) const {
345 return isSuperRegister(regB, regA);
348 /// isSuperRegister - Returns true if regB is a super-register of regA.
350 bool isSuperRegister(unsigned regA, unsigned regB) const {
351 for (const unsigned *regList = getSuperRegisters(regA); *regList;++regList){
352 if (*regList == regB) return true;
357 /// getCalleeSavedRegs - Return a null-terminated list of all of the
358 /// callee saved registers on this target. The register should be in the
359 /// order of desired callee-save stack frame offset. The first register is
360 /// closed to the incoming stack pointer if stack grows down, and vice versa.
361 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
365 /// getReservedRegs - Returns a bitset indexed by physical register number
366 /// indicating if a register is a special register that has particular uses
367 /// and should be considered unavailable at all times, e.g. SP, RA. This is
368 /// used by register scavenger to determine what registers are free.
369 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
371 /// getSubReg - Returns the physical register number of sub-register "Index"
372 /// for physical register RegNo. Return zero if the sub-register does not
374 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
376 /// getSubRegIndex - For a given register pair, return the sub-register index
377 /// if the second register is a sub-register of the first. Return zero
379 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
381 /// getMatchingSuperReg - Return a super-register of the specified register
382 /// Reg so its sub-register of index SubIdx is Reg.
383 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
384 const TargetRegisterClass *RC) const {
385 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
386 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
391 /// canCombineSubRegIndices - Given a register class and a list of
392 /// subregister indices, return true if it's possible to combine the
393 /// subregister indices into one that corresponds to a larger
394 /// subregister. Return the new subregister index by reference. Note the
395 /// new index may be zero if the given subregisters can be combined to
396 /// form the whole register.
397 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
398 SmallVectorImpl<unsigned> &SubIndices,
399 unsigned &NewSubIdx) const {
403 /// getMatchingSuperRegClass - Return a subclass of the specified register
404 /// class A so that each register in it has a sub-register of the
405 /// specified sub-register index which is in the specified register class B.
407 /// TableGen will synthesize missing A sub-classes.
408 virtual const TargetRegisterClass *
409 getMatchingSuperRegClass(const TargetRegisterClass *A,
410 const TargetRegisterClass *B, unsigned Idx) const =0;
412 /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that
413 /// supports the sub-register index Idx.
414 /// If no such sub-class exists, return NULL.
415 /// If all registers in RC already have an Idx sub-register, return RC.
417 /// TableGen generates a version of this function that is good enough in most
418 /// cases. Targets can override if they have constraints that TableGen
419 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
420 /// supported by the full GR32 register class in 64-bit mode, but only by the
421 /// GR32_ABCD regiister class in 32-bit mode.
423 /// TableGen will synthesize missing RC sub-classes.
424 virtual const TargetRegisterClass *
425 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0;
427 /// composeSubRegIndices - Return the subregister index you get from composing
428 /// two subregister indices.
430 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
431 /// returns c. Note that composeSubRegIndices does not tell you about illegal
432 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
433 /// b, composeSubRegIndices doesn't tell you.
435 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
436 /// ssub_0:S0 - ssub_3:S3 subregs.
437 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
439 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
440 // This default implementation is correct for most targets.
444 //===--------------------------------------------------------------------===//
445 // Register Class Information
448 /// Register class iterators
450 regclass_iterator regclass_begin() const { return RegClassBegin; }
451 regclass_iterator regclass_end() const { return RegClassEnd; }
453 unsigned getNumRegClasses() const {
454 return (unsigned)(regclass_end()-regclass_begin());
457 /// getRegClass - Returns the register class associated with the enumeration
458 /// value. See class MCOperandInfo.
459 const TargetRegisterClass *getRegClass(unsigned i) const {
460 assert(i < getNumRegClasses() && "Register Class ID out of range");
461 return RegClassBegin[i];
464 /// getCommonSubClass - find the largest common subclass of A and B. Return
465 /// NULL if there is no common subclass.
466 const TargetRegisterClass *
467 getCommonSubClass(const TargetRegisterClass *A,
468 const TargetRegisterClass *B) const;
470 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
471 /// values. If a target supports multiple different pointer register classes,
472 /// kind specifies which one is indicated.
473 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
474 assert(0 && "Target didn't implement getPointerRegClass!");
475 return 0; // Must return a value in order to compile with VS 2005
478 /// getCrossCopyRegClass - Returns a legal register class to copy a register
479 /// in the specified class to or from. If it is possible to copy the register
480 /// directly without using a cross register class copy, return the specified
481 /// RC. Returns NULL if it is not possible to copy between a two registers of
482 /// the specified class.
483 virtual const TargetRegisterClass *
484 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
488 /// getLargestLegalSuperClass - Returns the largest super class of RC that is
489 /// legal to use in the current sub-target and has the same spill size.
490 /// The returned register class can be used to create virtual registers which
491 /// means that all its registers can be copied and spilled.
492 virtual const TargetRegisterClass*
493 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
494 /// The default implementation is very conservative and doesn't allow the
495 /// register allocator to inflate register classes.
499 /// getRegPressureLimit - Return the register pressure "high water mark" for
500 /// the specific register class. The scheduler is in high register pressure
501 /// mode (for the specific register class) if it goes over the limit.
502 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
503 MachineFunction &MF) const {
507 /// getRawAllocationOrder - Returns the register allocation order for a
508 /// specified register class with a target-dependent hint. The returned list
509 /// may contain reserved registers that cannot be allocated.
511 /// Register allocators need only call this function to resolve
512 /// target-dependent hints, but it should work without hinting as well.
513 virtual ArrayRef<unsigned>
514 getRawAllocationOrder(const TargetRegisterClass *RC,
515 unsigned HintType, unsigned HintReg,
516 const MachineFunction &MF) const {
517 return RC->getRawAllocationOrder(MF);
520 /// ResolveRegAllocHint - Resolves the specified register allocation hint
521 /// to a physical register. Returns the physical register if it is successful.
522 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
523 const MachineFunction &MF) const {
524 if (Type == 0 && Reg && isPhysicalRegister(Reg))
529 /// avoidWriteAfterWrite - Return true if the register allocator should avoid
530 /// writing a register from RC in two consecutive instructions.
531 /// This can avoid pipeline stalls on certain architectures.
532 /// It does cause increased register pressure, though.
533 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
537 /// UpdateRegAllocHint - A callback to allow target a chance to update
538 /// register allocation hints when a register is "changed" (e.g. coalesced)
539 /// to another register. e.g. On ARM, some virtual registers should target
540 /// register pairs, if one of pair is coalesced to another register, the
541 /// allocation hint of the other half of the pair should be changed to point
542 /// to the new register.
543 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
544 MachineFunction &MF) const {
548 /// requiresRegisterScavenging - returns true if the target requires (and can
549 /// make use of) the register scavenger.
550 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
554 /// useFPForScavengingIndex - returns true if the target wants to use
555 /// frame pointer based accesses to spill to the scavenger emergency spill
557 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
561 /// requiresFrameIndexScavenging - returns true if the target requires post
562 /// PEI scavenging of registers for materializing frame index constants.
563 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
567 /// requiresVirtualBaseRegisters - Returns true if the target wants the
568 /// LocalStackAllocation pass to be run and virtual base registers
569 /// used for more efficient stack access.
570 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
574 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
575 /// the stack frame of the given function for the specified register. e.g. On
576 /// x86, if the frame register is required, the first fixed stack object is
577 /// reserved as its spill slot. This tells PEI not to create a new stack frame
578 /// object for the given register. It should be called only after
579 /// processFunctionBeforeCalleeSavedScan().
580 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
581 int &FrameIdx) const {
585 /// needsStackRealignment - true if storage within the function requires the
586 /// stack pointer to be aligned more than the normal calling convention calls
588 virtual bool needsStackRealignment(const MachineFunction &MF) const {
592 /// getFrameIndexInstrOffset - Get the offset from the referenced frame
593 /// index in the instruction, if there is one.
594 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
599 /// needsFrameBaseReg - Returns true if the instruction's frame index
600 /// reference would be better served by a base register other than FP
601 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
602 /// references it should create new base registers for.
603 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
607 /// materializeFrameBaseRegister - Insert defining instruction(s) for
608 /// BaseReg to be a pointer to FrameIdx before insertion point I.
609 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
610 unsigned BaseReg, int FrameIdx,
611 int64_t Offset) const {
612 assert(0 && "materializeFrameBaseRegister does not exist on this target");
615 /// resolveFrameIndex - Resolve a frame index operand of an instruction
616 /// to reference the indicated base register plus offset instead.
617 virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
618 unsigned BaseReg, int64_t Offset) const {
619 assert(0 && "resolveFrameIndex does not exist on this target");
622 /// isFrameOffsetLegal - Determine whether a given offset immediate is
623 /// encodable to resolve a frame index.
624 virtual bool isFrameOffsetLegal(const MachineInstr *MI,
625 int64_t Offset) const {
626 assert(0 && "isFrameOffsetLegal does not exist on this target");
627 return false; // Must return a value in order to compile with VS 2005
630 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
631 /// code insertion to eliminate call frame setup and destroy pseudo
632 /// instructions (but only if the Target is using them). It is responsible
633 /// for eliminating these instructions, replacing them with concrete
634 /// instructions. This method need only be implemented if using call frame
635 /// setup/destroy pseudo instructions.
638 eliminateCallFramePseudoInstr(MachineFunction &MF,
639 MachineBasicBlock &MBB,
640 MachineBasicBlock::iterator MI) const {
641 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
645 /// saveScavengerRegister - Spill the register so it can be used by the
646 /// register scavenger. Return true if the register was spilled, false
647 /// otherwise. If this function does not spill the register, the scavenger
648 /// will instead spill it to the emergency spill slot.
650 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
651 MachineBasicBlock::iterator I,
652 MachineBasicBlock::iterator &UseMI,
653 const TargetRegisterClass *RC,
654 unsigned Reg) const {
658 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
659 /// frame indices from instructions which may use them. The instruction
660 /// referenced by the iterator contains an MO_FrameIndex operand which must be
661 /// eliminated by this method. This method may modify or replace the
662 /// specified instruction, as long as it keeps the iterator pointing at the
663 /// finished product. SPAdj is the SP adjustment due to call frame setup
665 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
666 int SPAdj, RegScavenger *RS=NULL) const = 0;
668 //===--------------------------------------------------------------------===//
669 /// Debug information queries.
671 /// getFrameRegister - This method should return the register used as a base
672 /// for values allocated in the current stack frame.
673 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
675 /// getCompactUnwindRegNum - This function maps the register to the number for
676 /// compact unwind encoding. Return -1 if the register isn't valid.
677 virtual int getCompactUnwindRegNum(unsigned, bool) const {
683 // This is useful when building IndexedMaps keyed on virtual registers
684 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
685 unsigned operator()(unsigned Reg) const {
686 return TargetRegisterInfo::virtReg2Index(Reg);
690 /// PrintReg - Helper class for printing registers on a raw_ostream.
691 /// Prints virtual and physical registers with or without a TRI instance.
694 /// %noreg - NoRegister
695 /// %vreg5 - a virtual register.
696 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
697 /// %EAX - a physical register
698 /// %physreg17 - a physical register when no TRI instance given.
700 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
703 const TargetRegisterInfo *TRI;
707 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
708 : TRI(tri), Reg(reg), SubIdx(subidx) {}
709 void print(raw_ostream&) const;
712 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
717 } // End llvm namespace