1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/DenseSet.h"
28 class MachineFunction;
32 /// TargetRegisterDesc - This record contains all of the information known about
33 /// a particular register. The AliasSet field (if not null) contains a pointer
34 /// to a Zero terminated array of registers that this register aliases. This is
35 /// needed for architectures like X86 which have AL alias AX alias EAX.
36 /// Registers that this does not apply to simply should set this to null.
37 /// The SubRegs field is a zero terminated array of registers that are
38 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
39 /// The SuperRegs field is a zero terminated array of registers that are
40 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
43 struct TargetRegisterDesc {
44 const char *AsmName; // Assembly language name for the register
45 const char *Name; // Printable name for the reg (for debugging)
46 const unsigned *AliasSet; // Register Alias Set, described above
47 const unsigned *SubRegs; // Sub-register set, described above
48 const unsigned *SuperRegs; // Super-register set, described above
51 class TargetRegisterClass {
53 typedef const unsigned* iterator;
54 typedef const unsigned* const_iterator;
56 typedef const MVT* vt_iterator;
57 typedef const TargetRegisterClass* const * sc_iterator;
61 const vt_iterator VTs;
62 const sc_iterator SubClasses;
63 const sc_iterator SuperClasses;
64 const sc_iterator SubRegClasses;
65 const sc_iterator SuperRegClasses;
66 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
68 const iterator RegsBegin, RegsEnd;
69 DenseSet<unsigned> RegSet;
71 TargetRegisterClass(unsigned id,
74 const TargetRegisterClass * const *subcs,
75 const TargetRegisterClass * const *supcs,
76 const TargetRegisterClass * const *subregcs,
77 const TargetRegisterClass * const *superregcs,
78 unsigned RS, unsigned Al, int CC,
79 iterator RB, iterator RE)
80 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
81 SubRegClasses(subregcs), SuperRegClasses(superregcs),
82 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {
83 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
86 virtual ~TargetRegisterClass() {} // Allow subclasses
88 /// getID() - Return the register class ID number.
90 unsigned getID() const { return ID; }
92 /// getName() - Return the register class name for debugging.
94 const char *getName() const { return Name; }
96 /// begin/end - Return all of the registers in this class.
98 iterator begin() const { return RegsBegin; }
99 iterator end() const { return RegsEnd; }
101 /// getNumRegs - Return the number of registers in this class.
103 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
105 /// getRegister - Return the specified register in the class.
107 unsigned getRegister(unsigned i) const {
108 assert(i < getNumRegs() && "Register number out of range!");
112 /// contains - Return true if the specified register is included in this
114 bool contains(unsigned Reg) const {
115 return RegSet.count(Reg);
118 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
120 bool hasType(MVT vt) const {
121 for(int i = 0; VTs[i] != MVT::Other; ++i)
127 /// vt_begin / vt_end - Loop over all of the value types that can be
128 /// represented by values in this register class.
129 vt_iterator vt_begin() const {
133 vt_iterator vt_end() const {
135 while (*I != MVT::Other) ++I;
139 /// subregclasses_begin / subregclasses_end - Loop over all of
140 /// the subreg register classes of this register class.
141 sc_iterator subregclasses_begin() const {
142 return SubRegClasses;
145 sc_iterator subregclasses_end() const {
146 sc_iterator I = SubRegClasses;
147 while (*I != NULL) ++I;
151 /// superregclasses_begin / superregclasses_end - Loop over all of
152 /// the superreg register classes of this register class.
153 sc_iterator superregclasses_begin() const {
154 return SuperRegClasses;
157 sc_iterator superregclasses_end() const {
158 sc_iterator I = SuperRegClasses;
159 while (*I != NULL) ++I;
163 /// hasSubClass - return true if the the specified TargetRegisterClass
164 /// is a proper subset of this TargetRegisterClass.
165 bool hasSubClass(const TargetRegisterClass *cs) const {
166 for (int i = 0; SubClasses[i] != NULL; ++i)
167 if (SubClasses[i] == cs)
172 /// subclasses_begin / subclasses_end - Loop over all of the classes
173 /// that are proper subsets of this register class.
174 sc_iterator subclasses_begin() const {
178 sc_iterator subclasses_end() const {
179 sc_iterator I = SubClasses;
180 while (*I != NULL) ++I;
184 /// hasSuperClass - return true if the specified TargetRegisterClass is a
185 /// proper superset of this TargetRegisterClass.
186 bool hasSuperClass(const TargetRegisterClass *cs) const {
187 for (int i = 0; SuperClasses[i] != NULL; ++i)
188 if (SuperClasses[i] == cs)
193 /// superclasses_begin / superclasses_end - Loop over all of the classes
194 /// that are proper supersets of this register class.
195 sc_iterator superclasses_begin() const {
199 sc_iterator superclasses_end() const {
200 sc_iterator I = SuperClasses;
201 while (*I != NULL) ++I;
205 /// isASubClass - return true if this TargetRegisterClass is a subset
206 /// class of at least one other TargetRegisterClass.
207 bool isASubClass() const {
208 return SuperClasses[0] != 0;
211 /// allocation_order_begin/end - These methods define a range of registers
212 /// which specify the registers in this class that are valid to register
213 /// allocate, and the preferred order to allocate them in. For example,
214 /// callee saved registers should be at the end of the list, because it is
215 /// cheaper to allocate caller saved registers.
217 /// These methods take a MachineFunction argument, which can be used to tune
218 /// the allocatable registers based on the characteristics of the function.
219 /// One simple example is that the frame pointer register can be used if
220 /// frame-pointer-elimination is performed.
222 /// By default, these methods return all registers in the class.
224 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
227 virtual iterator allocation_order_end(const MachineFunction &MF) const {
233 /// getSize - Return the size of the register in bytes, which is also the size
234 /// of a stack slot allocated to hold a spilled copy of this register.
235 unsigned getSize() const { return RegSize; }
237 /// getAlignment - Return the minimum required alignment for a register of
239 unsigned getAlignment() const { return Alignment; }
241 /// getCopyCost - Return the cost of copying a value between two registers in
242 /// this class. A negative number means the register class is very expensive
243 /// to copy e.g. status flag register classes.
244 int getCopyCost() const { return CopyCost; }
248 /// TargetRegisterInfo base class - We assume that the target defines a static
249 /// array of TargetRegisterDesc objects that represent all of the machine
250 /// registers that the target has. As such, we simply have to track a pointer
251 /// to this array so that we can turn register number into a register
254 class TargetRegisterInfo {
256 const unsigned* SubregHash;
257 const unsigned SubregHashSize;
258 const unsigned* SuperregHash;
259 const unsigned SuperregHashSize;
260 const unsigned* AliasesHash;
261 const unsigned AliasesHashSize;
263 typedef const TargetRegisterClass * const * regclass_iterator;
265 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
266 unsigned NumRegs; // Number of entries in the array
268 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
270 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
272 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
273 regclass_iterator RegClassBegin,
274 regclass_iterator RegClassEnd,
275 int CallFrameSetupOpcode = -1,
276 int CallFrameDestroyOpcode = -1,
277 const unsigned* subregs = 0,
278 const unsigned subregsize = 0,
279 const unsigned* superregs = 0,
280 const unsigned superregsize = 0,
281 const unsigned* aliases = 0,
282 const unsigned aliasessize = 0);
283 virtual ~TargetRegisterInfo();
286 enum { // Define some target independent constants
287 /// NoRegister - This physical register is not a real target register. It
288 /// is useful as a sentinal.
291 /// FirstVirtualRegister - This is the first register number that is
292 /// considered to be a 'virtual' register, which is part of the SSA
293 /// namespace. This must be the same for all targets, which means that each
294 /// target is limited to 1024 registers.
295 FirstVirtualRegister = 1024
298 /// isPhysicalRegister - Return true if the specified register number is in
299 /// the physical register namespace.
300 static bool isPhysicalRegister(unsigned Reg) {
301 assert(Reg && "this is not a register!");
302 return Reg < FirstVirtualRegister;
305 /// isVirtualRegister - Return true if the specified register number is in
306 /// the virtual register namespace.
307 static bool isVirtualRegister(unsigned Reg) {
308 assert(Reg && "this is not a register!");
309 return Reg >= FirstVirtualRegister;
312 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
313 /// register of the given type. If type is MVT::Other, then just return any
314 /// register class the register belongs to.
315 virtual const TargetRegisterClass *
316 getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
318 /// getAllocatableSet - Returns a bitset indexed by register number
319 /// indicating if a register is allocatable or not. If a register class is
320 /// specified, returns the subset for the class.
321 BitVector getAllocatableSet(MachineFunction &MF,
322 const TargetRegisterClass *RC = NULL) const;
324 const TargetRegisterDesc &operator[](unsigned RegNo) const {
325 assert(RegNo < NumRegs &&
326 "Attempting to access record for invalid register number!");
330 /// Provide a get method, equivalent to [], but more useful if we have a
331 /// pointer to this object.
333 const TargetRegisterDesc &get(unsigned RegNo) const {
334 return operator[](RegNo);
337 /// getAliasSet - Return the set of registers aliased by the specified
338 /// register, or a null list of there are none. The list returned is zero
341 const unsigned *getAliasSet(unsigned RegNo) const {
342 return get(RegNo).AliasSet;
345 /// getSubRegisters - Return the list of registers that are sub-registers of
346 /// the specified register, or a null list of there are none. The list
347 /// returned is zero terminated and sorted according to super-sub register
348 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
350 const unsigned *getSubRegisters(unsigned RegNo) const {
351 return get(RegNo).SubRegs;
354 /// getSuperRegisters - Return the list of registers that are super-registers
355 /// of the specified register, or a null list of there are none. The list
356 /// returned is zero terminated and sorted according to super-sub register
357 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
359 const unsigned *getSuperRegisters(unsigned RegNo) const {
360 return get(RegNo).SuperRegs;
363 /// getAsmName - Return the symbolic target-specific name for the
364 /// specified physical register.
365 const char *getAsmName(unsigned RegNo) const {
366 return get(RegNo).AsmName;
369 /// getName - Return the human-readable symbolic target-specific name for the
370 /// specified physical register.
371 const char *getName(unsigned RegNo) const {
372 return get(RegNo).Name;
375 /// getNumRegs - Return the number of registers this target has (useful for
376 /// sizing arrays holding per register information)
377 unsigned getNumRegs() const {
381 /// areAliases - Returns true if the two registers alias each other, false
383 bool areAliases(unsigned regA, unsigned regB) const {
384 size_t index = (regA + regB * 37) & (AliasesHashSize-1);
385 unsigned ProbeAmt = 0;
386 while (AliasesHash[index*2] != 0 &&
387 AliasesHash[index*2+1] != 0) {
388 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB)
391 index = (index + ProbeAmt) & (AliasesHashSize-1);
398 /// regsOverlap - Returns true if the two registers are equal or alias each
399 /// other. The registers may be virtual register.
400 bool regsOverlap(unsigned regA, unsigned regB) const {
404 if (isVirtualRegister(regA) || isVirtualRegister(regB))
406 return areAliases(regA, regB);
409 /// isSubRegister - Returns true if regB is a sub-register of regA.
411 bool isSubRegister(unsigned regA, unsigned regB) const {
412 // SubregHash is a simple quadratically probed hash table.
413 size_t index = (regA + regB * 37) & (SubregHashSize-1);
414 unsigned ProbeAmt = 2;
415 while (SubregHash[index*2] != 0 &&
416 SubregHash[index*2+1] != 0) {
417 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
420 index = (index + ProbeAmt) & (SubregHashSize-1);
427 /// isSuperRegister - Returns true if regB is a super-register of regA.
429 bool isSuperRegister(unsigned regA, unsigned regB) const {
430 // SuperregHash is a simple quadratically probed hash table.
431 size_t index = (regA + regB * 37) & (SuperregHashSize-1);
432 unsigned ProbeAmt = 2;
433 while (SuperregHash[index*2] != 0 &&
434 SuperregHash[index*2+1] != 0) {
435 if (SuperregHash[index*2] == regA && SuperregHash[index*2+1] == regB)
438 index = (index + ProbeAmt) & (SuperregHashSize-1);
445 /// getCalleeSavedRegs - Return a null-terminated list of all of the
446 /// callee saved registers on this target. The register should be in the
447 /// order of desired callee-save stack frame offset. The first register is
448 /// closed to the incoming stack pointer if stack grows down, and vice versa.
449 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
452 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
453 /// register classes to spill each callee saved register with. The order and
454 /// length of this list match the getCalleeSaveRegs() list.
455 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
456 const MachineFunction *MF) const =0;
458 /// getReservedRegs - Returns a bitset indexed by physical register number
459 /// indicating if a register is a special register that has particular uses
460 /// and should be considered unavailable at all times, e.g. SP, RA. This is
461 /// used by register scavenger to determine what registers are free.
462 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
464 /// getSubReg - Returns the physical register number of sub-register "Index"
465 /// for physical register RegNo. Return zero if the sub-register does not
467 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
469 //===--------------------------------------------------------------------===//
470 // Register Class Information
473 /// Register class iterators
475 regclass_iterator regclass_begin() const { return RegClassBegin; }
476 regclass_iterator regclass_end() const { return RegClassEnd; }
478 unsigned getNumRegClasses() const {
479 return (unsigned)(regclass_end()-regclass_begin());
482 /// getRegClass - Returns the register class associated with the enumeration
483 /// value. See class TargetOperandInfo.
484 const TargetRegisterClass *getRegClass(unsigned i) const {
485 assert(i <= getNumRegClasses() && "Register Class ID out of range");
486 return i ? RegClassBegin[i - 1] : NULL;
489 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
491 virtual const TargetRegisterClass *getPointerRegClass() const {
492 assert(0 && "Target didn't implement getPointerRegClass!");
493 return 0; // Must return a value in order to compile with VS 2005
496 /// getCrossCopyRegClass - Returns a legal register class to copy a register
497 /// in the specified class to or from. Returns NULL if it is possible to copy
498 /// between a two registers of the specified class.
499 virtual const TargetRegisterClass *
500 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
504 /// targetHandlesStackFrameRounding - Returns true if the target is
505 /// responsible for rounding up the stack frame (probably at emitPrologue
507 virtual bool targetHandlesStackFrameRounding() const {
511 /// requiresRegisterScavenging - returns true if the target requires (and can
512 /// make use of) the register scavenger.
513 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
517 /// hasFP - Return true if the specified function should have a dedicated
518 /// frame pointer register. For most targets this is true only if the function
519 /// has variable sized allocas or if frame pointer elimination is disabled.
520 virtual bool hasFP(const MachineFunction &MF) const = 0;
522 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
523 // not required, we reserve argument space for call sites in the function
524 // immediately on entry to the current function. This eliminates the need for
525 // add/sub sp brackets around call sites. Returns true if the call frame is
526 // included as part of the stack frame.
527 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
531 // needsStackRealignment - true if storage within the function requires the
532 // stack pointer to be aligned more than the normal calling convention calls
534 virtual bool needsStackRealignment(const MachineFunction &MF) const {
538 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
539 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
540 /// targets use pseudo instructions in order to abstract away the difference
541 /// between operating with a frame pointer and operating without, through the
542 /// use of these two instructions.
544 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
545 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
547 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
548 /// code insertion to eliminate call frame setup and destroy pseudo
549 /// instructions (but only if the Target is using them). It is responsible
550 /// for eliminating these instructions, replacing them with concrete
551 /// instructions. This method need only be implemented if using call frame
552 /// setup/destroy pseudo instructions.
555 eliminateCallFramePseudoInstr(MachineFunction &MF,
556 MachineBasicBlock &MBB,
557 MachineBasicBlock::iterator MI) const {
558 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
559 "eliminateCallFramePseudoInstr must be implemented if using"
560 " call frame setup/destroy pseudo instructions!");
561 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
564 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
565 /// before PrologEpilogInserter scans the physical registers used to determine
566 /// what callee saved registers should be spilled. This method is optional.
567 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
568 RegScavenger *RS = NULL) const {
572 /// processFunctionBeforeFrameFinalized - This method is called immediately
573 /// before the specified functions frame layout (MF.getFrameInfo()) is
574 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
575 /// replaced with direct constants. This method is optional.
577 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
580 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
581 /// frame indices from instructions which may use them. The instruction
582 /// referenced by the iterator contains an MO_FrameIndex operand which must be
583 /// eliminated by this method. This method may modify or replace the
584 /// specified instruction, as long as it keeps the iterator pointing the the
585 /// finished product. SPAdj is the SP adjustment due to call frame setup
587 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
588 int SPAdj, RegScavenger *RS=NULL) const = 0;
590 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
592 virtual void emitPrologue(MachineFunction &MF) const = 0;
593 virtual void emitEpilogue(MachineFunction &MF,
594 MachineBasicBlock &MBB) const = 0;
596 //===--------------------------------------------------------------------===//
597 /// Debug information queries.
599 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
600 /// number. Returns -1 if there is no equivalent value. The second
601 /// parameter allows targets to use different numberings for EH info and
603 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
605 /// getFrameRegister - This method should return the register used as a base
606 /// for values allocated in the current stack frame.
607 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
609 /// getFrameIndexOffset - Returns the displacement from the frame register to
610 /// the stack frame of the specified index.
611 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
613 /// getRARegister - This method should return the register where the return
614 /// address can be found.
615 virtual unsigned getRARegister() const = 0;
617 /// getInitialFrameState - Returns a list of machine moves that are assumed
618 /// on entry to all functions. Note that LabelID is ignored (assumed to be
619 /// the beginning of the function.)
620 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
623 // This is useful when building IndexedMaps keyed on virtual registers
624 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
625 unsigned operator()(unsigned Reg) const {
626 return Reg - TargetRegisterInfo::FirstVirtualRegister;
630 } // End llvm namespace