1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/ADT/DenseSet.h"
28 class MachineFunction;
31 template<class T> class SmallVectorImpl;
33 /// TargetRegisterDesc - This record contains all of the information known about
34 /// a particular register. The AliasSet field (if not null) contains a pointer
35 /// to a Zero terminated array of registers that this register aliases. This is
36 /// needed for architectures like X86 which have AL alias AX alias EAX.
37 /// Registers that this does not apply to simply should set this to null.
38 /// The SubRegs field is a zero terminated array of registers that are
39 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
40 /// The SuperRegs field is a zero terminated array of registers that are
41 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
44 struct TargetRegisterDesc {
45 const char *Name; // Printable name for the reg (for debugging)
46 const unsigned *AliasSet; // Register Alias Set, described above
47 const unsigned *SubRegs; // Sub-register set, described above
48 const unsigned *SuperRegs; // Super-register set, described above
51 class TargetRegisterClass {
53 typedef const unsigned* iterator;
54 typedef const unsigned* const_iterator;
56 typedef const EVT* vt_iterator;
57 typedef const TargetRegisterClass* const * sc_iterator;
61 const vt_iterator VTs;
62 const sc_iterator SubClasses;
63 const sc_iterator SuperClasses;
64 const sc_iterator SubRegClasses;
65 const sc_iterator SuperRegClasses;
66 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
68 const iterator RegsBegin, RegsEnd;
69 DenseSet<unsigned> RegSet;
71 TargetRegisterClass(unsigned id,
74 const TargetRegisterClass * const *subcs,
75 const TargetRegisterClass * const *supcs,
76 const TargetRegisterClass * const *subregcs,
77 const TargetRegisterClass * const *superregcs,
78 unsigned RS, unsigned Al, int CC,
79 iterator RB, iterator RE)
80 : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
81 SubRegClasses(subregcs), SuperRegClasses(superregcs),
82 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {
83 for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
86 virtual ~TargetRegisterClass() {} // Allow subclasses
88 /// getID() - Return the register class ID number.
90 unsigned getID() const { return ID; }
92 /// getName() - Return the register class name for debugging.
94 const char *getName() const { return Name; }
96 /// begin/end - Return all of the registers in this class.
98 iterator begin() const { return RegsBegin; }
99 iterator end() const { return RegsEnd; }
101 /// getNumRegs - Return the number of registers in this class.
103 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
105 /// getRegister - Return the specified register in the class.
107 unsigned getRegister(unsigned i) const {
108 assert(i < getNumRegs() && "Register number out of range!");
112 /// contains - Return true if the specified register is included in this
113 /// register class. This does not include virtual registers.
114 bool contains(unsigned Reg) const {
115 return RegSet.count(Reg);
118 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
120 bool hasType(EVT vt) const {
121 for(int i = 0; VTs[i].getSimpleVT().SimpleTy != MVT::Other; ++i)
127 /// vt_begin / vt_end - Loop over all of the value types that can be
128 /// represented by values in this register class.
129 vt_iterator vt_begin() const {
133 vt_iterator vt_end() const {
135 while (I->getSimpleVT().SimpleTy != MVT::Other) ++I;
139 /// subregclasses_begin / subregclasses_end - Loop over all of
140 /// the subreg register classes of this register class.
141 sc_iterator subregclasses_begin() const {
142 return SubRegClasses;
145 sc_iterator subregclasses_end() const {
146 sc_iterator I = SubRegClasses;
147 while (*I != NULL) ++I;
151 /// getSubRegisterRegClass - Return the register class of subregisters with
152 /// index SubIdx, or NULL if no such class exists.
153 const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
154 assert(SubIdx>0 && "Invalid subregister index");
155 return SubRegClasses[SubIdx-1];
158 /// superregclasses_begin / superregclasses_end - Loop over all of
159 /// the superreg register classes of this register class.
160 sc_iterator superregclasses_begin() const {
161 return SuperRegClasses;
164 sc_iterator superregclasses_end() const {
165 sc_iterator I = SuperRegClasses;
166 while (*I != NULL) ++I;
170 /// hasSubClass - return true if the specified TargetRegisterClass
171 /// is a proper subset of this TargetRegisterClass.
172 bool hasSubClass(const TargetRegisterClass *cs) const {
173 for (int i = 0; SubClasses[i] != NULL; ++i)
174 if (SubClasses[i] == cs)
179 /// subclasses_begin / subclasses_end - Loop over all of the classes
180 /// that are proper subsets of this register class.
181 sc_iterator subclasses_begin() const {
185 sc_iterator subclasses_end() const {
186 sc_iterator I = SubClasses;
187 while (*I != NULL) ++I;
191 /// hasSuperClass - return true if the specified TargetRegisterClass is a
192 /// proper superset of this TargetRegisterClass.
193 bool hasSuperClass(const TargetRegisterClass *cs) const {
194 for (int i = 0; SuperClasses[i] != NULL; ++i)
195 if (SuperClasses[i] == cs)
200 /// superclasses_begin / superclasses_end - Loop over all of the classes
201 /// that are proper supersets of this register class.
202 sc_iterator superclasses_begin() const {
206 sc_iterator superclasses_end() const {
207 sc_iterator I = SuperClasses;
208 while (*I != NULL) ++I;
212 /// isASubClass - return true if this TargetRegisterClass is a subset
213 /// class of at least one other TargetRegisterClass.
214 bool isASubClass() const {
215 return SuperClasses[0] != 0;
218 /// allocation_order_begin/end - These methods define a range of registers
219 /// which specify the registers in this class that are valid to register
220 /// allocate, and the preferred order to allocate them in. For example,
221 /// callee saved registers should be at the end of the list, because it is
222 /// cheaper to allocate caller saved registers.
224 /// These methods take a MachineFunction argument, which can be used to tune
225 /// the allocatable registers based on the characteristics of the function.
226 /// One simple example is that the frame pointer register can be used if
227 /// frame-pointer-elimination is performed.
229 /// By default, these methods return all registers in the class.
231 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
234 virtual iterator allocation_order_end(const MachineFunction &MF) const {
238 /// getSize - Return the size of the register in bytes, which is also the size
239 /// of a stack slot allocated to hold a spilled copy of this register.
240 unsigned getSize() const { return RegSize; }
242 /// getAlignment - Return the minimum required alignment for a register of
244 unsigned getAlignment() const { return Alignment; }
246 /// getCopyCost - Return the cost of copying a value between two registers in
247 /// this class. A negative number means the register class is very expensive
248 /// to copy e.g. status flag register classes.
249 int getCopyCost() const { return CopyCost; }
253 /// TargetRegisterInfo base class - We assume that the target defines a static
254 /// array of TargetRegisterDesc objects that represent all of the machine
255 /// registers that the target has. As such, we simply have to track a pointer
256 /// to this array so that we can turn register number into a register
259 class TargetRegisterInfo {
261 const unsigned* SubregHash;
262 const unsigned SubregHashSize;
263 const unsigned* AliasesHash;
264 const unsigned AliasesHashSize;
266 typedef const TargetRegisterClass * const * regclass_iterator;
268 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
269 const char *const *SubRegIndexNames; // Names of subreg indexes.
270 unsigned NumRegs; // Number of entries in the array
272 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
274 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
277 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
278 regclass_iterator RegClassBegin,
279 regclass_iterator RegClassEnd,
280 const char *const *subregindexnames,
281 int CallFrameSetupOpcode = -1,
282 int CallFrameDestroyOpcode = -1,
283 const unsigned* subregs = 0,
284 const unsigned subregsize = 0,
285 const unsigned* aliases = 0,
286 const unsigned aliasessize = 0);
287 virtual ~TargetRegisterInfo();
290 enum { // Define some target independent constants
291 /// NoRegister - This physical register is not a real target register. It
292 /// is useful as a sentinal.
295 /// FirstVirtualRegister - This is the first register number that is
296 /// considered to be a 'virtual' register, which is part of the SSA
297 /// namespace. This must be the same for all targets, which means that each
298 /// target is limited to this fixed number of registers.
299 FirstVirtualRegister = 1024
302 /// isPhysicalRegister - Return true if the specified register number is in
303 /// the physical register namespace.
304 static bool isPhysicalRegister(unsigned Reg) {
305 assert(Reg && "this is not a register!");
306 return Reg < FirstVirtualRegister;
309 /// isVirtualRegister - Return true if the specified register number is in
310 /// the virtual register namespace.
311 static bool isVirtualRegister(unsigned Reg) {
312 assert(Reg && "this is not a register!");
313 return Reg >= FirstVirtualRegister;
316 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
317 /// register of the given type. If type is EVT::Other, then just return any
318 /// register class the register belongs to.
319 virtual const TargetRegisterClass *
320 getPhysicalRegisterRegClass(unsigned Reg, EVT VT = MVT::Other) const;
322 /// getMinimalPhysRegClass - Returns the Register Class of a physical
323 /// register of the given type.
324 const TargetRegisterClass * getMinimalPhysRegClass(unsigned Reg) const;
326 /// getAllocatableSet - Returns a bitset indexed by register number
327 /// indicating if a register is allocatable or not. If a register class is
328 /// specified, returns the subset for the class.
329 BitVector getAllocatableSet(const MachineFunction &MF,
330 const TargetRegisterClass *RC = NULL) const;
332 const TargetRegisterDesc &operator[](unsigned RegNo) const {
333 assert(RegNo < NumRegs &&
334 "Attempting to access record for invalid register number!");
338 /// Provide a get method, equivalent to [], but more useful if we have a
339 /// pointer to this object.
341 const TargetRegisterDesc &get(unsigned RegNo) const {
342 return operator[](RegNo);
345 /// getAliasSet - Return the set of registers aliased by the specified
346 /// register, or a null list of there are none. The list returned is zero
349 const unsigned *getAliasSet(unsigned RegNo) const {
350 return get(RegNo).AliasSet;
353 /// getSubRegisters - Return the list of registers that are sub-registers of
354 /// the specified register, or a null list of there are none. The list
355 /// returned is zero terminated and sorted according to super-sub register
356 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
358 const unsigned *getSubRegisters(unsigned RegNo) const {
359 return get(RegNo).SubRegs;
362 /// getSuperRegisters - Return the list of registers that are super-registers
363 /// of the specified register, or a null list of there are none. The list
364 /// returned is zero terminated and sorted according to super-sub register
365 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
367 const unsigned *getSuperRegisters(unsigned RegNo) const {
368 return get(RegNo).SuperRegs;
371 /// getName - Return the human-readable symbolic target-specific name for the
372 /// specified physical register.
373 const char *getName(unsigned RegNo) const {
374 return get(RegNo).Name;
377 /// getNumRegs - Return the number of registers this target has (useful for
378 /// sizing arrays holding per register information)
379 unsigned getNumRegs() const {
383 /// getSubRegIndexName - Return the human-readable symbolic target-specific
384 /// name for the specified SubRegIndex.
385 const char *getSubRegIndexName(unsigned SubIdx) const {
386 assert(SubIdx && "This is not a subregister index");
387 return SubRegIndexNames[SubIdx-1];
390 /// regsOverlap - Returns true if the two registers are equal or alias each
391 /// other. The registers may be virtual register.
392 bool regsOverlap(unsigned regA, unsigned regB) const {
396 if (isVirtualRegister(regA) || isVirtualRegister(regB))
399 // regA and regB are distinct physical registers. Do they alias?
400 size_t index = (regA + regB * 37) & (AliasesHashSize-1);
401 unsigned ProbeAmt = 0;
402 while (AliasesHash[index*2] != 0 &&
403 AliasesHash[index*2+1] != 0) {
404 if (AliasesHash[index*2] == regA && AliasesHash[index*2+1] == regB)
407 index = (index + ProbeAmt) & (AliasesHashSize-1);
414 /// isSubRegister - Returns true if regB is a sub-register of regA.
416 bool isSubRegister(unsigned regA, unsigned regB) const {
417 // SubregHash is a simple quadratically probed hash table.
418 size_t index = (regA + regB * 37) & (SubregHashSize-1);
419 unsigned ProbeAmt = 2;
420 while (SubregHash[index*2] != 0 &&
421 SubregHash[index*2+1] != 0) {
422 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
425 index = (index + ProbeAmt) & (SubregHashSize-1);
432 /// isSuperRegister - Returns true if regB is a super-register of regA.
434 bool isSuperRegister(unsigned regA, unsigned regB) const {
435 return isSubRegister(regB, regA);
438 /// getCalleeSavedRegs - Return a null-terminated list of all of the
439 /// callee saved registers on this target. The register should be in the
440 /// order of desired callee-save stack frame offset. The first register is
441 /// closed to the incoming stack pointer if stack grows down, and vice versa.
442 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
446 /// getReservedRegs - Returns a bitset indexed by physical register number
447 /// indicating if a register is a special register that has particular uses
448 /// and should be considered unavailable at all times, e.g. SP, RA. This is
449 /// used by register scavenger to determine what registers are free.
450 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
452 /// getSubReg - Returns the physical register number of sub-register "Index"
453 /// for physical register RegNo. Return zero if the sub-register does not
455 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
457 /// getSubRegIndex - For a given register pair, return the sub-register index
458 /// if the second register is a sub-register of the first. Return zero
460 virtual unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const = 0;
462 /// getMatchingSuperReg - Return a super-register of the specified register
463 /// Reg so its sub-register of index SubIdx is Reg.
464 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
465 const TargetRegisterClass *RC) const {
466 for (const unsigned *SRs = getSuperRegisters(Reg); unsigned SR = *SRs;++SRs)
467 if (Reg == getSubReg(SR, SubIdx) && RC->contains(SR))
472 /// canCombineSubRegIndices - Given a register class and a list of
473 /// subregister indices, return true if it's possible to combine the
474 /// subregister indices into one that corresponds to a larger
475 /// subregister. Return the new subregister index by reference. Note the
476 /// new index may be zero if the given subregisters can be combined to
477 /// form the whole register.
478 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
479 SmallVectorImpl<unsigned> &SubIndices,
480 unsigned &NewSubIdx) const {
484 /// getMatchingSuperRegClass - Return a subclass of the specified register
485 /// class A so that each register in it has a sub-register of the
486 /// specified sub-register index which is in the specified register class B.
487 virtual const TargetRegisterClass *
488 getMatchingSuperRegClass(const TargetRegisterClass *A,
489 const TargetRegisterClass *B, unsigned Idx) const {
493 /// composeSubRegIndices - Return the subregister index you get from composing
494 /// two subregister indices.
496 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
497 /// returns c. Note that composeSubRegIndices does not tell you about illegal
498 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
499 /// b, composeSubRegIndices doesn't tell you.
501 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
502 /// ssub_0:S0 - ssub_3:S3 subregs.
503 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
505 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
506 // This default implementation is correct for most targets.
510 //===--------------------------------------------------------------------===//
511 // Register Class Information
514 /// Register class iterators
516 regclass_iterator regclass_begin() const { return RegClassBegin; }
517 regclass_iterator regclass_end() const { return RegClassEnd; }
519 unsigned getNumRegClasses() const {
520 return (unsigned)(regclass_end()-regclass_begin());
523 /// getRegClass - Returns the register class associated with the enumeration
524 /// value. See class TargetOperandInfo.
525 const TargetRegisterClass *getRegClass(unsigned i) const {
526 assert(i <= getNumRegClasses() && "Register Class ID out of range");
527 return i ? RegClassBegin[i - 1] : NULL;
530 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
531 /// values. If a target supports multiple different pointer register classes,
532 /// kind specifies which one is indicated.
533 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
534 assert(0 && "Target didn't implement getPointerRegClass!");
535 return 0; // Must return a value in order to compile with VS 2005
538 /// getCrossCopyRegClass - Returns a legal register class to copy a register
539 /// in the specified class to or from. Returns NULL if it is possible to copy
540 /// between a two registers of the specified class.
541 virtual const TargetRegisterClass *
542 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
546 /// getAllocationOrder - Returns the register allocation order for a specified
547 /// register class in the form of a pair of TargetRegisterClass iterators.
548 virtual std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
549 getAllocationOrder(const TargetRegisterClass *RC,
550 unsigned HintType, unsigned HintReg,
551 const MachineFunction &MF) const {
552 return std::make_pair(RC->allocation_order_begin(MF),
553 RC->allocation_order_end(MF));
556 /// ResolveRegAllocHint - Resolves the specified register allocation hint
557 /// to a physical register. Returns the physical register if it is successful.
558 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
559 const MachineFunction &MF) const {
560 if (Type == 0 && Reg && isPhysicalRegister(Reg))
565 /// UpdateRegAllocHint - A callback to allow target a chance to update
566 /// register allocation hints when a register is "changed" (e.g. coalesced)
567 /// to another register. e.g. On ARM, some virtual registers should target
568 /// register pairs, if one of pair is coalesced to another register, the
569 /// allocation hint of the other half of the pair should be changed to point
570 /// to the new register.
571 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
572 MachineFunction &MF) const {
576 /// targetHandlesStackFrameRounding - Returns true if the target is
577 /// responsible for rounding up the stack frame (probably at emitPrologue
579 virtual bool targetHandlesStackFrameRounding() const {
583 /// requiresRegisterScavenging - returns true if the target requires (and can
584 /// make use of) the register scavenger.
585 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
589 /// requiresFrameIndexScavenging - returns true if the target requires post
590 /// PEI scavenging of registers for materializing frame index constants.
591 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
595 /// hasFP - Return true if the specified function should have a dedicated
596 /// frame pointer register. For most targets this is true only if the function
597 /// has variable sized allocas or if frame pointer elimination is disabled.
598 virtual bool hasFP(const MachineFunction &MF) const = 0;
600 /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
601 /// not required, we reserve argument space for call sites in the function
602 /// immediately on entry to the current function. This eliminates the need for
603 /// add/sub sp brackets around call sites. Returns true if the call frame is
604 /// included as part of the stack frame.
605 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
609 /// canSimplifyCallFramePseudos - When possible, it's best to simplify the
610 /// call frame pseudo ops before doing frame index elimination. This is
611 /// possible only when frame index references between the pseudos won't
612 /// need adjusted for the call frame adjustments. Normally, that's true
613 /// if the function has a reserved call frame or a frame pointer. Some
614 /// targets (Thumb2, for example) may have more complicated criteria,
615 /// however, and can override this behavior.
616 virtual bool canSimplifyCallFramePseudos(MachineFunction &MF) const {
617 return hasReservedCallFrame(MF) || hasFP(MF);
620 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
621 /// the stack frame of the given function for the specified register. e.g. On
622 /// x86, if the frame register is required, the first fixed stack object is
623 /// reserved as its spill slot. This tells PEI not to create a new stack frame
624 /// object for the given register. It should be called only after
625 /// processFunctionBeforeCalleeSavedScan().
626 virtual bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
627 int &FrameIdx) const {
631 /// needsStackRealignment - true if storage within the function requires the
632 /// stack pointer to be aligned more than the normal calling convention calls
634 virtual bool needsStackRealignment(const MachineFunction &MF) const {
638 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
639 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
640 /// targets use pseudo instructions in order to abstract away the difference
641 /// between operating with a frame pointer and operating without, through the
642 /// use of these two instructions.
644 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
645 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
647 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
648 /// code insertion to eliminate call frame setup and destroy pseudo
649 /// instructions (but only if the Target is using them). It is responsible
650 /// for eliminating these instructions, replacing them with concrete
651 /// instructions. This method need only be implemented if using call frame
652 /// setup/destroy pseudo instructions.
655 eliminateCallFramePseudoInstr(MachineFunction &MF,
656 MachineBasicBlock &MBB,
657 MachineBasicBlock::iterator MI) const {
658 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
659 "eliminateCallFramePseudoInstr must be implemented if using"
660 " call frame setup/destroy pseudo instructions!");
661 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
664 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
665 /// before PrologEpilogInserter scans the physical registers used to determine
666 /// what callee saved registers should be spilled. This method is optional.
667 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
668 RegScavenger *RS = NULL) const {
672 /// processFunctionBeforeFrameFinalized - This method is called immediately
673 /// before the specified functions frame layout (MF.getFrameInfo()) is
674 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
675 /// replaced with direct constants. This method is optional.
677 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
680 /// saveScavengerRegister - Spill the register so it can be used by the
681 /// register scavenger. Return true if the register was spilled, false
682 /// otherwise. If this function does not spill the register, the scavenger
683 /// will instead spill it to the emergency spill slot.
685 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
686 MachineBasicBlock::iterator I,
687 MachineBasicBlock::iterator &UseMI,
688 const TargetRegisterClass *RC,
689 unsigned Reg) const {
693 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
694 /// frame indices from instructions which may use them. The instruction
695 /// referenced by the iterator contains an MO_FrameIndex operand which must be
696 /// eliminated by this method. This method may modify or replace the
697 /// specified instruction, as long as it keeps the iterator pointing at the
698 /// finished product. SPAdj is the SP adjustment due to call frame setup
701 /// When -enable-frame-index-scavenging is enabled, the virtual register
702 /// allocated for this frame index is returned and its value is stored in
704 typedef std::pair<unsigned, int> FrameIndexValue;
705 virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI,
706 int SPAdj, FrameIndexValue *Value = NULL,
707 RegScavenger *RS=NULL) const = 0;
709 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
711 virtual void emitPrologue(MachineFunction &MF) const = 0;
712 virtual void emitEpilogue(MachineFunction &MF,
713 MachineBasicBlock &MBB) const = 0;
715 //===--------------------------------------------------------------------===//
716 /// Debug information queries.
718 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
719 /// number. Returns -1 if there is no equivalent value. The second
720 /// parameter allows targets to use different numberings for EH info and
722 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
724 /// getFrameRegister - This method should return the register used as a base
725 /// for values allocated in the current stack frame.
726 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
728 /// getFrameIndexOffset - Returns the displacement from the frame register to
729 /// the stack frame of the specified index.
730 virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
732 /// getFrameIndexReference - This method should return the base register
733 /// and offset used to reference a frame index location. The offset is
734 /// returned directly, and the base register is returned via FrameReg.
735 virtual int getFrameIndexReference(const MachineFunction &MF, int FI,
736 unsigned &FrameReg) const {
737 // By default, assume all frame indices are referenced via whatever
738 // getFrameRegister() says. The target can override this if it's doing
739 // something different.
740 FrameReg = getFrameRegister(MF);
741 return getFrameIndexOffset(MF, FI);
744 /// getRARegister - This method should return the register where the return
745 /// address can be found.
746 virtual unsigned getRARegister() const = 0;
748 /// getInitialFrameState - Returns a list of machine moves that are assumed
749 /// on entry to all functions. Note that LabelID is ignored (assumed to be
750 /// the beginning of the function.)
751 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
755 // This is useful when building IndexedMaps keyed on virtual registers
756 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
757 unsigned operator()(unsigned Reg) const {
758 return Reg - TargetRegisterInfo::FirstVirtualRegister;
762 /// getCommonSubClass - find the largest common subclass of A and B. Return NULL
763 /// if there is no common subclass.
764 const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
765 const TargetRegisterClass *B);
767 } // End llvm namespace