1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/ValueTypes.h"
27 class MachineFunction;
31 /// TargetRegisterDesc - This record contains all of the information known about
32 /// a particular register. The AliasSet field (if not null) contains a pointer
33 /// to a Zero terminated array of registers that this register aliases. This is
34 /// needed for architectures like X86 which have AL alias AX alias EAX.
35 /// Registers that this does not apply to simply should set this to null.
36 /// The SubRegs field is a zero terminated array of registers that are
37 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
38 /// The SuperRegs field is a zero terminated array of registers that are
39 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
42 struct TargetRegisterDesc {
43 const char *AsmName; // Assembly language name for the register
44 const char *Name; // Printable name for the reg (for debugging)
45 const unsigned *AliasSet; // Register Alias Set, described above
46 const unsigned *SubRegs; // Sub-register set, described above
47 const unsigned *SuperRegs; // Super-register set, described above
50 class TargetRegisterClass {
52 typedef const unsigned* iterator;
53 typedef const unsigned* const_iterator;
55 typedef const MVT* vt_iterator;
56 typedef const TargetRegisterClass* const * sc_iterator;
60 const vt_iterator VTs;
61 const sc_iterator SubClasses;
62 const sc_iterator SuperClasses;
63 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
65 const iterator RegsBegin, RegsEnd;
67 TargetRegisterClass(unsigned id,
69 const TargetRegisterClass * const *subcs,
70 const TargetRegisterClass * const *supcs,
71 unsigned RS, unsigned Al, int CC,
72 iterator RB, iterator RE)
73 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
74 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
75 virtual ~TargetRegisterClass() {} // Allow subclasses
77 /// getID() - Return the register class ID number.
79 unsigned getID() const { return ID; }
81 /// begin/end - Return all of the registers in this class.
83 iterator begin() const { return RegsBegin; }
84 iterator end() const { return RegsEnd; }
86 /// getNumRegs - Return the number of registers in this class.
88 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
90 /// getRegister - Return the specified register in the class.
92 unsigned getRegister(unsigned i) const {
93 assert(i < getNumRegs() && "Register number out of range!");
97 /// contains - Return true if the specified register is included in this
99 bool contains(unsigned Reg) const {
100 for (iterator I = begin(), E = end(); I != E; ++I)
101 if (*I == Reg) return true;
105 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
107 bool hasType(MVT vt) const {
108 for(int i = 0; VTs[i] != MVT::Other; ++i)
114 /// vt_begin / vt_end - Loop over all of the value types that can be
115 /// represented by values in this register class.
116 vt_iterator vt_begin() const {
120 vt_iterator vt_end() const {
122 while (*I != MVT::Other) ++I;
126 /// hasSubClass - return true if the specified TargetRegisterClass is a
127 /// sub-register class of this TargetRegisterClass.
128 bool hasSubClass(const TargetRegisterClass *cs) const {
129 for (int i = 0; SubClasses[i] != NULL; ++i)
130 if (SubClasses[i] == cs)
135 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
136 /// this register class.
137 sc_iterator subclasses_begin() const {
141 sc_iterator subclasses_end() const {
142 sc_iterator I = SubClasses;
143 while (*I != NULL) ++I;
147 /// hasSuperClass - return true if the specified TargetRegisterClass is a
148 /// super-register class of this TargetRegisterClass.
149 bool hasSuperClass(const TargetRegisterClass *cs) const {
150 for (int i = 0; SuperClasses[i] != NULL; ++i)
151 if (SuperClasses[i] == cs)
156 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
157 /// of this register class.
158 sc_iterator superclasses_begin() const {
162 sc_iterator superclasses_end() const {
163 sc_iterator I = SuperClasses;
164 while (*I != NULL) ++I;
168 /// isASubClass - return true if this TargetRegisterClass is a sub-class of at
169 /// least one other TargetRegisterClass.
170 bool isASubClass() const {
171 return SuperClasses[0] != 0;
174 /// allocation_order_begin/end - These methods define a range of registers
175 /// which specify the registers in this class that are valid to register
176 /// allocate, and the preferred order to allocate them in. For example,
177 /// callee saved registers should be at the end of the list, because it is
178 /// cheaper to allocate caller saved registers.
180 /// These methods take a MachineFunction argument, which can be used to tune
181 /// the allocatable registers based on the characteristics of the function.
182 /// One simple example is that the frame pointer register can be used if
183 /// frame-pointer-elimination is performed.
185 /// By default, these methods return all registers in the class.
187 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
190 virtual iterator allocation_order_end(const MachineFunction &MF) const {
196 /// getSize - Return the size of the register in bytes, which is also the size
197 /// of a stack slot allocated to hold a spilled copy of this register.
198 unsigned getSize() const { return RegSize; }
200 /// getAlignment - Return the minimum required alignment for a register of
202 unsigned getAlignment() const { return Alignment; }
204 /// getCopyCost - Return the cost of copying a value between two registers in
206 int getCopyCost() const { return CopyCost; }
210 /// TargetRegisterInfo base class - We assume that the target defines a static
211 /// array of TargetRegisterDesc objects that represent all of the machine
212 /// registers that the target has. As such, we simply have to track a pointer
213 /// to this array so that we can turn register number into a register
216 class TargetRegisterInfo {
218 const unsigned* SubregHash;
219 const unsigned SubregHashSize;
221 typedef const TargetRegisterClass * const * regclass_iterator;
223 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
224 unsigned NumRegs; // Number of entries in the array
226 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
228 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
230 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
231 regclass_iterator RegClassBegin,
232 regclass_iterator RegClassEnd,
233 int CallFrameSetupOpcode = -1,
234 int CallFrameDestroyOpcode = -1,
235 const unsigned* subregs = 0,
236 const unsigned subregsize = 0);
237 virtual ~TargetRegisterInfo();
240 enum { // Define some target independent constants
241 /// NoRegister - This physical register is not a real target register. It
242 /// is useful as a sentinal.
245 /// FirstVirtualRegister - This is the first register number that is
246 /// considered to be a 'virtual' register, which is part of the SSA
247 /// namespace. This must be the same for all targets, which means that each
248 /// target is limited to 1024 registers.
249 FirstVirtualRegister = 1024
252 /// isPhysicalRegister - Return true if the specified register number is in
253 /// the physical register namespace.
254 static bool isPhysicalRegister(unsigned Reg) {
255 assert(Reg && "this is not a register!");
256 return Reg < FirstVirtualRegister;
259 /// isVirtualRegister - Return true if the specified register number is in
260 /// the virtual register namespace.
261 static bool isVirtualRegister(unsigned Reg) {
262 assert(Reg && "this is not a register!");
263 return Reg >= FirstVirtualRegister;
266 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
267 /// register of the given type. If type is MVT::Other, then just return any
268 /// register class the register belongs to.
269 const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned Reg,
270 MVT VT = MVT::Other) const;
272 /// getAllocatableSet - Returns a bitset indexed by register number
273 /// indicating if a register is allocatable or not. If a register class is
274 /// specified, returns the subset for the class.
275 BitVector getAllocatableSet(MachineFunction &MF,
276 const TargetRegisterClass *RC = NULL) const;
278 const TargetRegisterDesc &operator[](unsigned RegNo) const {
279 assert(RegNo < NumRegs &&
280 "Attempting to access record for invalid register number!");
284 /// Provide a get method, equivalent to [], but more useful if we have a
285 /// pointer to this object.
287 const TargetRegisterDesc &get(unsigned RegNo) const {
288 return operator[](RegNo);
291 /// getAliasSet - Return the set of registers aliased by the specified
292 /// register, or a null list of there are none. The list returned is zero
295 const unsigned *getAliasSet(unsigned RegNo) const {
296 return get(RegNo).AliasSet;
299 /// getSubRegisters - Return the list of registers that are sub-registers of
300 /// the specified register, or a null list of there are none. The list
301 /// returned is zero terminated and sorted according to super-sub register
302 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
304 const unsigned *getSubRegisters(unsigned RegNo) const {
305 return get(RegNo).SubRegs;
308 /// getSuperRegisters - Return the list of registers that are super-registers
309 /// of the specified register, or a null list of there are none. The list
310 /// returned is zero terminated and sorted according to super-sub register
311 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
313 const unsigned *getSuperRegisters(unsigned RegNo) const {
314 return get(RegNo).SuperRegs;
317 /// getAsmName - Return the symbolic target-specific name for the
318 /// specified physical register.
319 const char *getAsmName(unsigned RegNo) const {
320 return get(RegNo).AsmName;
323 /// getName - Return the human-readable symbolic target-specific name for the
324 /// specified physical register.
325 const char *getName(unsigned RegNo) const {
326 return get(RegNo).Name;
329 /// getNumRegs - Return the number of registers this target has (useful for
330 /// sizing arrays holding per register information)
331 unsigned getNumRegs() const {
335 /// areAliases - Returns true if the two registers alias each other, false
337 bool areAliases(unsigned regA, unsigned regB) const {
338 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
339 if (*Alias == regB) return true;
343 /// regsOverlap - Returns true if the two registers are equal or alias each
344 /// other. The registers may be virtual register.
345 bool regsOverlap(unsigned regA, unsigned regB) const {
349 if (isVirtualRegister(regA) || isVirtualRegister(regB))
351 return areAliases(regA, regB);
354 /// isSubRegister - Returns true if regB is a sub-register of regA.
356 bool isSubRegister(unsigned regA, unsigned regB) const {
357 // SubregHash is a simple quadratically probed hash table.
358 size_t index = (regA + regB * 37) & (SubregHashSize-1);
359 unsigned ProbeAmt = 2;
360 while (SubregHash[index*2] != 0 &&
361 SubregHash[index*2+1] != 0) {
362 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
365 index = (index + ProbeAmt) & (SubregHashSize-1);
372 /// isSuperRegister - Returns true if regB is a super-register of regA.
374 bool isSuperRegister(unsigned regA, unsigned regB) const {
375 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
376 if (*SR == regB) return true;
380 /// getCalleeSavedRegs - Return a null-terminated list of all of the
381 /// callee saved registers on this target. The register should be in the
382 /// order of desired callee-save stack frame offset. The first register is
383 /// closed to the incoming stack pointer if stack grows down, and vice versa.
384 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
387 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
388 /// register classes to spill each callee saved register with. The order and
389 /// length of this list match the getCalleeSaveRegs() list.
390 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
391 const MachineFunction *MF) const =0;
393 /// getReservedRegs - Returns a bitset indexed by physical register number
394 /// indicating if a register is a special register that has particular uses
395 /// and should be considered unavailable at all times, e.g. SP, RA. This is
396 /// used by register scavenger to determine what registers are free.
397 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
399 /// getSubReg - Returns the physical register number of sub-register "Index"
400 /// for physical register RegNo. Return zero if the sub-register does not
402 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
404 //===--------------------------------------------------------------------===//
405 // Register Class Information
408 /// Register class iterators
410 regclass_iterator regclass_begin() const { return RegClassBegin; }
411 regclass_iterator regclass_end() const { return RegClassEnd; }
413 unsigned getNumRegClasses() const {
414 return (unsigned)(regclass_end()-regclass_begin());
417 /// getRegClass - Returns the register class associated with the enumeration
418 /// value. See class TargetOperandInfo.
419 const TargetRegisterClass *getRegClass(unsigned i) const {
420 assert(i <= getNumRegClasses() && "Register Class ID out of range");
421 return i ? RegClassBegin[i - 1] : NULL;
424 //===--------------------------------------------------------------------===//
425 // Interfaces used by the register allocator and stack frame
426 // manipulation passes to move data around between registers,
427 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
430 /// getCrossCopyRegClass - Returns a legal register class to copy a register
431 /// in the specified class to or from. Returns NULL if it is possible to copy
432 /// between a two registers of the specified class.
433 virtual const TargetRegisterClass *
434 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
438 /// targetHandlesStackFrameRounding - Returns true if the target is
439 /// responsible for rounding up the stack frame (probably at emitPrologue
441 virtual bool targetHandlesStackFrameRounding() const {
445 /// requiresRegisterScavenging - returns true if the target requires (and can
446 /// make use of) the register scavenger.
447 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
451 /// hasFP - Return true if the specified function should have a dedicated
452 /// frame pointer register. For most targets this is true only if the function
453 /// has variable sized allocas or if frame pointer elimination is disabled.
454 virtual bool hasFP(const MachineFunction &MF) const = 0;
456 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
457 // not required, we reserve argument space for call sites in the function
458 // immediately on entry to the current function. This eliminates the need for
459 // add/sub sp brackets around call sites. Returns true if the call frame is
460 // included as part of the stack frame.
461 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
465 // needsStackRealignment - true if storage within the function requires the
466 // stack pointer to be aligned more than the normal calling convention calls
468 virtual bool needsStackRealignment(const MachineFunction &MF) const {
472 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
473 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
474 /// targets use pseudo instructions in order to abstract away the difference
475 /// between operating with a frame pointer and operating without, through the
476 /// use of these two instructions.
478 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
479 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
482 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
483 /// code insertion to eliminate call frame setup and destroy pseudo
484 /// instructions (but only if the Target is using them). It is responsible
485 /// for eliminating these instructions, replacing them with concrete
486 /// instructions. This method need only be implemented if using call frame
487 /// setup/destroy pseudo instructions.
490 eliminateCallFramePseudoInstr(MachineFunction &MF,
491 MachineBasicBlock &MBB,
492 MachineBasicBlock::iterator MI) const {
493 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
494 "eliminateCallFramePseudoInstr must be implemented if using"
495 " call frame setup/destroy pseudo instructions!");
496 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
499 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
500 /// before PrologEpilogInserter scans the physical registers used to determine
501 /// what callee saved registers should be spilled. This method is optional.
502 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
503 RegScavenger *RS = NULL) const {
507 /// processFunctionBeforeFrameFinalized - This method is called immediately
508 /// before the specified functions frame layout (MF.getFrameInfo()) is
509 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
510 /// replaced with direct constants. This method is optional.
512 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
515 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
516 /// frame indices from instructions which may use them. The instruction
517 /// referenced by the iterator contains an MO_FrameIndex operand which must be
518 /// eliminated by this method. This method may modify or replace the
519 /// specified instruction, as long as it keeps the iterator pointing the the
520 /// finished product. SPAdj is the SP adjustment due to call frame setup
522 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
523 int SPAdj, RegScavenger *RS=NULL) const = 0;
525 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
527 virtual void emitPrologue(MachineFunction &MF) const = 0;
528 virtual void emitEpilogue(MachineFunction &MF,
529 MachineBasicBlock &MBB) const = 0;
531 //===--------------------------------------------------------------------===//
532 /// Debug information queries.
534 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
535 /// number. Returns -1 if there is no equivalent value. The second
536 /// parameter allows targets to use different numberings for EH info and
538 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
540 /// getFrameRegister - This method should return the register used as a base
541 /// for values allocated in the current stack frame.
542 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
544 /// getFrameIndexOffset - Returns the displacement from the frame register to
545 /// the stack frame of the specified index.
546 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
548 /// getRARegister - This method should return the register where the return
549 /// address can be found.
550 virtual unsigned getRARegister() const = 0;
552 /// getInitialFrameState - Returns a list of machine moves that are assumed
553 /// on entry to all functions. Note that LabelID is ignored (assumed to be
554 /// the beginning of the function.)
555 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
558 // This is useful when building IndexedMaps keyed on virtual registers
559 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
560 unsigned operator()(unsigned Reg) const {
561 return Reg - TargetRegisterInfo::FirstVirtualRegister;
565 } // End llvm namespace