1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/ADT/SmallVector.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/ValueTypes.h"
29 class MachineFunction;
35 class TargetRegisterClass;
38 /// TargetRegisterDesc - This record contains all of the information known about
39 /// a particular register. The AliasSet field (if not null) contains a pointer
40 /// to a Zero terminated array of registers that this register aliases. This is
41 /// needed for architectures like X86 which have AL alias AX alias EAX.
42 /// Registers that this does not apply to simply should set this to null.
43 /// The SubRegs field is a zero terminated array of registers that are
44 /// sub-registers of the specific register, e.g. AL, AH are sub-registers of AX.
45 /// The SuperRegs field is a zero terminated array of registers that are
46 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
49 struct TargetRegisterDesc {
50 const char *AsmName; // Assembly language name for the register
51 const char *Name; // Printable name for the reg (for debugging)
52 const unsigned *AliasSet; // Register Alias Set, described above
53 const unsigned *SubRegs; // Sub-register set, described above
54 const unsigned *SuperRegs; // Super-register set, described above
57 class TargetRegisterClass {
59 typedef const unsigned* iterator;
60 typedef const unsigned* const_iterator;
62 typedef const MVT* vt_iterator;
63 typedef const TargetRegisterClass* const * sc_iterator;
67 const vt_iterator VTs;
68 const sc_iterator SubClasses;
69 const sc_iterator SuperClasses;
70 const sc_iterator SubRegClasses;
71 const sc_iterator SuperRegClasses;
72 const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
74 const iterator RegsBegin, RegsEnd;
76 TargetRegisterClass(unsigned id,
78 const TargetRegisterClass * const *subcs,
79 const TargetRegisterClass * const *supcs,
80 const TargetRegisterClass * const *subregcs,
81 const TargetRegisterClass * const *superregcs,
82 unsigned RS, unsigned Al, int CC,
83 iterator RB, iterator RE)
84 : ID(id), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
85 SubRegClasses(subregcs), SuperRegClasses(superregcs),
86 RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) {}
87 virtual ~TargetRegisterClass() {} // Allow subclasses
89 /// getID() - Return the register class ID number.
91 unsigned getID() const { return ID; }
93 /// begin/end - Return all of the registers in this class.
95 iterator begin() const { return RegsBegin; }
96 iterator end() const { return RegsEnd; }
98 /// getNumRegs - Return the number of registers in this class.
100 unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
102 /// getRegister - Return the specified register in the class.
104 unsigned getRegister(unsigned i) const {
105 assert(i < getNumRegs() && "Register number out of range!");
109 /// contains - Return true if the specified register is included in this
111 bool contains(unsigned Reg) const {
112 for (iterator I = begin(), E = end(); I != E; ++I)
113 if (*I == Reg) return true;
117 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
119 bool hasType(MVT vt) const {
120 for(int i = 0; VTs[i] != MVT::Other; ++i)
126 /// vt_begin / vt_end - Loop over all of the value types that can be
127 /// represented by values in this register class.
128 vt_iterator vt_begin() const {
132 vt_iterator vt_end() const {
134 while (*I != MVT::Other) ++I;
138 /// hasSubClass - return true if the specified TargetRegisterClass is a
139 /// sub-register class of this TargetRegisterClass.
140 bool hasSubClass(const TargetRegisterClass *cs) const {
141 for (int i = 0; SubClasses[i] != NULL; ++i)
142 if (SubClasses[i] == cs)
147 /// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
148 /// this register class.
149 sc_iterator subclasses_begin() const {
153 sc_iterator subclasses_end() const {
154 sc_iterator I = SubClasses;
155 while (*I != NULL) ++I;
159 /// hasSuperClass - return true if the specified TargetRegisterClass is a
160 /// super-register class of this TargetRegisterClass.
161 bool hasSuperClass(const TargetRegisterClass *cs) const {
162 for (int i = 0; SuperClasses[i] != NULL; ++i)
163 if (SuperClasses[i] == cs)
168 /// superclasses_begin / superclasses_end - Loop over all of the super-classes
169 /// of this register class.
170 sc_iterator superclasses_begin() const {
174 sc_iterator superclasses_end() const {
175 sc_iterator I = SuperClasses;
176 while (*I != NULL) ++I;
180 /// hasSubRegClass - return true if the specified TargetRegisterClass is a
181 /// class of a sub-register class for this TargetRegisterClass.
182 bool hasSubRegClass(const TargetRegisterClass *cs) const {
183 for (int i = 0; SubRegClasses[i] != NULL; ++i)
184 if (SubRegClasses[i] == cs)
189 /// hasClassForSubReg - return true if the specified TargetRegisterClass is a
190 /// class of a sub-register class for this TargetRegisterClass.
191 bool hasClassForSubReg(unsigned SubReg) const {
193 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
199 /// getClassForSubReg - return theTargetRegisterClass for the sub-register
200 /// at idx for this TargetRegisterClass.
201 sc_iterator getClassForSubReg(unsigned SubReg) const {
203 for (unsigned i = 0; SubRegClasses[i] != NULL; ++i)
205 return &SubRegClasses[i];
206 assert(0 && "Invalid subregister index for register class");
210 /// subregclasses_begin / subregclasses_end - Loop over all of
211 /// the subregister classes of this register class.
212 sc_iterator subregclasses_begin() const {
213 return SubRegClasses;
216 sc_iterator subregclasses_end() const {
217 sc_iterator I = SubRegClasses;
218 while (*I != NULL) ++I;
222 /// superregclasses_begin / superregclasses_end - Loop over all of
223 /// the superregister classes of this register class.
224 sc_iterator superregclasses_begin() const {
225 return SuperRegClasses;
228 sc_iterator superregclasses_end() const {
229 sc_iterator I = SuperRegClasses;
230 while (*I != NULL) ++I;
234 /// allocation_order_begin/end - These methods define a range of registers
235 /// which specify the registers in this class that are valid to register
236 /// allocate, and the preferred order to allocate them in. For example,
237 /// callee saved registers should be at the end of the list, because it is
238 /// cheaper to allocate caller saved registers.
240 /// These methods take a MachineFunction argument, which can be used to tune
241 /// the allocatable registers based on the characteristics of the function.
242 /// One simple example is that the frame pointer register can be used if
243 /// frame-pointer-elimination is performed.
245 /// By default, these methods return all registers in the class.
247 virtual iterator allocation_order_begin(const MachineFunction &MF) const {
250 virtual iterator allocation_order_end(const MachineFunction &MF) const {
256 /// getSize - Return the size of the register in bytes, which is also the size
257 /// of a stack slot allocated to hold a spilled copy of this register.
258 unsigned getSize() const { return RegSize; }
260 /// getAlignment - Return the minimum required alignment for a register of
262 unsigned getAlignment() const { return Alignment; }
264 /// getCopyCost - Return the cost of copying a value between two registers in
266 int getCopyCost() const { return CopyCost; }
270 /// TargetRegisterInfo base class - We assume that the target defines a static
271 /// array of TargetRegisterDesc objects that represent all of the machine
272 /// registers that the target has. As such, we simply have to track a pointer
273 /// to this array so that we can turn register number into a register
276 class TargetRegisterInfo {
278 const unsigned* SubregHash;
279 const unsigned SubregHashSize;
281 typedef const TargetRegisterClass * const * regclass_iterator;
283 const TargetRegisterDesc *Desc; // Pointer to the descriptor array
284 unsigned NumRegs; // Number of entries in the array
286 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
288 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
290 TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
291 regclass_iterator RegClassBegin,
292 regclass_iterator RegClassEnd,
293 int CallFrameSetupOpcode = -1,
294 int CallFrameDestroyOpcode = -1,
295 const unsigned* subregs = 0,
296 const unsigned subregsize = 0);
297 virtual ~TargetRegisterInfo();
300 enum { // Define some target independent constants
301 /// NoRegister - This physical register is not a real target register. It
302 /// is useful as a sentinal.
305 /// FirstVirtualRegister - This is the first register number that is
306 /// considered to be a 'virtual' register, which is part of the SSA
307 /// namespace. This must be the same for all targets, which means that each
308 /// target is limited to 1024 registers.
309 FirstVirtualRegister = 1024
312 /// isPhysicalRegister - Return true if the specified register number is in
313 /// the physical register namespace.
314 static bool isPhysicalRegister(unsigned Reg) {
315 assert(Reg && "this is not a register!");
316 return Reg < FirstVirtualRegister;
319 /// isVirtualRegister - Return true if the specified register number is in
320 /// the virtual register namespace.
321 static bool isVirtualRegister(unsigned Reg) {
322 assert(Reg && "this is not a register!");
323 return Reg >= FirstVirtualRegister;
326 /// getPhysicalRegisterRegClass - Returns the Register Class of a physical
327 /// register of the given type. If type is MVT::Other, then just return any
328 /// register class the register belongs to.
329 const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned Reg,
330 MVT VT = MVT::Other) const;
332 /// getAllocatableSet - Returns a bitset indexed by register number
333 /// indicating if a register is allocatable or not. If a register class is
334 /// specified, returns the subset for the class.
335 BitVector getAllocatableSet(MachineFunction &MF,
336 const TargetRegisterClass *RC = NULL) const;
338 const TargetRegisterDesc &operator[](unsigned RegNo) const {
339 assert(RegNo < NumRegs &&
340 "Attempting to access record for invalid register number!");
344 /// Provide a get method, equivalent to [], but more useful if we have a
345 /// pointer to this object.
347 const TargetRegisterDesc &get(unsigned RegNo) const {
348 return operator[](RegNo);
351 /// getAliasSet - Return the set of registers aliased by the specified
352 /// register, or a null list of there are none. The list returned is zero
355 const unsigned *getAliasSet(unsigned RegNo) const {
356 return get(RegNo).AliasSet;
359 /// getSubRegisters - Return the list of registers that are sub-registers of
360 /// the specified register, or a null list of there are none. The list
361 /// returned is zero terminated and sorted according to super-sub register
362 /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
364 const unsigned *getSubRegisters(unsigned RegNo) const {
365 return get(RegNo).SubRegs;
368 /// getSuperRegisters - Return the list of registers that are super-registers
369 /// of the specified register, or a null list of there are none. The list
370 /// returned is zero terminated and sorted according to super-sub register
371 /// relations. e.g. X86::AL's super-register list is RAX, EAX, AX.
373 const unsigned *getSuperRegisters(unsigned RegNo) const {
374 return get(RegNo).SuperRegs;
377 /// getAsmName - Return the symbolic target-specific name for the
378 /// specified physical register.
379 const char *getAsmName(unsigned RegNo) const {
380 return get(RegNo).AsmName;
383 /// getName - Return the human-readable symbolic target-specific name for the
384 /// specified physical register.
385 const char *getName(unsigned RegNo) const {
386 return get(RegNo).Name;
389 /// getNumRegs - Return the number of registers this target has (useful for
390 /// sizing arrays holding per register information)
391 unsigned getNumRegs() const {
395 /// areAliases - Returns true if the two registers alias each other, false
397 bool areAliases(unsigned regA, unsigned regB) const {
398 for (const unsigned *Alias = getAliasSet(regA); *Alias; ++Alias)
399 if (*Alias == regB) return true;
403 /// regsOverlap - Returns true if the two registers are equal or alias each
404 /// other. The registers may be virtual register.
405 bool regsOverlap(unsigned regA, unsigned regB) const {
409 if (isVirtualRegister(regA) || isVirtualRegister(regB))
411 return areAliases(regA, regB);
414 /// isSubRegister - Returns true if regB is a sub-register of regA.
416 bool isSubRegister(unsigned regA, unsigned regB) const {
417 // SubregHash is a simple quadratically probed hash table.
418 size_t index = (regA + regB * 37) & (SubregHashSize-1);
419 unsigned ProbeAmt = 2;
420 while (SubregHash[index*2] != 0 &&
421 SubregHash[index*2+1] != 0) {
422 if (SubregHash[index*2] == regA && SubregHash[index*2+1] == regB)
425 index = (index + ProbeAmt) & (SubregHashSize-1);
432 /// isSuperRegister - Returns true if regB is a super-register of regA.
434 bool isSuperRegister(unsigned regA, unsigned regB) const {
435 for (const unsigned *SR = getSuperRegisters(regA); *SR; ++SR)
436 if (*SR == regB) return true;
440 /// getCalleeSavedRegs - Return a null-terminated list of all of the
441 /// callee saved registers on this target. The register should be in the
442 /// order of desired callee-save stack frame offset. The first register is
443 /// closed to the incoming stack pointer if stack grows down, and vice versa.
444 virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF = 0)
447 /// getCalleeSavedRegClasses - Return a null-terminated list of the preferred
448 /// register classes to spill each callee saved register with. The order and
449 /// length of this list match the getCalleeSaveRegs() list.
450 virtual const TargetRegisterClass* const *getCalleeSavedRegClasses(
451 const MachineFunction *MF) const =0;
453 /// getReservedRegs - Returns a bitset indexed by physical register number
454 /// indicating if a register is a special register that has particular uses
455 /// and should be considered unavailable at all times, e.g. SP, RA. This is
456 /// used by register scavenger to determine what registers are free.
457 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
459 /// getSubReg - Returns the physical register number of sub-register "Index"
460 /// for physical register RegNo. Return zero if the sub-register does not
462 virtual unsigned getSubReg(unsigned RegNo, unsigned Index) const = 0;
464 //===--------------------------------------------------------------------===//
465 // Register Class Information
468 /// Register class iterators
470 regclass_iterator regclass_begin() const { return RegClassBegin; }
471 regclass_iterator regclass_end() const { return RegClassEnd; }
473 unsigned getNumRegClasses() const {
474 return (unsigned)(regclass_end()-regclass_begin());
477 /// getRegClass - Returns the register class associated with the enumeration
478 /// value. See class TargetOperandInfo.
479 const TargetRegisterClass *getRegClass(unsigned i) const {
480 assert(i <= getNumRegClasses() && "Register Class ID out of range");
481 return i ? RegClassBegin[i - 1] : NULL;
484 //===--------------------------------------------------------------------===//
485 // Interfaces used by the register allocator and stack frame
486 // manipulation passes to move data around between registers,
487 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
490 /// getCrossCopyRegClass - Returns a legal register class to copy a register
491 /// in the specified class to or from. Returns NULL if it is possible to copy
492 /// between a two registers of the specified class.
493 virtual const TargetRegisterClass *
494 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
498 /// targetHandlesStackFrameRounding - Returns true if the target is
499 /// responsible for rounding up the stack frame (probably at emitPrologue
501 virtual bool targetHandlesStackFrameRounding() const {
505 /// requiresRegisterScavenging - returns true if the target requires (and can
506 /// make use of) the register scavenger.
507 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
511 /// hasFP - Return true if the specified function should have a dedicated
512 /// frame pointer register. For most targets this is true only if the function
513 /// has variable sized allocas or if frame pointer elimination is disabled.
514 virtual bool hasFP(const MachineFunction &MF) const = 0;
516 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
517 // not required, we reserve argument space for call sites in the function
518 // immediately on entry to the current function. This eliminates the need for
519 // add/sub sp brackets around call sites. Returns true if the call frame is
520 // included as part of the stack frame.
521 virtual bool hasReservedCallFrame(MachineFunction &MF) const {
525 // needsStackRealignment - true if storage within the function requires the
526 // stack pointer to be aligned more than the normal calling convention calls
528 virtual bool needsStackRealignment(const MachineFunction &MF) const {
532 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
533 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
534 /// targets use pseudo instructions in order to abstract away the difference
535 /// between operating with a frame pointer and operating without, through the
536 /// use of these two instructions.
538 int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; }
539 int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; }
542 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
543 /// code insertion to eliminate call frame setup and destroy pseudo
544 /// instructions (but only if the Target is using them). It is responsible
545 /// for eliminating these instructions, replacing them with concrete
546 /// instructions. This method need only be implemented if using call frame
547 /// setup/destroy pseudo instructions.
550 eliminateCallFramePseudoInstr(MachineFunction &MF,
551 MachineBasicBlock &MBB,
552 MachineBasicBlock::iterator MI) const {
553 assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 &&
554 "eliminateCallFramePseudoInstr must be implemented if using"
555 " call frame setup/destroy pseudo instructions!");
556 assert(0 && "Call Frame Pseudo Instructions do not exist on this target!");
559 /// processFunctionBeforeCalleeSavedScan - This method is called immediately
560 /// before PrologEpilogInserter scans the physical registers used to determine
561 /// what callee saved registers should be spilled. This method is optional.
562 virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
563 RegScavenger *RS = NULL) const {
567 /// processFunctionBeforeFrameFinalized - This method is called immediately
568 /// before the specified functions frame layout (MF.getFrameInfo()) is
569 /// finalized. Once the frame is finalized, MO_FrameIndex operands are
570 /// replaced with direct constants. This method is optional.
572 virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
575 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
576 /// frame indices from instructions which may use them. The instruction
577 /// referenced by the iterator contains an MO_FrameIndex operand which must be
578 /// eliminated by this method. This method may modify or replace the
579 /// specified instruction, as long as it keeps the iterator pointing the the
580 /// finished product. SPAdj is the SP adjustment due to call frame setup
581 /// instruction. The return value is the number of instructions added to
582 /// (negative if removed from) the basic block.
584 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
585 int SPAdj, RegScavenger *RS=NULL) const = 0;
587 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
588 /// the function. The return value is the number of instructions
589 /// added to (negative if removed from) the basic block (entry for prologue).
591 virtual void emitPrologue(MachineFunction &MF) const = 0;
592 virtual void emitEpilogue(MachineFunction &MF,
593 MachineBasicBlock &MBB) const = 0;
595 //===--------------------------------------------------------------------===//
596 /// Debug information queries.
598 /// getDwarfRegNum - Map a target register to an equivalent dwarf register
599 /// number. Returns -1 if there is no equivalent value. The second
600 /// parameter allows targets to use different numberings for EH info and
602 virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
604 /// getFrameRegister - This method should return the register used as a base
605 /// for values allocated in the current stack frame.
606 virtual unsigned getFrameRegister(MachineFunction &MF) const = 0;
608 /// getFrameIndexOffset - Returns the displacement from the frame register to
609 /// the stack frame of the specified index.
610 virtual int getFrameIndexOffset(MachineFunction &MF, int FI) const;
612 /// getRARegister - This method should return the register where the return
613 /// address can be found.
614 virtual unsigned getRARegister() const = 0;
616 /// getInitialFrameState - Returns a list of machine moves that are assumed
617 /// on entry to all functions. Note that LabelID is ignored (assumed to be
618 /// the beginning of the function.)
619 virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
622 // This is useful when building IndexedMaps keyed on virtual registers
623 struct VirtReg2IndexFunctor : std::unary_function<unsigned, unsigned> {
624 unsigned operator()(unsigned Reg) const {
625 return Reg - TargetRegisterInfo::FirstVirtualRegister;
629 } // End llvm namespace