1 //=== Target/TargetRegisterInfo.h - Target Register Information -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes an abstract interface used to get information about a
11 // target machines register file. This information is used for a variety of
12 // purposed, especially register allocation.
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
17 #define LLVM_TARGET_TARGETREGISTERINFO_H
19 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/ValueTypes.h"
22 #include "llvm/ADT/ArrayRef.h"
23 #include "llvm/CallingConv.h"
30 class MachineFunction;
32 template<class T> class SmallVectorImpl;
35 class TargetRegisterClass {
37 typedef const uint16_t* iterator;
38 typedef const uint16_t* const_iterator;
39 typedef const MVT::SimpleValueType* vt_iterator;
40 typedef const TargetRegisterClass* const * sc_iterator;
42 // Instance variables filled by tablegen, do not use!
43 const MCRegisterClass *MC;
44 const vt_iterator VTs;
45 const unsigned *SubClassMask;
46 const sc_iterator SuperClasses;
47 const sc_iterator SuperRegClasses;
48 ArrayRef<uint16_t> (*OrderFunc)(const MachineFunction&);
50 /// getID() - Return the register class ID number.
52 unsigned getID() const { return MC->getID(); }
54 /// getName() - Return the register class name for debugging.
56 const char *getName() const { return MC->getName(); }
58 /// begin/end - Return all of the registers in this class.
60 iterator begin() const { return MC->begin(); }
61 iterator end() const { return MC->end(); }
63 /// getNumRegs - Return the number of registers in this class.
65 unsigned getNumRegs() const { return MC->getNumRegs(); }
67 /// getRegister - Return the specified register in the class.
69 unsigned getRegister(unsigned i) const {
70 return MC->getRegister(i);
73 /// contains - Return true if the specified register is included in this
74 /// register class. This does not include virtual registers.
75 bool contains(unsigned Reg) const {
76 return MC->contains(Reg);
79 /// contains - Return true if both registers are in this class.
80 bool contains(unsigned Reg1, unsigned Reg2) const {
81 return MC->contains(Reg1, Reg2);
84 /// getSize - Return the size of the register in bytes, which is also the size
85 /// of a stack slot allocated to hold a spilled copy of this register.
86 unsigned getSize() const { return MC->getSize(); }
88 /// getAlignment - Return the minimum required alignment for a register of
90 unsigned getAlignment() const { return MC->getAlignment(); }
92 /// getCopyCost - Return the cost of copying a value between two registers in
93 /// this class. A negative number means the register class is very expensive
94 /// to copy e.g. status flag register classes.
95 int getCopyCost() const { return MC->getCopyCost(); }
97 /// isAllocatable - Return true if this register class may be used to create
98 /// virtual registers.
99 bool isAllocatable() const { return MC->isAllocatable(); }
101 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
103 bool hasType(EVT vt) const {
104 for(int i = 0; VTs[i] != MVT::Other; ++i)
105 if (EVT(VTs[i]) == vt)
110 /// vt_begin / vt_end - Loop over all of the value types that can be
111 /// represented by values in this register class.
112 vt_iterator vt_begin() const {
116 vt_iterator vt_end() const {
118 while (*I != MVT::Other) ++I;
122 /// superregclasses_begin / superregclasses_end - Loop over all of
123 /// the superreg register classes of this register class.
124 sc_iterator superregclasses_begin() const {
125 return SuperRegClasses;
128 sc_iterator superregclasses_end() const {
129 sc_iterator I = SuperRegClasses;
130 while (*I != NULL) ++I;
134 /// hasSubClass - return true if the specified TargetRegisterClass
135 /// is a proper sub-class of this TargetRegisterClass.
136 bool hasSubClass(const TargetRegisterClass *RC) const {
137 return RC != this && hasSubClassEq(RC);
140 /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
142 bool hasSubClassEq(const TargetRegisterClass *RC) const {
143 unsigned ID = RC->getID();
144 return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
147 /// hasSuperClass - return true if the specified TargetRegisterClass is a
148 /// proper super-class of this TargetRegisterClass.
149 bool hasSuperClass(const TargetRegisterClass *RC) const {
150 return RC->hasSubClass(this);
153 /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
155 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
156 return RC->hasSubClassEq(this);
159 /// getSubClassMask - Returns a bit vector of subclasses, including this one.
160 /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
162 const uint32_t *getSubClassMask() const {
166 /// getSuperClasses - Returns a NULL terminated list of super-classes. The
167 /// classes are ordered by ID which is also a topological ordering from large
168 /// to small classes. The list does NOT include the current class.
169 sc_iterator getSuperClasses() const {
173 /// isASubClass - return true if this TargetRegisterClass is a subset
174 /// class of at least one other TargetRegisterClass.
175 bool isASubClass() const {
176 return SuperClasses[0] != 0;
179 /// getRawAllocationOrder - Returns the preferred order for allocating
180 /// registers from this register class in MF. The raw order comes directly
181 /// from the .td file and may include reserved registers that are not
182 /// allocatable. Register allocators should also make sure to allocate
183 /// callee-saved registers only after all the volatiles are used. The
184 /// RegisterClassInfo class provides filtered allocation orders with
185 /// callee-saved registers moved to the end.
187 /// The MachineFunction argument can be used to tune the allocatable
188 /// registers based on the characteristics of the function, subtarget, or
191 /// By default, this method returns all registers in the class.
193 ArrayRef<uint16_t> getRawAllocationOrder(const MachineFunction &MF) const {
194 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
198 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
199 /// registers. These are used by codegen, not by MC.
200 struct TargetRegisterInfoDesc {
201 unsigned CostPerUse; // Extra cost of instructions using register.
202 bool inAllocatableClass; // Register belongs to an allocatable regclass.
205 /// TargetRegisterInfo base class - We assume that the target defines a static
206 /// array of TargetRegisterDesc objects that represent all of the machine
207 /// registers that the target has. As such, we simply have to track a pointer
208 /// to this array so that we can turn register number into a register
211 class TargetRegisterInfo : public MCRegisterInfo {
213 typedef const TargetRegisterClass * const * regclass_iterator;
215 const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
216 const char *const *SubRegIndexNames; // Names of subreg indexes.
217 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
220 TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
221 regclass_iterator RegClassBegin,
222 regclass_iterator RegClassEnd,
223 const char *const *subregindexnames);
224 virtual ~TargetRegisterInfo();
227 // Register numbers can represent physical registers, virtual registers, and
228 // sometimes stack slots. The unsigned values are divided into these ranges:
230 // 0 Not a register, can be used as a sentinel.
231 // [1;2^30) Physical registers assigned by TableGen.
232 // [2^30;2^31) Stack slots. (Rarely used.)
233 // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo.
235 // Further sentinels can be allocated from the small negative integers.
236 // DenseMapInfo<unsigned> uses -1u and -2u.
238 /// isStackSlot - Sometimes it is useful the be able to store a non-negative
239 /// frame index in a variable that normally holds a register. isStackSlot()
240 /// returns true if Reg is in the range used for stack slots.
242 /// Note that isVirtualRegister() and isPhysicalRegister() cannot handle stack
243 /// slots, so if a variable may contains a stack slot, always check
244 /// isStackSlot() first.
246 static bool isStackSlot(unsigned Reg) {
247 return int(Reg) >= (1 << 30);
250 /// stackSlot2Index - Compute the frame index from a register value
251 /// representing a stack slot.
252 static int stackSlot2Index(unsigned Reg) {
253 assert(isStackSlot(Reg) && "Not a stack slot");
254 return int(Reg - (1u << 30));
257 /// index2StackSlot - Convert a non-negative frame index to a stack slot
259 static unsigned index2StackSlot(int FI) {
260 assert(FI >= 0 && "Cannot hold a negative frame index.");
261 return FI + (1u << 30);
264 /// isPhysicalRegister - Return true if the specified register number is in
265 /// the physical register namespace.
266 static bool isPhysicalRegister(unsigned Reg) {
267 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
271 /// isVirtualRegister - Return true if the specified register number is in
272 /// the virtual register namespace.
273 static bool isVirtualRegister(unsigned Reg) {
274 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first.");
278 /// virtReg2Index - Convert a virtual register number to a 0-based index.
279 /// The first virtual register in a function will get the index 0.
280 static unsigned virtReg2Index(unsigned Reg) {
281 assert(isVirtualRegister(Reg) && "Not a virtual register");
282 return Reg & ~(1u << 31);
285 /// index2VirtReg - Convert a 0-based index to a virtual register number.
286 /// This is the inverse operation of VirtReg2IndexFunctor below.
287 static unsigned index2VirtReg(unsigned Index) {
288 return Index | (1u << 31);
291 /// getMinimalPhysRegClass - Returns the Register Class of a physical
292 /// register of the given type, picking the most sub register class of
293 /// the right type that contains this physreg.
294 const TargetRegisterClass *
295 getMinimalPhysRegClass(unsigned Reg, EVT VT = MVT::Other) const;
297 /// getAllocatableSet - Returns a bitset indexed by register number
298 /// indicating if a register is allocatable or not. If a register class is
299 /// specified, returns the subset for the class.
300 BitVector getAllocatableSet(const MachineFunction &MF,
301 const TargetRegisterClass *RC = NULL) const;
303 /// getCostPerUse - Return the additional cost of using this register instead
304 /// of other registers in its class.
305 unsigned getCostPerUse(unsigned RegNo) const {
306 return InfoDesc[RegNo].CostPerUse;
309 /// isInAllocatableClass - Return true if the register is in the allocation
310 /// of any register class.
311 bool isInAllocatableClass(unsigned RegNo) const {
312 return InfoDesc[RegNo].inAllocatableClass;
315 /// getSubRegIndexName - Return the human-readable symbolic target-specific
316 /// name for the specified SubRegIndex.
317 const char *getSubRegIndexName(unsigned SubIdx) const {
318 assert(SubIdx && "This is not a subregister index");
319 return SubRegIndexNames[SubIdx-1];
322 /// regsOverlap - Returns true if the two registers are equal or alias each
323 /// other. The registers may be virtual register.
324 bool regsOverlap(unsigned regA, unsigned regB) const {
325 if (regA == regB) return true;
326 if (isVirtualRegister(regA) || isVirtualRegister(regB))
328 for (const uint16_t *regList = getOverlaps(regA)+1; *regList; ++regList) {
329 if (*regList == regB) return true;
334 /// isSubRegister - Returns true if regB is a sub-register of regA.
336 bool isSubRegister(unsigned regA, unsigned regB) const {
337 return isSuperRegister(regB, regA);
340 /// isSuperRegister - Returns true if regB is a super-register of regA.
342 bool isSuperRegister(unsigned regA, unsigned regB) const {
343 for (const uint16_t *regList = getSuperRegisters(regA); *regList;++regList){
344 if (*regList == regB) return true;
349 /// getCalleeSavedRegs - Return a null-terminated list of all of the
350 /// callee saved registers on this target. The register should be in the
351 /// order of desired callee-save stack frame offset. The first register is
352 /// closest to the incoming stack pointer if stack grows down, and vice versa.
354 virtual const uint16_t* getCalleeSavedRegs(const MachineFunction *MF = 0)
357 /// getCallPreservedMask - Return a mask of call-preserved registers for the
358 /// given calling convention on the current sub-target. The mask should
359 /// include all call-preserved aliases. This is used by the register
360 /// allocator to determine which registers can be live across a call.
362 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
363 /// A set bit indicates that all bits of the corresponding register are
364 /// preserved across the function call. The bit mask is expected to be
365 /// sub-register complete, i.e. if A is preserved, so are all its
368 /// Bits are numbered from the LSB, so the bit for physical register Reg can
369 /// be found as (Mask[Reg / 32] >> Reg % 32) & 1.
371 /// A NULL pointer means that no register mask will be used, and call
372 /// instructions should use implicit-def operands to indicate call clobbered
375 virtual const uint32_t *getCallPreservedMask(CallingConv::ID) const {
376 // The default mask clobbers everything. All targets should override.
380 /// getReservedRegs - Returns a bitset indexed by physical register number
381 /// indicating if a register is a special register that has particular uses
382 /// and should be considered unavailable at all times, e.g. SP, RA. This is
383 /// used by register scavenger to determine what registers are free.
384 virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
386 /// getMatchingSuperReg - Return a super-register of the specified register
387 /// Reg so its sub-register of index SubIdx is Reg.
388 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
389 const TargetRegisterClass *RC) const {
390 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
393 /// canCombineSubRegIndices - Given a register class and a list of
394 /// subregister indices, return true if it's possible to combine the
395 /// subregister indices into one that corresponds to a larger
396 /// subregister. Return the new subregister index by reference. Note the
397 /// new index may be zero if the given subregisters can be combined to
398 /// form the whole register.
399 virtual bool canCombineSubRegIndices(const TargetRegisterClass *RC,
400 SmallVectorImpl<unsigned> &SubIndices,
401 unsigned &NewSubIdx) const {
405 /// getMatchingSuperRegClass - Return a subclass of the specified register
406 /// class A so that each register in it has a sub-register of the
407 /// specified sub-register index which is in the specified register class B.
409 /// TableGen will synthesize missing A sub-classes.
410 virtual const TargetRegisterClass *
411 getMatchingSuperRegClass(const TargetRegisterClass *A,
412 const TargetRegisterClass *B, unsigned Idx) const =0;
414 /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that
415 /// supports the sub-register index Idx.
416 /// If no such sub-class exists, return NULL.
417 /// If all registers in RC already have an Idx sub-register, return RC.
419 /// TableGen generates a version of this function that is good enough in most
420 /// cases. Targets can override if they have constraints that TableGen
421 /// doesn't understand. For example, the x86 sub_8bit sub-register index is
422 /// supported by the full GR32 register class in 64-bit mode, but only by the
423 /// GR32_ABCD regiister class in 32-bit mode.
425 /// TableGen will synthesize missing RC sub-classes.
426 virtual const TargetRegisterClass *
427 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0;
429 /// composeSubRegIndices - Return the subregister index you get from composing
430 /// two subregister indices.
432 /// If R:a:b is the same register as R:c, then composeSubRegIndices(a, b)
433 /// returns c. Note that composeSubRegIndices does not tell you about illegal
434 /// compositions. If R does not have a subreg a, or R:a does not have a subreg
435 /// b, composeSubRegIndices doesn't tell you.
437 /// The ARM register Q0 has two D subregs dsub_0:D0 and dsub_1:D1. It also has
438 /// ssub_0:S0 - ssub_3:S3 subregs.
439 /// If you compose subreg indices dsub_1, ssub_0 you get ssub_2.
441 virtual unsigned composeSubRegIndices(unsigned a, unsigned b) const {
442 // This default implementation is correct for most targets.
446 //===--------------------------------------------------------------------===//
447 // Register Class Information
450 /// Register class iterators
452 regclass_iterator regclass_begin() const { return RegClassBegin; }
453 regclass_iterator regclass_end() const { return RegClassEnd; }
455 unsigned getNumRegClasses() const {
456 return (unsigned)(regclass_end()-regclass_begin());
459 /// getRegClass - Returns the register class associated with the enumeration
460 /// value. See class MCOperandInfo.
461 const TargetRegisterClass *getRegClass(unsigned i) const {
462 assert(i < getNumRegClasses() && "Register Class ID out of range");
463 return RegClassBegin[i];
466 /// getCommonSubClass - find the largest common subclass of A and B. Return
467 /// NULL if there is no common subclass.
468 const TargetRegisterClass *
469 getCommonSubClass(const TargetRegisterClass *A,
470 const TargetRegisterClass *B) const;
472 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
473 /// values. If a target supports multiple different pointer register classes,
474 /// kind specifies which one is indicated.
475 virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const {
476 llvm_unreachable("Target didn't implement getPointerRegClass!");
479 /// getCrossCopyRegClass - Returns a legal register class to copy a register
480 /// in the specified class to or from. If it is possible to copy the register
481 /// directly without using a cross register class copy, return the specified
482 /// RC. Returns NULL if it is not possible to copy between a two registers of
483 /// the specified class.
484 virtual const TargetRegisterClass *
485 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
489 /// getLargestLegalSuperClass - Returns the largest super class of RC that is
490 /// legal to use in the current sub-target and has the same spill size.
491 /// The returned register class can be used to create virtual registers which
492 /// means that all its registers can be copied and spilled.
493 virtual const TargetRegisterClass*
494 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
495 /// The default implementation is very conservative and doesn't allow the
496 /// register allocator to inflate register classes.
500 /// getRegPressureLimit - Return the register pressure "high water mark" for
501 /// the specific register class. The scheduler is in high register pressure
502 /// mode (for the specific register class) if it goes over the limit.
504 /// Note: this is the old register pressure model that relies on a manually
505 /// specified representative register class per value type.
506 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
507 MachineFunction &MF) const {
511 /// Get the weight in units of pressure for this register class.
512 virtual unsigned getRegClassWeight(const TargetRegisterClass *RC) const = 0;
514 /// Get the number of dimensions of register pressure.
515 virtual unsigned getNumRegPressureSets() const = 0;
517 /// Get the register unit pressure limit for this dimension.
518 /// This limit must be adjusted dynamically for reserved registers.
519 virtual unsigned getRegPressureSetLimit(unsigned Idx) const = 0;
521 /// Get the dimensions of register pressure impacted by this register class.
522 /// Returns a -1 terminated array of pressure set IDs.
523 virtual const int *getRegClassPressureSets(
524 const TargetRegisterClass *RC) const = 0;
526 /// getRawAllocationOrder - Returns the register allocation order for a
527 /// specified register class with a target-dependent hint. The returned list
528 /// may contain reserved registers that cannot be allocated.
530 /// Register allocators need only call this function to resolve
531 /// target-dependent hints, but it should work without hinting as well.
532 virtual ArrayRef<uint16_t>
533 getRawAllocationOrder(const TargetRegisterClass *RC,
534 unsigned HintType, unsigned HintReg,
535 const MachineFunction &MF) const {
536 return RC->getRawAllocationOrder(MF);
539 /// ResolveRegAllocHint - Resolves the specified register allocation hint
540 /// to a physical register. Returns the physical register if it is successful.
541 virtual unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
542 const MachineFunction &MF) const {
543 if (Type == 0 && Reg && isPhysicalRegister(Reg))
548 /// avoidWriteAfterWrite - Return true if the register allocator should avoid
549 /// writing a register from RC in two consecutive instructions.
550 /// This can avoid pipeline stalls on certain architectures.
551 /// It does cause increased register pressure, though.
552 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const {
556 /// UpdateRegAllocHint - A callback to allow target a chance to update
557 /// register allocation hints when a register is "changed" (e.g. coalesced)
558 /// to another register. e.g. On ARM, some virtual registers should target
559 /// register pairs, if one of pair is coalesced to another register, the
560 /// allocation hint of the other half of the pair should be changed to point
561 /// to the new register.
562 virtual void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
563 MachineFunction &MF) const {
567 /// requiresRegisterScavenging - returns true if the target requires (and can
568 /// make use of) the register scavenger.
569 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const {
573 /// useFPForScavengingIndex - returns true if the target wants to use
574 /// frame pointer based accesses to spill to the scavenger emergency spill
576 virtual bool useFPForScavengingIndex(const MachineFunction &MF) const {
580 /// requiresFrameIndexScavenging - returns true if the target requires post
581 /// PEI scavenging of registers for materializing frame index constants.
582 virtual bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
586 /// requiresVirtualBaseRegisters - Returns true if the target wants the
587 /// LocalStackAllocation pass to be run and virtual base registers
588 /// used for more efficient stack access.
589 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
593 /// hasReservedSpillSlot - Return true if target has reserved a spill slot in
594 /// the stack frame of the given function for the specified register. e.g. On
595 /// x86, if the frame register is required, the first fixed stack object is
596 /// reserved as its spill slot. This tells PEI not to create a new stack frame
597 /// object for the given register. It should be called only after
598 /// processFunctionBeforeCalleeSavedScan().
599 virtual bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
600 int &FrameIdx) const {
604 /// needsStackRealignment - true if storage within the function requires the
605 /// stack pointer to be aligned more than the normal calling convention calls
607 virtual bool needsStackRealignment(const MachineFunction &MF) const {
611 /// getFrameIndexInstrOffset - Get the offset from the referenced frame
612 /// index in the instruction, if there is one.
613 virtual int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
618 /// needsFrameBaseReg - Returns true if the instruction's frame index
619 /// reference would be better served by a base register other than FP
620 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
621 /// references it should create new base registers for.
622 virtual bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
626 /// materializeFrameBaseRegister - Insert defining instruction(s) for
627 /// BaseReg to be a pointer to FrameIdx before insertion point I.
628 virtual void materializeFrameBaseRegister(MachineBasicBlock *MBB,
629 unsigned BaseReg, int FrameIdx,
630 int64_t Offset) const {
631 llvm_unreachable("materializeFrameBaseRegister does not exist on this "
635 /// resolveFrameIndex - Resolve a frame index operand of an instruction
636 /// to reference the indicated base register plus offset instead.
637 virtual void resolveFrameIndex(MachineBasicBlock::iterator I,
638 unsigned BaseReg, int64_t Offset) const {
639 llvm_unreachable("resolveFrameIndex does not exist on this target");
642 /// isFrameOffsetLegal - Determine whether a given offset immediate is
643 /// encodable to resolve a frame index.
644 virtual bool isFrameOffsetLegal(const MachineInstr *MI,
645 int64_t Offset) const {
646 llvm_unreachable("isFrameOffsetLegal does not exist on this target");
649 /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog
650 /// code insertion to eliminate call frame setup and destroy pseudo
651 /// instructions (but only if the Target is using them). It is responsible
652 /// for eliminating these instructions, replacing them with concrete
653 /// instructions. This method need only be implemented if using call frame
654 /// setup/destroy pseudo instructions.
657 eliminateCallFramePseudoInstr(MachineFunction &MF,
658 MachineBasicBlock &MBB,
659 MachineBasicBlock::iterator MI) const {
660 llvm_unreachable("Call Frame Pseudo Instructions do not exist on this "
665 /// saveScavengerRegister - Spill the register so it can be used by the
666 /// register scavenger. Return true if the register was spilled, false
667 /// otherwise. If this function does not spill the register, the scavenger
668 /// will instead spill it to the emergency spill slot.
670 virtual bool saveScavengerRegister(MachineBasicBlock &MBB,
671 MachineBasicBlock::iterator I,
672 MachineBasicBlock::iterator &UseMI,
673 const TargetRegisterClass *RC,
674 unsigned Reg) const {
678 /// eliminateFrameIndex - This method must be overriden to eliminate abstract
679 /// frame indices from instructions which may use them. The instruction
680 /// referenced by the iterator contains an MO_FrameIndex operand which must be
681 /// eliminated by this method. This method may modify or replace the
682 /// specified instruction, as long as it keeps the iterator pointing at the
683 /// finished product. SPAdj is the SP adjustment due to call frame setup
685 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
686 int SPAdj, RegScavenger *RS=NULL) const = 0;
688 //===--------------------------------------------------------------------===//
689 /// Debug information queries.
691 /// getFrameRegister - This method should return the register used as a base
692 /// for values allocated in the current stack frame.
693 virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
695 /// getCompactUnwindRegNum - This function maps the register to the number for
696 /// compact unwind encoding. Return -1 if the register isn't valid.
697 virtual int getCompactUnwindRegNum(unsigned, bool) const {
703 // This is useful when building IndexedMaps keyed on virtual registers
704 struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
705 unsigned operator()(unsigned Reg) const {
706 return TargetRegisterInfo::virtReg2Index(Reg);
710 /// PrintReg - Helper class for printing registers on a raw_ostream.
711 /// Prints virtual and physical registers with or without a TRI instance.
714 /// %noreg - NoRegister
715 /// %vreg5 - a virtual register.
716 /// %vreg5:sub_8bit - a virtual register with sub-register index (with TRI).
717 /// %EAX - a physical register
718 /// %physreg17 - a physical register when no TRI instance given.
720 /// Usage: OS << PrintReg(Reg, TRI) << '\n';
723 const TargetRegisterInfo *TRI;
727 PrintReg(unsigned reg, const TargetRegisterInfo *tri = 0, unsigned subidx = 0)
728 : TRI(tri), Reg(reg), SubIdx(subidx) {}
729 void print(raw_ostream&) const;
732 static inline raw_ostream &operator<<(raw_ostream &OS, const PrintReg &PR) {
737 } // End llvm namespace