1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand has floating-point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisVec - The specified operand has a vector type.
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
42 // SDTCisSameAs - The two specified operands have identical types.
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
44 int OtherOperandNum = OtherOp;
47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
48 // smaller than the 'Other' operand.
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
50 int OtherOperandNum = OtherOp;
53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
54 int BigOperandNum = BigOp;
57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
58 /// type as the element type of OtherOp, which is a vector type.
59 class SDTCisEltOfVec<int ThisOp, int OtherOp>
60 : SDTypeConstraint<ThisOp> {
61 int OtherOpNum = OtherOp;
64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
65 /// with length less that of OtherOp, which is a vector type.
66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
67 : SDTypeConstraint<ThisOp> {
68 int OtherOpNum = OtherOp;
71 //===----------------------------------------------------------------------===//
72 // Selection DAG Type Profile definitions.
74 // These use the constraints defined above to describe the type requirements of
75 // the various nodes. These are not hard coded into tblgen, allowing targets to
76 // add their own if needed.
79 // SDTypeProfile - This profile describes the type requirements of a Selection
81 class SDTypeProfile<int numresults, int numoperands,
82 list<SDTypeConstraint> constraints> {
83 int NumResults = numresults;
84 int NumOperands = numoperands;
85 list<SDTypeConstraint> Constraints = constraints;
89 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
90 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
91 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
92 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
93 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
94 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
96 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
97 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
99 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
100 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
102 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
103 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
106 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
107 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
109 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
110 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
112 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
115 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
116 SDTCisSameAs<0, 1>, SDTCisInt<0>
118 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
119 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
121 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
122 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
124 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
125 SDTCisSameAs<0, 1>, SDTCisFP<0>
127 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
128 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
130 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
131 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
133 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
134 SDTCisFP<0>, SDTCisInt<1>
136 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
137 SDTCisInt<0>, SDTCisFP<1>
139 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
140 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
141 SDTCisVTSmallerThanOp<2, 1>
144 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
145 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
148 def SDTSelect : SDTypeProfile<1, 3, [ // select
149 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
152 def SDTVSelect : SDTypeProfile<1, 3, [ // vselect
153 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
156 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
157 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
161 def SDTBr : SDTypeProfile<0, 1, [ // br
165 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
166 SDTCisInt<0>, SDTCisVT<1, OtherVT>
169 def SDTBrind : SDTypeProfile<0, 1, [ // brind
173 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
175 def SDTLoad : SDTypeProfile<1, 1, [ // load
179 def SDTStore : SDTypeProfile<0, 2, [ // store
183 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
184 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
187 def SDTVecShuffle : SDTypeProfile<1, 2, [
188 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
190 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
191 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
193 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
194 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
197 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
198 SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
200 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
201 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
204 def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch
205 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1>
208 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier
209 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
212 def SDTAtomicFence : SDTypeProfile<0, 2, [
213 SDTCisSameAs<0,1>, SDTCisPtrTy<0>
215 def SDTAtomic3 : SDTypeProfile<1, 3, [
216 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
218 def SDTAtomic2 : SDTypeProfile<1, 2, [
219 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
221 def SDTAtomicStore : SDTypeProfile<0, 2, [
222 SDTCisPtrTy<0>, SDTCisInt<1>
224 def SDTAtomicLoad : SDTypeProfile<1, 1, [
225 SDTCisInt<0>, SDTCisPtrTy<1>
228 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
229 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
232 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
233 SDTypeProfile<0, 1, constraints>;
234 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
235 SDTypeProfile<0, 2, constraints>;
237 //===----------------------------------------------------------------------===//
238 // Selection DAG Node Properties.
240 // Note: These are hard coded into tblgen.
242 class SDNodeProperty;
243 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
244 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
245 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
246 def SDNPOutGlue : SDNodeProperty; // Write a flag result
247 def SDNPInGlue : SDNodeProperty; // Read a flag operand
248 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand
249 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
250 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
251 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
252 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
253 def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
254 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match
255 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent
257 //===----------------------------------------------------------------------===//
258 // Selection DAG Pattern Operations
259 class SDPatternOperator;
261 //===----------------------------------------------------------------------===//
262 // Selection DAG Node definitions.
264 class SDNode<string opcode, SDTypeProfile typeprof,
265 list<SDNodeProperty> props = [], string sdclass = "SDNode">
266 : SDPatternOperator {
267 string Opcode = opcode;
268 string SDClass = sdclass;
269 list<SDNodeProperty> Properties = props;
270 SDTypeProfile TypeProfile = typeprof;
273 // Special TableGen-recognized dag nodes
279 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
280 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
281 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
282 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
283 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
284 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
285 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
286 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
287 "GlobalAddressSDNode">;
288 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
289 "GlobalAddressSDNode">;
290 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
291 "GlobalAddressSDNode">;
292 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
293 "GlobalAddressSDNode">;
294 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
295 "ConstantPoolSDNode">;
296 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
297 "ConstantPoolSDNode">;
298 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
300 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
302 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
304 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
306 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
307 "ExternalSymbolSDNode">;
308 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
309 "ExternalSymbolSDNode">;
310 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
311 "BlockAddressSDNode">;
312 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
313 "BlockAddressSDNode">;
315 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
316 [SDNPCommutative, SDNPAssociative]>;
317 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
318 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
319 [SDNPCommutative, SDNPAssociative]>;
320 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
321 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
322 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
323 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
324 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
325 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
326 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
327 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
328 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
329 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
330 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
331 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
332 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
333 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
334 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
335 def and : SDNode<"ISD::AND" , SDTIntBinOp,
336 [SDNPCommutative, SDNPAssociative]>;
337 def or : SDNode<"ISD::OR" , SDTIntBinOp,
338 [SDNPCommutative, SDNPAssociative]>;
339 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
340 [SDNPCommutative, SDNPAssociative]>;
341 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
342 [SDNPCommutative, SDNPOutGlue]>;
343 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
344 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>;
345 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
347 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
348 [SDNPOutGlue, SDNPInGlue]>;
350 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
351 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
352 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
353 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
354 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
355 def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>;
356 def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>;
357 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
358 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
359 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
360 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
361 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>;
362 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
363 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
365 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
366 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
367 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
368 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
369 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
370 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>;
371 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
372 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
373 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
374 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
375 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
376 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
377 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
378 def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
379 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
380 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
381 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
382 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
383 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
384 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
385 def frnd : SDNode<"ISD::FROUND" , SDTFPUnaryOp>;
387 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
388 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
389 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
391 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
392 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
393 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
394 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
395 def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>;
396 def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>;
398 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
399 def select : SDNode<"ISD::SELECT" , SDTSelect>;
400 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
401 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
403 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
404 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
405 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
406 def trap : SDNode<"ISD::TRAP" , SDTNone,
407 [SDNPHasChain, SDNPSideEffect]>;
408 def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone,
409 [SDNPHasChain, SDNPSideEffect]>;
411 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
412 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
415 def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf,
416 [SDNPHasChain, SDNPSideEffect]>;
418 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
419 [SDNPHasChain, SDNPSideEffect]>;
421 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
422 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
423 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2,
424 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
425 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2,
426 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
427 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2,
428 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
429 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2,
430 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
431 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2,
432 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
433 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2,
434 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
435 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2,
436 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
437 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2,
438 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
439 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2,
440 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
441 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2,
442 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
443 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
444 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
445 def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad,
446 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
447 def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
448 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
450 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
451 // and truncst (see below).
452 def ld : SDNode<"ISD::LOAD" , SDTLoad,
453 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
454 def st : SDNode<"ISD::STORE" , SDTStore,
455 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
456 def ist : SDNode<"ISD::STORE" , SDTIStore,
457 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
459 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
460 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
461 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
463 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
464 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
465 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
466 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
467 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
468 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>;
470 // This operator does not do subvector type checking. The ARM
471 // backend, at least, needs it.
472 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
473 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
476 // This operator does subvector type checking.
477 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
478 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
480 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
481 // these internally. Don't reference these directly.
482 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
483 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
485 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
486 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
488 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
489 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
491 // Do not use cvt directly. Use cvt forms below
492 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
494 def SDT_assertext : SDTypeProfile<1, 1,
495 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
496 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
497 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
500 //===----------------------------------------------------------------------===//
501 // Selection DAG Condition Codes
503 class CondCode; // ISD::CondCode enums
504 def SETOEQ : CondCode; def SETOGT : CondCode;
505 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
506 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
507 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
508 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
510 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
511 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
514 //===----------------------------------------------------------------------===//
515 // Selection DAG Node Transformation Functions.
517 // This mechanism allows targets to manipulate nodes in the output DAG once a
518 // match has been formed. This is typically used to manipulate immediate
521 class SDNodeXForm<SDNode opc, code xformFunction> {
523 code XFormFunction = xformFunction;
526 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
528 //===----------------------------------------------------------------------===//
529 // PatPred Subclasses.
531 // These allow specifying different sorts of predicates that control whether a
536 class CodePatPred<code predicate> : PatPred {
537 code PredicateCode = predicate;
541 //===----------------------------------------------------------------------===//
542 // Selection DAG Pattern Fragments.
544 // Pattern fragments are reusable chunks of dags that match specific things.
545 // They can take arguments and have C++ predicates that control whether they
546 // match. They are intended to make the patterns for common instructions more
547 // compact and readable.
550 /// PatFrag - Represents a pattern fragment. This can match something on the
551 /// DAG, from a single node to multiple nested other fragments.
553 class PatFrag<dag ops, dag frag, code pred = [{}],
554 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator {
557 code PredicateCode = pred;
558 code ImmediateCode = [{}];
559 SDNodeXForm OperandTransform = xform;
562 // OutPatFrag is a pattern fragment that is used as part of an output pattern
563 // (not an input pattern). These do not have predicates or transforms, but are
564 // used to avoid repeated subexpressions in output patterns.
565 class OutPatFrag<dag ops, dag frag>
566 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>;
568 // PatLeaf's are pattern fragments that have no operands. This is just a helper
569 // to define immediates and other common things concisely.
570 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
571 : PatFrag<(ops), frag, pred, xform>;
574 // ImmLeaf is a pattern fragment with a constraint on the immediate. The
575 // constraint is a function that is run on the immediate (always with the value
576 // sign extended out to an int64_t) as Imm. For example:
578 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>;
580 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also
581 // is preferred over using PatLeaf because it allows the code generator to
582 // reason more about the constraint.
584 // If FastIsel should ignore all instructions that have an operand of this type,
585 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce
586 // the code size of the generated fast instruction selector.
587 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
588 : PatFrag<(ops), (vt imm), [{}], xform> {
589 let ImmediateCode = pred;
590 bit FastIselShouldIgnore = 0;
596 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
597 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
599 def immAllOnesV: PatLeaf<(build_vector), [{
600 return ISD::isBuildVectorAllOnes(N);
602 def immAllZerosV: PatLeaf<(build_vector), [{
603 return ISD::isBuildVectorAllZeros(N);
608 // Other helper fragments.
609 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
610 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
611 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
613 // null_frag - The null pattern operator is used in multiclass instantiations
614 // which accept an SDPatternOperator for use in matching patterns for internal
615 // definitions. When expanding a pattern, if the null fragment is referenced
616 // in the expansion, the pattern is discarded and it is as-if '[]' had been
617 // specified. This allows multiclasses to have the isel patterns be optional.
618 def null_frag : SDPatternOperator;
621 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
622 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
624 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
625 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
628 // extending load fragments.
629 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
630 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
632 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
633 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
635 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
636 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
639 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
640 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
642 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
643 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
645 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
646 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
648 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
649 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
651 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
652 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
654 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
655 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
658 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
659 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
661 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
662 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
664 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
665 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
667 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
668 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
671 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
672 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
674 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
675 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
677 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
678 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
680 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
681 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
684 def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
685 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
687 def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
688 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
690 def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
691 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
693 def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
694 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
696 def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
697 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f32;
699 def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
700 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f64;
703 def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
704 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
706 def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
707 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
709 def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
710 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
712 def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
713 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
716 def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
717 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
719 def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
720 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
722 def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
723 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
725 def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
726 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
730 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
731 (st node:$val, node:$ptr), [{
732 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
734 def store : PatFrag<(ops node:$val, node:$ptr),
735 (unindexedstore node:$val, node:$ptr), [{
736 return !cast<StoreSDNode>(N)->isTruncatingStore();
739 // truncstore fragments.
740 def truncstore : PatFrag<(ops node:$val, node:$ptr),
741 (unindexedstore node:$val, node:$ptr), [{
742 return cast<StoreSDNode>(N)->isTruncatingStore();
744 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
745 (truncstore node:$val, node:$ptr), [{
746 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
748 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
749 (truncstore node:$val, node:$ptr), [{
750 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
752 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
753 (truncstore node:$val, node:$ptr), [{
754 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
756 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
757 (truncstore node:$val, node:$ptr), [{
758 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
760 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
761 (truncstore node:$val, node:$ptr), [{
762 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
765 // indexed store fragments.
766 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
767 (ist node:$val, node:$base, node:$offset), [{
768 return !cast<StoreSDNode>(N)->isTruncatingStore();
771 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
772 (istore node:$val, node:$base, node:$offset), [{
773 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
774 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
777 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
778 (ist node:$val, node:$base, node:$offset), [{
779 return cast<StoreSDNode>(N)->isTruncatingStore();
781 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
782 (itruncstore node:$val, node:$base, node:$offset), [{
783 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
784 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
786 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
787 (pre_truncst node:$val, node:$base, node:$offset), [{
788 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
790 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
791 (pre_truncst node:$val, node:$base, node:$offset), [{
792 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
794 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
795 (pre_truncst node:$val, node:$base, node:$offset), [{
796 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
798 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
799 (pre_truncst node:$val, node:$base, node:$offset), [{
800 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
802 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
803 (pre_truncst node:$val, node:$base, node:$offset), [{
804 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
807 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
808 (istore node:$val, node:$ptr, node:$offset), [{
809 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
810 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
813 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
814 (itruncstore node:$val, node:$base, node:$offset), [{
815 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
816 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
818 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
819 (post_truncst node:$val, node:$base, node:$offset), [{
820 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
822 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
823 (post_truncst node:$val, node:$base, node:$offset), [{
824 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
826 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
827 (post_truncst node:$val, node:$base, node:$offset), [{
828 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
830 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
831 (post_truncst node:$val, node:$base, node:$offset), [{
832 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
834 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
835 (post_truncst node:$val, node:$base, node:$offset), [{
836 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
839 // setcc convenience fragments.
840 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
841 (setcc node:$lhs, node:$rhs, SETOEQ)>;
842 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
843 (setcc node:$lhs, node:$rhs, SETOGT)>;
844 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
845 (setcc node:$lhs, node:$rhs, SETOGE)>;
846 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
847 (setcc node:$lhs, node:$rhs, SETOLT)>;
848 def setole : PatFrag<(ops node:$lhs, node:$rhs),
849 (setcc node:$lhs, node:$rhs, SETOLE)>;
850 def setone : PatFrag<(ops node:$lhs, node:$rhs),
851 (setcc node:$lhs, node:$rhs, SETONE)>;
852 def seto : PatFrag<(ops node:$lhs, node:$rhs),
853 (setcc node:$lhs, node:$rhs, SETO)>;
854 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
855 (setcc node:$lhs, node:$rhs, SETUO)>;
856 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
857 (setcc node:$lhs, node:$rhs, SETUEQ)>;
858 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
859 (setcc node:$lhs, node:$rhs, SETUGT)>;
860 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
861 (setcc node:$lhs, node:$rhs, SETUGE)>;
862 def setult : PatFrag<(ops node:$lhs, node:$rhs),
863 (setcc node:$lhs, node:$rhs, SETULT)>;
864 def setule : PatFrag<(ops node:$lhs, node:$rhs),
865 (setcc node:$lhs, node:$rhs, SETULE)>;
866 def setune : PatFrag<(ops node:$lhs, node:$rhs),
867 (setcc node:$lhs, node:$rhs, SETUNE)>;
868 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
869 (setcc node:$lhs, node:$rhs, SETEQ)>;
870 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
871 (setcc node:$lhs, node:$rhs, SETGT)>;
872 def setge : PatFrag<(ops node:$lhs, node:$rhs),
873 (setcc node:$lhs, node:$rhs, SETGE)>;
874 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
875 (setcc node:$lhs, node:$rhs, SETLT)>;
876 def setle : PatFrag<(ops node:$lhs, node:$rhs),
877 (setcc node:$lhs, node:$rhs, SETLE)>;
878 def setne : PatFrag<(ops node:$lhs, node:$rhs),
879 (setcc node:$lhs, node:$rhs, SETNE)>;
881 def atomic_cmp_swap_8 :
882 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
883 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
884 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
886 def atomic_cmp_swap_16 :
887 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
888 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
889 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
891 def atomic_cmp_swap_32 :
892 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
893 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
894 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
896 def atomic_cmp_swap_64 :
897 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
898 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
899 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
902 multiclass binary_atomic_op<SDNode atomic_op> {
903 def _8 : PatFrag<(ops node:$ptr, node:$val),
904 (atomic_op node:$ptr, node:$val), [{
905 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
907 def _16 : PatFrag<(ops node:$ptr, node:$val),
908 (atomic_op node:$ptr, node:$val), [{
909 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
911 def _32 : PatFrag<(ops node:$ptr, node:$val),
912 (atomic_op node:$ptr, node:$val), [{
913 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
915 def _64 : PatFrag<(ops node:$ptr, node:$val),
916 (atomic_op node:$ptr, node:$val), [{
917 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
921 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
922 defm atomic_swap : binary_atomic_op<atomic_swap>;
923 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
924 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
925 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
926 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
927 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
928 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
929 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
930 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
931 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
932 defm atomic_store : binary_atomic_op<atomic_store>;
935 PatFrag<(ops node:$ptr),
936 (atomic_load node:$ptr), [{
937 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
940 PatFrag<(ops node:$ptr),
941 (atomic_load node:$ptr), [{
942 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
945 PatFrag<(ops node:$ptr),
946 (atomic_load node:$ptr), [{
947 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
950 PatFrag<(ops node:$ptr),
951 (atomic_load node:$ptr), [{
952 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
955 //===----------------------------------------------------------------------===//
956 // Selection DAG CONVERT_RNDSAT patterns
958 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
959 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
960 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
963 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
964 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
965 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
968 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
969 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
970 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
973 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
974 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
975 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
978 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
979 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
980 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
983 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
984 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
985 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
988 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
989 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
990 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
993 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
994 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
995 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
998 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
999 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1000 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
1003 //===----------------------------------------------------------------------===//
1004 // Selection DAG Pattern Support.
1006 // Patterns are what are actually matched against by the target-flavored
1007 // instruction selection DAG. Instructions defined by the target implicitly
1008 // define patterns in most cases, but patterns can also be explicitly added when
1009 // an operation is defined by a sequence of instructions (e.g. loading a large
1010 // immediate value on RISC targets that do not support immediates as large as
1014 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
1015 dag PatternToMatch = patternToMatch;
1016 list<dag> ResultInstrs = resultInstrs;
1017 list<Predicate> Predicates = []; // See class Instruction in Target.td.
1018 int AddedComplexity = 0; // See class Instruction in Target.td.
1021 // Pat - A simple (but common) form of a pattern, which produces a simple result
1022 // not needing a full list.
1023 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
1025 //===----------------------------------------------------------------------===//
1026 // Complex pattern definitions.
1029 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
1030 // in C++. NumOperands is the number of operands returned by the select function;
1031 // SelectFunc is the name of the function used to pattern match the max. pattern;
1032 // RootNodes are the list of possible root nodes of the sub-dags to match.
1033 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
1035 class ComplexPattern<ValueType ty, int numops, string fn,
1036 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
1038 int NumOperands = numops;
1039 string SelectFunc = fn;
1040 list<SDNode> RootNodes = roots;
1041 list<SDNodeProperty> Properties = props;