1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand has floating-point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisVec - The specified operand has a vector type.
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
42 // SDTCisSameAs - The two specified operands have identical types.
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
44 int OtherOperandNum = OtherOp;
47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
48 // smaller than the 'Other' operand.
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
50 int OtherOperandNum = OtherOp;
53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
54 int BigOperandNum = BigOp;
57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
58 /// type as the element type of OtherOp, which is a vector type.
59 class SDTCisEltOfVec<int ThisOp, int OtherOp>
60 : SDTypeConstraint<ThisOp> {
61 int OtherOpNum = OtherOp;
64 //===----------------------------------------------------------------------===//
65 // Selection DAG Type Profile definitions.
67 // These use the constraints defined above to describe the type requirements of
68 // the various nodes. These are not hard coded into tblgen, allowing targets to
69 // add their own if needed.
72 // SDTypeProfile - This profile describes the type requirements of a Selection
74 class SDTypeProfile<int numresults, int numoperands,
75 list<SDTypeConstraint> constraints> {
76 int NumResults = numresults;
77 int NumOperands = numoperands;
78 list<SDTypeConstraint> Constraints = constraints;
82 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
83 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
84 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
85 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
86 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
87 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
89 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
90 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
92 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
93 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
95 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
99 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
100 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
102 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
103 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
105 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
106 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
108 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
109 SDTCisSameAs<0, 1>, SDTCisInt<0>
111 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
112 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
114 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
115 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
117 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
118 SDTCisSameAs<0, 1>, SDTCisFP<0>
120 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
121 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
123 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
124 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
126 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
127 SDTCisFP<0>, SDTCisInt<1>
129 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
130 SDTCisInt<0>, SDTCisFP<1>
132 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
133 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
134 SDTCisVTSmallerThanOp<2, 1>
137 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
138 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
141 def SDTSelect : SDTypeProfile<1, 3, [ // select
142 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
145 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
146 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
150 def SDTBr : SDTypeProfile<0, 1, [ // br
154 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
155 SDTCisInt<0>, SDTCisVT<1, OtherVT>
158 def SDTBrind : SDTypeProfile<0, 1, [ // brind
162 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
164 def SDTLoad : SDTypeProfile<1, 1, [ // load
168 def SDTStore : SDTypeProfile<0, 2, [ // store
172 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
173 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
176 def SDTVecShuffle : SDTypeProfile<1, 2, [
177 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
179 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
180 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
182 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
183 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
186 def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch
187 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
190 def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier
191 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
194 def STDAtomic3 : SDTypeProfile<1, 3, [
195 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
197 def STDAtomic2 : SDTypeProfile<1, 2, [
198 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
201 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
202 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
205 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
206 SDTypeProfile<0, 1, constraints>;
207 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
208 SDTypeProfile<0, 2, constraints>;
210 //===----------------------------------------------------------------------===//
211 // Selection DAG Node Properties.
213 // Note: These are hard coded into tblgen.
215 class SDNodeProperty;
216 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
217 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
218 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
219 def SDNPOutFlag : SDNodeProperty; // Write a flag result
220 def SDNPInFlag : SDNodeProperty; // Read a flag operand
221 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
222 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
223 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
224 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
225 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
226 def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
228 //===----------------------------------------------------------------------===//
229 // Selection DAG Node definitions.
231 class SDNode<string opcode, SDTypeProfile typeprof,
232 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
233 string Opcode = opcode;
234 string SDClass = sdclass;
235 list<SDNodeProperty> Properties = props;
236 SDTypeProfile TypeProfile = typeprof;
239 // Special TableGen-recognized dag nodes
245 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
246 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
247 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
248 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
249 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
250 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
251 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
252 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
253 "GlobalAddressSDNode">;
254 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
255 "GlobalAddressSDNode">;
256 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
257 "GlobalAddressSDNode">;
258 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
259 "GlobalAddressSDNode">;
260 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
261 "ConstantPoolSDNode">;
262 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
263 "ConstantPoolSDNode">;
264 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
266 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
268 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
270 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
272 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
273 "ExternalSymbolSDNode">;
274 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
275 "ExternalSymbolSDNode">;
276 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
277 "BlockAddressSDNode">;
278 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
279 "BlockAddressSDNode">;
281 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
282 [SDNPCommutative, SDNPAssociative]>;
283 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
284 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
285 [SDNPCommutative, SDNPAssociative]>;
286 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
287 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
288 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
289 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
290 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
291 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
292 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
293 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
294 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
295 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
296 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
297 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
298 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
299 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
300 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
301 def and : SDNode<"ISD::AND" , SDTIntBinOp,
302 [SDNPCommutative, SDNPAssociative]>;
303 def or : SDNode<"ISD::OR" , SDTIntBinOp,
304 [SDNPCommutative, SDNPAssociative]>;
305 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
306 [SDNPCommutative, SDNPAssociative]>;
307 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
308 [SDNPCommutative, SDNPOutFlag]>;
309 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
310 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
311 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
313 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
314 [SDNPOutFlag, SDNPInFlag]>;
316 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
317 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
318 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
319 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
320 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
321 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
322 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
323 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
324 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
325 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
326 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
327 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
330 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
331 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
332 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
333 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
334 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
335 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
336 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
337 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
338 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
339 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
340 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
341 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
342 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
343 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
344 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
345 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
346 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
348 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
349 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
350 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
352 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
353 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
354 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
355 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
356 def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>;
357 def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>;
359 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
360 def select : SDNode<"ISD::SELECT" , SDTSelect>;
361 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
362 def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
364 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
365 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
366 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
367 def trap : SDNode<"ISD::TRAP" , SDTNone,
368 [SDNPHasChain, SDNPSideEffect]>;
370 def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch,
371 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
373 def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
374 [SDNPHasChain, SDNPSideEffect]>;
376 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , STDAtomic3,
377 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
378 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , STDAtomic2,
379 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
380 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2,
381 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
382 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , STDAtomic2,
383 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
384 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2,
385 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
386 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2,
387 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
388 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2,
389 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
390 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", STDAtomic2,
391 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
392 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2,
393 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
394 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2,
395 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
396 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2,
397 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
398 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2,
399 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
401 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
402 // and truncst (see below).
403 def ld : SDNode<"ISD::LOAD" , SDTLoad,
404 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
405 def st : SDNode<"ISD::STORE" , SDTStore,
406 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
407 def ist : SDNode<"ISD::STORE" , SDTIStore,
408 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
410 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
411 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
412 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
414 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
415 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
416 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
417 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
419 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
420 // these internally. Don't reference these directly.
421 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
422 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
424 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
425 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
427 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
428 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
430 // Do not use cvt directly. Use cvt forms below
431 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
433 //===----------------------------------------------------------------------===//
434 // Selection DAG Condition Codes
436 class CondCode; // ISD::CondCode enums
437 def SETOEQ : CondCode; def SETOGT : CondCode;
438 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
439 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
440 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
441 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
443 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
444 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
447 //===----------------------------------------------------------------------===//
448 // Selection DAG Node Transformation Functions.
450 // This mechanism allows targets to manipulate nodes in the output DAG once a
451 // match has been formed. This is typically used to manipulate immediate
454 class SDNodeXForm<SDNode opc, code xformFunction> {
456 code XFormFunction = xformFunction;
459 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
462 //===----------------------------------------------------------------------===//
463 // Selection DAG Pattern Fragments.
465 // Pattern fragments are reusable chunks of dags that match specific things.
466 // They can take arguments and have C++ predicates that control whether they
467 // match. They are intended to make the patterns for common instructions more
468 // compact and readable.
471 /// PatFrag - Represents a pattern fragment. This can match something on the
472 /// DAG, frame a single node to multiply nested other fragments.
474 class PatFrag<dag ops, dag frag, code pred = [{}],
475 SDNodeXForm xform = NOOP_SDNodeXForm> {
478 code Predicate = pred;
479 SDNodeXForm OperandTransform = xform;
482 // PatLeaf's are pattern fragments that have no operands. This is just a helper
483 // to define immediates and other common things concisely.
484 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
485 : PatFrag<(ops), frag, pred, xform>;
489 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
490 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
492 def immAllOnesV: PatLeaf<(build_vector), [{
493 return ISD::isBuildVectorAllOnes(N);
495 def immAllZerosV: PatLeaf<(build_vector), [{
496 return ISD::isBuildVectorAllZeros(N);
501 // Other helper fragments.
502 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
503 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
504 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
507 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
508 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
510 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
511 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
514 // extending load fragments.
515 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
516 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
518 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
519 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
521 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
522 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
525 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
526 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
528 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
529 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
531 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
532 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
534 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
535 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
537 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
538 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
540 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
541 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
544 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
545 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
547 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
548 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
550 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
551 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
553 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
554 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
557 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
558 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
560 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
561 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
563 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
564 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
566 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
567 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
571 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
572 (st node:$val, node:$ptr), [{
573 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
575 def store : PatFrag<(ops node:$val, node:$ptr),
576 (unindexedstore node:$val, node:$ptr), [{
577 return !cast<StoreSDNode>(N)->isTruncatingStore();
580 // truncstore fragments.
581 def truncstore : PatFrag<(ops node:$val, node:$ptr),
582 (unindexedstore node:$val, node:$ptr), [{
583 return cast<StoreSDNode>(N)->isTruncatingStore();
585 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
586 (truncstore node:$val, node:$ptr), [{
587 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
589 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
590 (truncstore node:$val, node:$ptr), [{
591 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
593 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
594 (truncstore node:$val, node:$ptr), [{
595 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
597 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
598 (truncstore node:$val, node:$ptr), [{
599 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
601 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
602 (truncstore node:$val, node:$ptr), [{
603 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
606 // indexed store fragments.
607 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
608 (ist node:$val, node:$base, node:$offset), [{
609 return !cast<StoreSDNode>(N)->isTruncatingStore();
612 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
613 (istore node:$val, node:$base, node:$offset), [{
614 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
615 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
618 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
619 (ist node:$val, node:$base, node:$offset), [{
620 return cast<StoreSDNode>(N)->isTruncatingStore();
622 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
623 (itruncstore node:$val, node:$base, node:$offset), [{
624 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
625 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
627 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
628 (pre_truncst node:$val, node:$base, node:$offset), [{
629 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
631 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
632 (pre_truncst node:$val, node:$base, node:$offset), [{
633 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
635 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
636 (pre_truncst node:$val, node:$base, node:$offset), [{
637 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
639 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
640 (pre_truncst node:$val, node:$base, node:$offset), [{
641 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
643 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
644 (pre_truncst node:$val, node:$base, node:$offset), [{
645 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
648 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
649 (istore node:$val, node:$ptr, node:$offset), [{
650 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
651 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
654 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
655 (itruncstore node:$val, node:$base, node:$offset), [{
656 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
657 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
659 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
660 (post_truncst node:$val, node:$base, node:$offset), [{
661 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
663 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
664 (post_truncst node:$val, node:$base, node:$offset), [{
665 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
667 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
668 (post_truncst node:$val, node:$base, node:$offset), [{
669 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
671 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
672 (post_truncst node:$val, node:$base, node:$offset), [{
673 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
675 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
676 (post_truncst node:$val, node:$base, node:$offset), [{
677 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
680 // setcc convenience fragments.
681 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
682 (setcc node:$lhs, node:$rhs, SETOEQ)>;
683 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
684 (setcc node:$lhs, node:$rhs, SETOGT)>;
685 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
686 (setcc node:$lhs, node:$rhs, SETOGE)>;
687 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
688 (setcc node:$lhs, node:$rhs, SETOLT)>;
689 def setole : PatFrag<(ops node:$lhs, node:$rhs),
690 (setcc node:$lhs, node:$rhs, SETOLE)>;
691 def setone : PatFrag<(ops node:$lhs, node:$rhs),
692 (setcc node:$lhs, node:$rhs, SETONE)>;
693 def seto : PatFrag<(ops node:$lhs, node:$rhs),
694 (setcc node:$lhs, node:$rhs, SETO)>;
695 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
696 (setcc node:$lhs, node:$rhs, SETUO)>;
697 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
698 (setcc node:$lhs, node:$rhs, SETUEQ)>;
699 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
700 (setcc node:$lhs, node:$rhs, SETUGT)>;
701 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
702 (setcc node:$lhs, node:$rhs, SETUGE)>;
703 def setult : PatFrag<(ops node:$lhs, node:$rhs),
704 (setcc node:$lhs, node:$rhs, SETULT)>;
705 def setule : PatFrag<(ops node:$lhs, node:$rhs),
706 (setcc node:$lhs, node:$rhs, SETULE)>;
707 def setune : PatFrag<(ops node:$lhs, node:$rhs),
708 (setcc node:$lhs, node:$rhs, SETUNE)>;
709 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
710 (setcc node:$lhs, node:$rhs, SETEQ)>;
711 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
712 (setcc node:$lhs, node:$rhs, SETGT)>;
713 def setge : PatFrag<(ops node:$lhs, node:$rhs),
714 (setcc node:$lhs, node:$rhs, SETGE)>;
715 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
716 (setcc node:$lhs, node:$rhs, SETLT)>;
717 def setle : PatFrag<(ops node:$lhs, node:$rhs),
718 (setcc node:$lhs, node:$rhs, SETLE)>;
719 def setne : PatFrag<(ops node:$lhs, node:$rhs),
720 (setcc node:$lhs, node:$rhs, SETNE)>;
722 def atomic_cmp_swap_8 :
723 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
724 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
725 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
727 def atomic_cmp_swap_16 :
728 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
729 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
730 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
732 def atomic_cmp_swap_32 :
733 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
734 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
735 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
737 def atomic_cmp_swap_64 :
738 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
739 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
740 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
743 multiclass binary_atomic_op<SDNode atomic_op> {
744 def _8 : PatFrag<(ops node:$ptr, node:$val),
745 (atomic_op node:$ptr, node:$val), [{
746 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
748 def _16 : PatFrag<(ops node:$ptr, node:$val),
749 (atomic_op node:$ptr, node:$val), [{
750 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
752 def _32 : PatFrag<(ops node:$ptr, node:$val),
753 (atomic_op node:$ptr, node:$val), [{
754 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
756 def _64 : PatFrag<(ops node:$ptr, node:$val),
757 (atomic_op node:$ptr, node:$val), [{
758 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
762 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
763 defm atomic_swap : binary_atomic_op<atomic_swap>;
764 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
765 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
766 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
767 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
768 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
769 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
770 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
771 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
772 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
774 //===----------------------------------------------------------------------===//
775 // Selection DAG CONVERT_RNDSAT patterns
777 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
778 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
779 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
782 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
783 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
784 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
787 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
788 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
789 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
792 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
793 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
794 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
797 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
798 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
799 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
802 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
803 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
804 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
807 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
808 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
809 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
812 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
813 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
814 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
817 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
818 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
819 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
822 //===----------------------------------------------------------------------===//
823 // Selection DAG Pattern Support.
825 // Patterns are what are actually matched against the target-flavored
826 // instruction selection DAG. Instructions defined by the target implicitly
827 // define patterns in most cases, but patterns can also be explicitly added when
828 // an operation is defined by a sequence of instructions (e.g. loading a large
829 // immediate value on RISC targets that do not support immediates as large as
833 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
834 dag PatternToMatch = patternToMatch;
835 list<dag> ResultInstrs = resultInstrs;
836 list<Predicate> Predicates = []; // See class Instruction in Target.td.
837 int AddedComplexity = 0; // See class Instruction in Target.td.
840 // Pat - A simple (but common) form of a pattern, which produces a simple result
841 // not needing a full list.
842 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
844 //===----------------------------------------------------------------------===//
845 // Complex pattern definitions.
848 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
849 // in C++. NumOperands is the number of operands returned by the select function;
850 // SelectFunc is the name of the function used to pattern match the max. pattern;
851 // RootNodes are the list of possible root nodes of the sub-dags to match.
852 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
854 class ComplexPattern<ValueType ty, int numops, string fn,
855 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
857 int NumOperands = numops;
858 string SelectFunc = fn;
859 list<SDNode> RootNodes = roots;
860 list<SDNodeProperty> Properties = props;