1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand has floating-point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisVec - The specified operand has a vector type.
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
42 // SDTCisSameAs - The two specified operands have identical types.
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
44 int OtherOperandNum = OtherOp;
47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
48 // smaller than the 'Other' operand.
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
50 int OtherOperandNum = OtherOp;
53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
54 int BigOperandNum = BigOp;
57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
58 /// type as the element type of OtherOp, which is a vector type.
59 class SDTCisEltOfVec<int ThisOp, int OtherOp>
60 : SDTypeConstraint<ThisOp> {
61 int OtherOpNum = OtherOp;
64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
65 /// with length less that of OtherOp, which is a vector type.
66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
67 : SDTypeConstraint<ThisOp> {
68 int OtherOpNum = OtherOp;
71 //===----------------------------------------------------------------------===//
72 // Selection DAG Type Profile definitions.
74 // These use the constraints defined above to describe the type requirements of
75 // the various nodes. These are not hard coded into tblgen, allowing targets to
76 // add their own if needed.
79 // SDTypeProfile - This profile describes the type requirements of a Selection
81 class SDTypeProfile<int numresults, int numoperands,
82 list<SDTypeConstraint> constraints> {
83 int NumResults = numresults;
84 int NumOperands = numoperands;
85 list<SDTypeConstraint> Constraints = constraints;
89 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
90 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
91 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
92 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
93 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
94 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
96 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
97 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
99 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
100 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
102 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
103 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
106 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
107 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
109 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
110 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
112 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
113 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
115 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
116 SDTCisSameAs<0, 1>, SDTCisInt<0>
118 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
119 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
121 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
122 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
124 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
125 SDTCisSameAs<0, 1>, SDTCisFP<0>
127 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
128 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
130 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
131 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
133 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
134 SDTCisFP<0>, SDTCisInt<1>
136 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
137 SDTCisInt<0>, SDTCisFP<1>
139 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
140 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
141 SDTCisVTSmallerThanOp<2, 1>
144 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
145 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
148 def SDTSelect : SDTypeProfile<1, 3, [ // select
149 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
152 def SDTVSelect : SDTypeProfile<1, 3, [ // vselect
153 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
156 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
157 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
161 def SDTBr : SDTypeProfile<0, 1, [ // br
165 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
166 SDTCisInt<0>, SDTCisVT<1, OtherVT>
169 def SDTBrind : SDTypeProfile<0, 1, [ // brind
173 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
175 def SDTLoad : SDTypeProfile<1, 1, [ // load
179 def SDTStore : SDTypeProfile<0, 2, [ // store
183 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
184 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
187 def SDTVecShuffle : SDTypeProfile<1, 2, [
188 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
190 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
191 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
193 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
194 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
197 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
198 SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
200 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
201 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
204 def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch
205 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1>
208 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier
209 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
212 def SDTAtomicFence : SDTypeProfile<0, 2, [
213 SDTCisSameAs<0,1>, SDTCisPtrTy<0>
215 def SDTAtomic3 : SDTypeProfile<1, 3, [
216 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
218 def SDTAtomic2 : SDTypeProfile<1, 2, [
219 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
221 def SDTAtomicStore : SDTypeProfile<0, 2, [
222 SDTCisPtrTy<0>, SDTCisInt<1>
224 def SDTAtomicLoad : SDTypeProfile<1, 1, [
225 SDTCisInt<0>, SDTCisPtrTy<1>
228 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
229 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
232 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
233 SDTypeProfile<0, 1, constraints>;
234 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
235 SDTypeProfile<0, 2, constraints>;
237 //===----------------------------------------------------------------------===//
238 // Selection DAG Node Properties.
240 // Note: These are hard coded into tblgen.
242 class SDNodeProperty;
243 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
244 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
245 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
246 def SDNPOutGlue : SDNodeProperty; // Write a flag result
247 def SDNPInGlue : SDNodeProperty; // Read a flag operand
248 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand
249 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
250 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
251 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
252 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
253 def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
254 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match
255 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent
257 //===----------------------------------------------------------------------===//
258 // Selection DAG Pattern Operations
259 class SDPatternOperator;
261 //===----------------------------------------------------------------------===//
262 // Selection DAG Node definitions.
264 class SDNode<string opcode, SDTypeProfile typeprof,
265 list<SDNodeProperty> props = [], string sdclass = "SDNode">
266 : SDPatternOperator {
267 string Opcode = opcode;
268 string SDClass = sdclass;
269 list<SDNodeProperty> Properties = props;
270 SDTypeProfile TypeProfile = typeprof;
273 // Special TableGen-recognized dag nodes
279 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
280 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
281 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
282 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
283 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
284 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
285 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
286 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
287 "GlobalAddressSDNode">;
288 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
289 "GlobalAddressSDNode">;
290 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
291 "GlobalAddressSDNode">;
292 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
293 "GlobalAddressSDNode">;
294 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
295 "ConstantPoolSDNode">;
296 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
297 "ConstantPoolSDNode">;
298 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
300 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
302 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
304 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
306 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
307 "ExternalSymbolSDNode">;
308 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
309 "ExternalSymbolSDNode">;
310 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
311 "BlockAddressSDNode">;
312 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
313 "BlockAddressSDNode">;
315 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
316 [SDNPCommutative, SDNPAssociative]>;
317 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
318 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
319 [SDNPCommutative, SDNPAssociative]>;
320 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
321 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
322 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
323 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
324 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
325 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
326 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
327 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
328 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
329 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
330 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
331 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
332 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
333 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
334 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
335 def and : SDNode<"ISD::AND" , SDTIntBinOp,
336 [SDNPCommutative, SDNPAssociative]>;
337 def or : SDNode<"ISD::OR" , SDTIntBinOp,
338 [SDNPCommutative, SDNPAssociative]>;
339 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
340 [SDNPCommutative, SDNPAssociative]>;
341 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
342 [SDNPCommutative, SDNPOutGlue]>;
343 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
344 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>;
345 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
347 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
348 [SDNPOutGlue, SDNPInGlue]>;
350 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
351 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
352 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
353 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
354 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
355 def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>;
356 def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>;
357 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
358 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
359 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
360 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
361 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>;
362 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
363 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
366 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
367 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
368 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
369 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
370 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
371 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>;
372 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
373 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
374 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
375 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
376 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
377 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
378 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
379 def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
380 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
381 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
382 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
383 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
384 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
385 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
386 def frnd : SDNode<"ISD::FROUND" , SDTFPUnaryOp>;
388 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
389 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
390 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
392 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
393 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
394 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
395 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
396 def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>;
397 def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>;
399 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
400 def select : SDNode<"ISD::SELECT" , SDTSelect>;
401 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
402 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
404 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
405 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
406 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
407 def trap : SDNode<"ISD::TRAP" , SDTNone,
408 [SDNPHasChain, SDNPSideEffect]>;
409 def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone,
410 [SDNPHasChain, SDNPSideEffect]>;
412 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
413 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
416 def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf,
417 [SDNPHasChain, SDNPSideEffect]>;
419 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
420 [SDNPHasChain, SDNPSideEffect]>;
422 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
423 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
424 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2,
425 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
426 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2,
427 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
428 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2,
429 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
430 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2,
431 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
432 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2,
433 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
434 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2,
435 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
436 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2,
437 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
438 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2,
439 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
440 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2,
441 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
442 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2,
443 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
444 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
445 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
446 def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad,
447 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
448 def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
449 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
451 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
452 // and truncst (see below).
453 def ld : SDNode<"ISD::LOAD" , SDTLoad,
454 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
455 def st : SDNode<"ISD::STORE" , SDTStore,
456 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
457 def ist : SDNode<"ISD::STORE" , SDTIStore,
458 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
460 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
461 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
462 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
464 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
465 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
466 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
467 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
468 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
469 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<1, 2>]>,[]>;
471 // This operator does not do subvector type checking. The ARM
472 // backend, at least, needs it.
473 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
474 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
477 // This operator does subvector type checking.
478 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
479 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
481 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
482 // these internally. Don't reference these directly.
483 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
484 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
486 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
487 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
489 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
490 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
492 // Do not use cvt directly. Use cvt forms below
493 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
495 def SDT_assertext : SDTypeProfile<1, 1,
496 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
497 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
498 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
501 //===----------------------------------------------------------------------===//
502 // Selection DAG Condition Codes
504 class CondCode; // ISD::CondCode enums
505 def SETOEQ : CondCode; def SETOGT : CondCode;
506 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
507 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
508 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
509 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
511 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
512 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
515 //===----------------------------------------------------------------------===//
516 // Selection DAG Node Transformation Functions.
518 // This mechanism allows targets to manipulate nodes in the output DAG once a
519 // match has been formed. This is typically used to manipulate immediate
522 class SDNodeXForm<SDNode opc, code xformFunction> {
524 code XFormFunction = xformFunction;
527 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
529 //===----------------------------------------------------------------------===//
530 // PatPred Subclasses.
532 // These allow specifying different sorts of predicates that control whether a
537 class CodePatPred<code predicate> : PatPred {
538 code PredicateCode = predicate;
542 //===----------------------------------------------------------------------===//
543 // Selection DAG Pattern Fragments.
545 // Pattern fragments are reusable chunks of dags that match specific things.
546 // They can take arguments and have C++ predicates that control whether they
547 // match. They are intended to make the patterns for common instructions more
548 // compact and readable.
551 /// PatFrag - Represents a pattern fragment. This can match something on the
552 /// DAG, from a single node to multiple nested other fragments.
554 class PatFrag<dag ops, dag frag, code pred = [{}],
555 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator {
558 code PredicateCode = pred;
559 code ImmediateCode = [{}];
560 SDNodeXForm OperandTransform = xform;
563 // OutPatFrag is a pattern fragment that is used as part of an output pattern
564 // (not an input pattern). These do not have predicates or transforms, but are
565 // used to avoid repeated subexpressions in output patterns.
566 class OutPatFrag<dag ops, dag frag>
567 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>;
569 // PatLeaf's are pattern fragments that have no operands. This is just a helper
570 // to define immediates and other common things concisely.
571 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
572 : PatFrag<(ops), frag, pred, xform>;
575 // ImmLeaf is a pattern fragment with a constraint on the immediate. The
576 // constraint is a function that is run on the immediate (always with the value
577 // sign extended out to an int64_t) as Imm. For example:
579 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>;
581 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also
582 // is preferred over using PatLeaf because it allows the code generator to
583 // reason more about the constraint.
585 // If FastIsel should ignore all instructions that have an operand of this type,
586 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce
587 // the code size of the generated fast instruction selector.
588 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
589 : PatFrag<(ops), (vt imm), [{}], xform> {
590 let ImmediateCode = pred;
591 bit FastIselShouldIgnore = 0;
597 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
598 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
600 def immAllOnesV: PatLeaf<(build_vector), [{
601 return ISD::isBuildVectorAllOnes(N);
603 def immAllZerosV: PatLeaf<(build_vector), [{
604 return ISD::isBuildVectorAllZeros(N);
609 // Other helper fragments.
610 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
611 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
612 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
614 // null_frag - The null pattern operator is used in multiclass instantiations
615 // which accept an SDPatternOperator for use in matching patterns for internal
616 // definitions. When expanding a pattern, if the null fragment is referenced
617 // in the expansion, the pattern is discarded and it is as-if '[]' had been
618 // specified. This allows multiclasses to have the isel patterns be optional.
619 def null_frag : SDPatternOperator;
622 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
623 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
625 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
626 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
629 // extending load fragments.
630 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
631 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
633 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
634 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
636 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
637 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
640 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
641 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
643 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
644 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
646 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
647 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
649 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
650 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
652 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
653 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
655 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
656 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
659 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
660 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
662 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
663 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
665 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
666 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
668 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
669 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
672 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
673 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
675 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
676 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
678 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
679 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
681 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
682 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
685 def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
686 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
688 def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
689 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
691 def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
692 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
694 def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
695 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
697 def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
698 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f32;
700 def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
701 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f64;
704 def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
705 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
707 def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
708 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
710 def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
711 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
713 def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
714 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
717 def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
718 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
720 def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
721 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
723 def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
724 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
726 def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
727 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
731 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
732 (st node:$val, node:$ptr), [{
733 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
735 def store : PatFrag<(ops node:$val, node:$ptr),
736 (unindexedstore node:$val, node:$ptr), [{
737 return !cast<StoreSDNode>(N)->isTruncatingStore();
740 // truncstore fragments.
741 def truncstore : PatFrag<(ops node:$val, node:$ptr),
742 (unindexedstore node:$val, node:$ptr), [{
743 return cast<StoreSDNode>(N)->isTruncatingStore();
745 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
746 (truncstore node:$val, node:$ptr), [{
747 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
749 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
750 (truncstore node:$val, node:$ptr), [{
751 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
753 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
754 (truncstore node:$val, node:$ptr), [{
755 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
757 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
758 (truncstore node:$val, node:$ptr), [{
759 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
761 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
762 (truncstore node:$val, node:$ptr), [{
763 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
766 // indexed store fragments.
767 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
768 (ist node:$val, node:$base, node:$offset), [{
769 return !cast<StoreSDNode>(N)->isTruncatingStore();
772 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
773 (istore node:$val, node:$base, node:$offset), [{
774 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
775 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
778 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
779 (ist node:$val, node:$base, node:$offset), [{
780 return cast<StoreSDNode>(N)->isTruncatingStore();
782 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
783 (itruncstore node:$val, node:$base, node:$offset), [{
784 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
785 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
787 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
788 (pre_truncst node:$val, node:$base, node:$offset), [{
789 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
791 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
792 (pre_truncst node:$val, node:$base, node:$offset), [{
793 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
795 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
796 (pre_truncst node:$val, node:$base, node:$offset), [{
797 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
799 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
800 (pre_truncst node:$val, node:$base, node:$offset), [{
801 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
803 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
804 (pre_truncst node:$val, node:$base, node:$offset), [{
805 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
808 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
809 (istore node:$val, node:$ptr, node:$offset), [{
810 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
811 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
814 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
815 (itruncstore node:$val, node:$base, node:$offset), [{
816 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
817 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
819 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
820 (post_truncst node:$val, node:$base, node:$offset), [{
821 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
823 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
824 (post_truncst node:$val, node:$base, node:$offset), [{
825 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
827 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
828 (post_truncst node:$val, node:$base, node:$offset), [{
829 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
831 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
832 (post_truncst node:$val, node:$base, node:$offset), [{
833 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
835 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
836 (post_truncst node:$val, node:$base, node:$offset), [{
837 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
840 // setcc convenience fragments.
841 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
842 (setcc node:$lhs, node:$rhs, SETOEQ)>;
843 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
844 (setcc node:$lhs, node:$rhs, SETOGT)>;
845 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
846 (setcc node:$lhs, node:$rhs, SETOGE)>;
847 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
848 (setcc node:$lhs, node:$rhs, SETOLT)>;
849 def setole : PatFrag<(ops node:$lhs, node:$rhs),
850 (setcc node:$lhs, node:$rhs, SETOLE)>;
851 def setone : PatFrag<(ops node:$lhs, node:$rhs),
852 (setcc node:$lhs, node:$rhs, SETONE)>;
853 def seto : PatFrag<(ops node:$lhs, node:$rhs),
854 (setcc node:$lhs, node:$rhs, SETO)>;
855 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
856 (setcc node:$lhs, node:$rhs, SETUO)>;
857 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
858 (setcc node:$lhs, node:$rhs, SETUEQ)>;
859 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
860 (setcc node:$lhs, node:$rhs, SETUGT)>;
861 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
862 (setcc node:$lhs, node:$rhs, SETUGE)>;
863 def setult : PatFrag<(ops node:$lhs, node:$rhs),
864 (setcc node:$lhs, node:$rhs, SETULT)>;
865 def setule : PatFrag<(ops node:$lhs, node:$rhs),
866 (setcc node:$lhs, node:$rhs, SETULE)>;
867 def setune : PatFrag<(ops node:$lhs, node:$rhs),
868 (setcc node:$lhs, node:$rhs, SETUNE)>;
869 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
870 (setcc node:$lhs, node:$rhs, SETEQ)>;
871 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
872 (setcc node:$lhs, node:$rhs, SETGT)>;
873 def setge : PatFrag<(ops node:$lhs, node:$rhs),
874 (setcc node:$lhs, node:$rhs, SETGE)>;
875 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
876 (setcc node:$lhs, node:$rhs, SETLT)>;
877 def setle : PatFrag<(ops node:$lhs, node:$rhs),
878 (setcc node:$lhs, node:$rhs, SETLE)>;
879 def setne : PatFrag<(ops node:$lhs, node:$rhs),
880 (setcc node:$lhs, node:$rhs, SETNE)>;
882 def atomic_cmp_swap_8 :
883 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
884 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
885 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
887 def atomic_cmp_swap_16 :
888 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
889 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
890 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
892 def atomic_cmp_swap_32 :
893 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
894 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
895 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
897 def atomic_cmp_swap_64 :
898 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
899 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
900 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
903 multiclass binary_atomic_op<SDNode atomic_op> {
904 def _8 : PatFrag<(ops node:$ptr, node:$val),
905 (atomic_op node:$ptr, node:$val), [{
906 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
908 def _16 : PatFrag<(ops node:$ptr, node:$val),
909 (atomic_op node:$ptr, node:$val), [{
910 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
912 def _32 : PatFrag<(ops node:$ptr, node:$val),
913 (atomic_op node:$ptr, node:$val), [{
914 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
916 def _64 : PatFrag<(ops node:$ptr, node:$val),
917 (atomic_op node:$ptr, node:$val), [{
918 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
922 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
923 defm atomic_swap : binary_atomic_op<atomic_swap>;
924 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
925 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
926 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
927 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
928 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
929 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
930 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
931 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
932 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
933 defm atomic_store : binary_atomic_op<atomic_store>;
936 PatFrag<(ops node:$ptr),
937 (atomic_load node:$ptr), [{
938 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
941 PatFrag<(ops node:$ptr),
942 (atomic_load node:$ptr), [{
943 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
946 PatFrag<(ops node:$ptr),
947 (atomic_load node:$ptr), [{
948 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
951 PatFrag<(ops node:$ptr),
952 (atomic_load node:$ptr), [{
953 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
956 //===----------------------------------------------------------------------===//
957 // Selection DAG CONVERT_RNDSAT patterns
959 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
960 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
961 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
964 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
965 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
966 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
969 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
970 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
971 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
974 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
975 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
976 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
979 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
980 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
981 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
984 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
985 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
986 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
989 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
990 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
991 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
994 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
995 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
996 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
999 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1000 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1001 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
1004 //===----------------------------------------------------------------------===//
1005 // Selection DAG Pattern Support.
1007 // Patterns are what are actually matched against by the target-flavored
1008 // instruction selection DAG. Instructions defined by the target implicitly
1009 // define patterns in most cases, but patterns can also be explicitly added when
1010 // an operation is defined by a sequence of instructions (e.g. loading a large
1011 // immediate value on RISC targets that do not support immediates as large as
1015 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
1016 dag PatternToMatch = patternToMatch;
1017 list<dag> ResultInstrs = resultInstrs;
1018 list<Predicate> Predicates = []; // See class Instruction in Target.td.
1019 int AddedComplexity = 0; // See class Instruction in Target.td.
1022 // Pat - A simple (but common) form of a pattern, which produces a simple result
1023 // not needing a full list.
1024 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
1026 //===----------------------------------------------------------------------===//
1027 // Complex pattern definitions.
1030 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
1031 // in C++. NumOperands is the number of operands returned by the select function;
1032 // SelectFunc is the name of the function used to pattern match the max. pattern;
1033 // RootNodes are the list of possible root nodes of the sub-dags to match.
1034 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
1036 class ComplexPattern<ValueType ty, int numops, string fn,
1037 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
1039 int NumOperands = numops;
1040 string SelectFunc = fn;
1041 list<SDNode> RootNodes = roots;
1042 list<SDNodeProperty> Properties = props;