1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand has floating-point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisVec - The specified operand has a vector type.
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
42 // SDTCisSameAs - The two specified operands have identical types.
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
44 int OtherOperandNum = OtherOp;
47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
48 // smaller than the 'Other' operand.
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
50 int OtherOperandNum = OtherOp;
53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
54 int BigOperandNum = BigOp;
57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
58 /// type as the element type of OtherOp, which is a vector type.
59 class SDTCisEltOfVec<int ThisOp, int OtherOp>
60 : SDTypeConstraint<ThisOp> {
61 int OtherOpNum = OtherOp;
64 //===----------------------------------------------------------------------===//
65 // Selection DAG Type Profile definitions.
67 // These use the constraints defined above to describe the type requirements of
68 // the various nodes. These are not hard coded into tblgen, allowing targets to
69 // add their own if needed.
72 // SDTypeProfile - This profile describes the type requirements of a Selection
74 class SDTypeProfile<int numresults, int numoperands,
75 list<SDTypeConstraint> constraints> {
76 int NumResults = numresults;
77 int NumOperands = numoperands;
78 list<SDTypeConstraint> Constraints = constraints;
82 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
83 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
84 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
85 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
86 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
87 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
89 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
90 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
92 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
93 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
95 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
98 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
99 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
101 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
104 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
105 SDTCisSameAs<0, 1>, SDTCisInt<0>
107 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
108 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
110 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
111 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
113 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
114 SDTCisSameAs<0, 1>, SDTCisFP<0>
116 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
117 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
119 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
120 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
122 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
123 SDTCisFP<0>, SDTCisInt<1>
125 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
126 SDTCisInt<0>, SDTCisFP<1>
128 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
129 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
130 SDTCisVTSmallerThanOp<2, 1>
133 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
134 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
137 def SDTSelect : SDTypeProfile<1, 3, [ // select
138 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
141 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
142 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
146 def SDTBr : SDTypeProfile<0, 1, [ // br
150 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
151 SDTCisInt<0>, SDTCisVT<1, OtherVT>
154 def SDTBrind : SDTypeProfile<0, 1, [ // brind
158 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
160 def SDTLoad : SDTypeProfile<1, 1, [ // load
164 def SDTStore : SDTypeProfile<0, 2, [ // store
168 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
169 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
172 def SDTVecShuffle : SDTypeProfile<1, 2, [
173 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
175 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
176 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
178 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
179 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
182 def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch
183 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
186 def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier
187 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
190 def STDAtomic3 : SDTypeProfile<1, 3, [
191 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
193 def STDAtomic2 : SDTypeProfile<1, 2, [
194 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
197 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
198 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
201 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
202 SDTypeProfile<0, 1, constraints>;
203 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
204 SDTypeProfile<0, 2, constraints>;
206 //===----------------------------------------------------------------------===//
207 // Selection DAG Node Properties.
209 // Note: These are hard coded into tblgen.
211 class SDNodeProperty;
212 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
213 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
214 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
215 def SDNPOutFlag : SDNodeProperty; // Write a flag result
216 def SDNPInFlag : SDNodeProperty; // Read a flag operand
217 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
218 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
219 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
220 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
221 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
223 //===----------------------------------------------------------------------===//
224 // Selection DAG Node definitions.
226 class SDNode<string opcode, SDTypeProfile typeprof,
227 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
228 string Opcode = opcode;
229 string SDClass = sdclass;
230 list<SDNodeProperty> Properties = props;
231 SDTypeProfile TypeProfile = typeprof;
234 // Special TableGen-recognized dag nodes
241 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
242 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
243 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
244 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
245 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
246 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
247 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
248 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
249 "GlobalAddressSDNode">;
250 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
251 "GlobalAddressSDNode">;
252 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
253 "GlobalAddressSDNode">;
254 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
255 "GlobalAddressSDNode">;
256 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
257 "ConstantPoolSDNode">;
258 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
259 "ConstantPoolSDNode">;
260 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
262 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
264 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
266 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
268 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
269 "ExternalSymbolSDNode">;
270 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
271 "ExternalSymbolSDNode">;
273 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
274 [SDNPCommutative, SDNPAssociative]>;
275 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
276 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
277 [SDNPCommutative, SDNPAssociative]>;
278 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
279 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
280 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
281 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
282 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
283 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
284 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
285 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
286 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
287 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
288 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
289 def and : SDNode<"ISD::AND" , SDTIntBinOp,
290 [SDNPCommutative, SDNPAssociative]>;
291 def or : SDNode<"ISD::OR" , SDTIntBinOp,
292 [SDNPCommutative, SDNPAssociative]>;
293 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
294 [SDNPCommutative, SDNPAssociative]>;
295 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
296 [SDNPCommutative, SDNPOutFlag]>;
297 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
298 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
299 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
301 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
302 [SDNPOutFlag, SDNPInFlag]>;
304 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
305 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
306 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
307 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
308 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
309 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
310 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
311 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
312 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
313 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
314 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
315 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
318 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
319 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
320 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
321 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
322 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
323 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
324 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
325 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
326 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
327 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
328 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
329 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
330 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
331 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
332 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
334 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
335 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
336 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
338 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
339 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
340 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
341 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
343 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
344 def select : SDNode<"ISD::SELECT" , SDTSelect>;
345 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
346 def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
348 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
349 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
350 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
351 def trap : SDNode<"ISD::TRAP" , SDTNone,
352 [SDNPHasChain, SDNPSideEffect]>;
354 def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch,
355 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
357 def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
358 [SDNPHasChain, SDNPSideEffect]>;
360 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , STDAtomic3,
361 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
362 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , STDAtomic2,
363 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
364 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2,
365 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
366 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , STDAtomic2,
367 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
368 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2,
369 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
370 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2,
371 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
372 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2,
373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
374 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", STDAtomic2,
375 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
376 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2,
377 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
378 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2,
379 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
380 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2,
381 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
382 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2,
383 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
385 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
386 // and truncst (see below).
387 def ld : SDNode<"ISD::LOAD" , SDTLoad,
388 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
389 def st : SDNode<"ISD::STORE" , SDTStore,
390 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
391 def ist : SDNode<"ISD::STORE" , SDTIStore,
392 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
394 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
395 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
396 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
398 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
399 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
400 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
401 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
403 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
404 // these internally. Don't reference these directly.
405 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
406 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
408 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
409 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
411 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
412 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
414 // Do not use cvt directly. Use cvt forms below
415 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
417 //===----------------------------------------------------------------------===//
418 // Selection DAG Condition Codes
420 class CondCode; // ISD::CondCode enums
421 def SETOEQ : CondCode; def SETOGT : CondCode;
422 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
423 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
424 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
425 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
427 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
428 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
431 //===----------------------------------------------------------------------===//
432 // Selection DAG Node Transformation Functions.
434 // This mechanism allows targets to manipulate nodes in the output DAG once a
435 // match has been formed. This is typically used to manipulate immediate
438 class SDNodeXForm<SDNode opc, code xformFunction> {
440 code XFormFunction = xformFunction;
443 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
446 //===----------------------------------------------------------------------===//
447 // Selection DAG Pattern Fragments.
449 // Pattern fragments are reusable chunks of dags that match specific things.
450 // They can take arguments and have C++ predicates that control whether they
451 // match. They are intended to make the patterns for common instructions more
452 // compact and readable.
455 /// PatFrag - Represents a pattern fragment. This can match something on the
456 /// DAG, frame a single node to multiply nested other fragments.
458 class PatFrag<dag ops, dag frag, code pred = [{}],
459 SDNodeXForm xform = NOOP_SDNodeXForm> {
462 code Predicate = pred;
463 SDNodeXForm OperandTransform = xform;
466 // PatLeaf's are pattern fragments that have no operands. This is just a helper
467 // to define immediates and other common things concisely.
468 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
469 : PatFrag<(ops), frag, pred, xform>;
473 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
474 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
476 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
477 def immAllOnesV: PatLeaf<(build_vector), [{
478 return ISD::isBuildVectorAllOnes(N);
480 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
481 return ISD::isBuildVectorAllOnes(N);
483 def immAllZerosV: PatLeaf<(build_vector), [{
484 return ISD::isBuildVectorAllZeros(N);
486 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
487 return ISD::isBuildVectorAllZeros(N);
492 // Other helper fragments.
493 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
494 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
495 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
496 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
499 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
500 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
502 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
503 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
506 // extending load fragments.
507 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
508 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
510 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
511 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
513 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
514 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
517 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
518 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
520 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
521 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
523 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
524 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
526 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
527 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
529 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
530 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
532 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
533 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
536 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
537 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
539 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
540 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
542 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
543 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
545 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
546 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
549 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
550 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
552 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
553 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
555 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
556 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
558 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
559 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
563 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
564 (st node:$val, node:$ptr), [{
565 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
567 def store : PatFrag<(ops node:$val, node:$ptr),
568 (unindexedstore node:$val, node:$ptr), [{
569 return !cast<StoreSDNode>(N)->isTruncatingStore();
572 // truncstore fragments.
573 def truncstore : PatFrag<(ops node:$val, node:$ptr),
574 (unindexedstore node:$val, node:$ptr), [{
575 return cast<StoreSDNode>(N)->isTruncatingStore();
577 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
578 (truncstore node:$val, node:$ptr), [{
579 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
581 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
582 (truncstore node:$val, node:$ptr), [{
583 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
585 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
586 (truncstore node:$val, node:$ptr), [{
587 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
589 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
590 (truncstore node:$val, node:$ptr), [{
591 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
593 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
594 (truncstore node:$val, node:$ptr), [{
595 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
598 // indexed store fragments.
599 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
600 (ist node:$val, node:$base, node:$offset), [{
601 return !cast<StoreSDNode>(N)->isTruncatingStore();
604 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
605 (istore node:$val, node:$base, node:$offset), [{
606 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
607 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
610 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
611 (ist node:$val, node:$base, node:$offset), [{
612 return cast<StoreSDNode>(N)->isTruncatingStore();
614 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
615 (itruncstore node:$val, node:$base, node:$offset), [{
616 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
617 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
619 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
620 (pre_truncst node:$val, node:$base, node:$offset), [{
621 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
623 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
624 (pre_truncst node:$val, node:$base, node:$offset), [{
625 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
627 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
628 (pre_truncst node:$val, node:$base, node:$offset), [{
629 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
631 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
632 (pre_truncst node:$val, node:$base, node:$offset), [{
633 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
635 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
636 (pre_truncst node:$val, node:$base, node:$offset), [{
637 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
640 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
641 (istore node:$val, node:$ptr, node:$offset), [{
642 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
643 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
646 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
647 (itruncstore node:$val, node:$base, node:$offset), [{
648 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
649 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
651 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
652 (post_truncst node:$val, node:$base, node:$offset), [{
653 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
655 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
656 (post_truncst node:$val, node:$base, node:$offset), [{
657 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
659 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
660 (post_truncst node:$val, node:$base, node:$offset), [{
661 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
663 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
664 (post_truncst node:$val, node:$base, node:$offset), [{
665 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
667 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
668 (post_truncst node:$val, node:$base, node:$offset), [{
669 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
672 // setcc convenience fragments.
673 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
674 (setcc node:$lhs, node:$rhs, SETOEQ)>;
675 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
676 (setcc node:$lhs, node:$rhs, SETOGT)>;
677 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
678 (setcc node:$lhs, node:$rhs, SETOGE)>;
679 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
680 (setcc node:$lhs, node:$rhs, SETOLT)>;
681 def setole : PatFrag<(ops node:$lhs, node:$rhs),
682 (setcc node:$lhs, node:$rhs, SETOLE)>;
683 def setone : PatFrag<(ops node:$lhs, node:$rhs),
684 (setcc node:$lhs, node:$rhs, SETONE)>;
685 def seto : PatFrag<(ops node:$lhs, node:$rhs),
686 (setcc node:$lhs, node:$rhs, SETO)>;
687 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
688 (setcc node:$lhs, node:$rhs, SETUO)>;
689 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
690 (setcc node:$lhs, node:$rhs, SETUEQ)>;
691 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
692 (setcc node:$lhs, node:$rhs, SETUGT)>;
693 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
694 (setcc node:$lhs, node:$rhs, SETUGE)>;
695 def setult : PatFrag<(ops node:$lhs, node:$rhs),
696 (setcc node:$lhs, node:$rhs, SETULT)>;
697 def setule : PatFrag<(ops node:$lhs, node:$rhs),
698 (setcc node:$lhs, node:$rhs, SETULE)>;
699 def setune : PatFrag<(ops node:$lhs, node:$rhs),
700 (setcc node:$lhs, node:$rhs, SETUNE)>;
701 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
702 (setcc node:$lhs, node:$rhs, SETEQ)>;
703 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
704 (setcc node:$lhs, node:$rhs, SETGT)>;
705 def setge : PatFrag<(ops node:$lhs, node:$rhs),
706 (setcc node:$lhs, node:$rhs, SETGE)>;
707 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
708 (setcc node:$lhs, node:$rhs, SETLT)>;
709 def setle : PatFrag<(ops node:$lhs, node:$rhs),
710 (setcc node:$lhs, node:$rhs, SETLE)>;
711 def setne : PatFrag<(ops node:$lhs, node:$rhs),
712 (setcc node:$lhs, node:$rhs, SETNE)>;
714 def atomic_cmp_swap_8 :
715 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
716 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
717 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
719 def atomic_cmp_swap_16 :
720 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
721 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
722 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
724 def atomic_cmp_swap_32 :
725 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
726 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
727 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
729 def atomic_cmp_swap_64 :
730 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
731 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
732 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
735 multiclass binary_atomic_op<SDNode atomic_op> {
736 def _8 : PatFrag<(ops node:$ptr, node:$val),
737 (atomic_op node:$ptr, node:$val), [{
738 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
740 def _16 : PatFrag<(ops node:$ptr, node:$val),
741 (atomic_op node:$ptr, node:$val), [{
742 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
744 def _32 : PatFrag<(ops node:$ptr, node:$val),
745 (atomic_op node:$ptr, node:$val), [{
746 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
748 def _64 : PatFrag<(ops node:$ptr, node:$val),
749 (atomic_op node:$ptr, node:$val), [{
750 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
754 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
755 defm atomic_swap : binary_atomic_op<atomic_swap>;
756 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
757 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
758 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
759 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
760 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
761 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
762 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
763 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
764 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
766 //===----------------------------------------------------------------------===//
767 // Selection DAG CONVERT_RNDSAT patterns
769 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
770 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
771 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
774 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
775 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
776 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
779 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
780 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
781 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
784 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
785 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
786 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
789 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
790 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
791 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
794 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
795 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
796 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
799 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
800 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
801 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
804 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
805 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
806 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
809 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
810 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
811 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
814 //===----------------------------------------------------------------------===//
815 // Selection DAG Pattern Support.
817 // Patterns are what are actually matched against the target-flavored
818 // instruction selection DAG. Instructions defined by the target implicitly
819 // define patterns in most cases, but patterns can also be explicitly added when
820 // an operation is defined by a sequence of instructions (e.g. loading a large
821 // immediate value on RISC targets that do not support immediates as large as
825 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
826 dag PatternToMatch = patternToMatch;
827 list<dag> ResultInstrs = resultInstrs;
828 list<Predicate> Predicates = []; // See class Instruction in Target.td.
829 int AddedComplexity = 0; // See class Instruction in Target.td.
832 // Pat - A simple (but common) form of a pattern, which produces a simple result
833 // not needing a full list.
834 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
836 //===----------------------------------------------------------------------===//
837 // Complex pattern definitions.
841 // Pass the parent Operand as root to CP function rather
842 // than the root of the sub-DAG
843 def CPAttrParentAsRoot : CPAttribute;
845 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
846 // in C++. NumOperands is the number of operands returned by the select function;
847 // SelectFunc is the name of the function used to pattern match the max. pattern;
848 // RootNodes are the list of possible root nodes of the sub-dags to match.
849 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
851 class ComplexPattern<ValueType ty, int numops, string fn,
852 list<SDNode> roots = [], list<SDNodeProperty> props = [],
853 list<CPAttribute> attrs = []> {
855 int NumOperands = numops;
856 string SelectFunc = fn;
857 list<SDNode> RootNodes = roots;
858 list<SDNodeProperty> Properties = props;
859 list<CPAttribute> Attributes = attrs;
862 //===----------------------------------------------------------------------===//
865 def SDT_dwarf_loc : SDTypeProfile<0, 3,
866 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
867 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;