1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand has floating-point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisVec - The specified operand has a vector type.
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
42 // SDTCisSameAs - The two specified operands have identical types.
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
44 int OtherOperandNum = OtherOp;
47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
48 // smaller than the 'Other' operand.
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
50 int OtherOperandNum = OtherOp;
53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
54 int BigOperandNum = BigOp;
57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
58 /// type as the element type of OtherOp, which is a vector type.
59 class SDTCisEltOfVec<int ThisOp, int OtherOp>
60 : SDTypeConstraint<ThisOp> {
61 int OtherOpNum = OtherOp;
64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
65 /// with length less that of OtherOp, which is a vector type.
66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
67 : SDTypeConstraint<ThisOp> {
68 int OtherOpNum = OtherOp;
71 // SDTCVecEltisVT - The specified operand is vector type with element type
73 class SDTCVecEltisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
77 // SDTCisSameNumEltsAs - The two specified operands have identical number
79 class SDTCisSameNumEltsAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
80 int OtherOperandNum = OtherOp;
83 // SDTCisSameSizeAs - The two specified operands have identical size.
84 class SDTCisSameSizeAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
85 int OtherOperandNum = OtherOp;
88 //===----------------------------------------------------------------------===//
89 // Selection DAG Type Profile definitions.
91 // These use the constraints defined above to describe the type requirements of
92 // the various nodes. These are not hard coded into tblgen, allowing targets to
93 // add their own if needed.
96 // SDTypeProfile - This profile describes the type requirements of a Selection
98 class SDTypeProfile<int numresults, int numoperands,
99 list<SDTypeConstraint> constraints> {
100 int NumResults = numresults;
101 int NumOperands = numoperands;
102 list<SDTypeConstraint> Constraints = constraints;
106 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
107 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
108 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
109 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
110 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
111 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
113 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
114 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
116 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
117 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
119 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
120 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
123 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
124 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
126 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
127 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
129 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
130 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
132 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
133 SDTCisSameAs<0, 1>, SDTCisInt<0>
135 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
136 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
138 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
139 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
141 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
142 SDTCisSameAs<0, 1>, SDTCisFP<0>
144 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
145 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
147 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
148 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
150 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
151 SDTCisFP<0>, SDTCisInt<1>
153 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
154 SDTCisInt<0>, SDTCisFP<1>
156 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
157 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
158 SDTCisVTSmallerThanOp<2, 1>
161 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
162 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
165 def SDTSelect : SDTypeProfile<1, 3, [ // select
166 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
169 def SDTVSelect : SDTypeProfile<1, 3, [ // vselect
170 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
173 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
174 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
178 def SDTBr : SDTypeProfile<0, 1, [ // br
182 def SDTBrCC : SDTypeProfile<0, 4, [ // brcc
183 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
186 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
187 SDTCisInt<0>, SDTCisVT<1, OtherVT>
190 def SDTBrind : SDTypeProfile<0, 1, [ // brind
194 def SDTCatchret : SDTypeProfile<0, 2, [ // catchret
195 SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>
198 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
200 def SDTLoad : SDTypeProfile<1, 1, [ // load
204 def SDTStore : SDTypeProfile<0, 2, [ // store
208 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
209 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
212 def SDTMaskedStore: SDTypeProfile<0, 3, [ // masked store
213 SDTCisPtrTy<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<1, 2>
216 def SDTMaskedLoad: SDTypeProfile<1, 3, [ // masked load
217 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>,
218 SDTCisSameNumEltsAs<0, 2>
221 def SDTMaskedGather: SDTypeProfile<2, 3, [ // masked gather
222 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>,
223 SDTCisPtrTy<4>, SDTCVecEltisVT<1, i1>, SDTCisSameNumEltsAs<0, 1>
226 def SDTMaskedScatter: SDTypeProfile<1, 3, [ // masked scatter
227 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameNumEltsAs<0, 1>,
228 SDTCVecEltisVT<0, i1>, SDTCisPtrTy<3>
231 def SDTVecShuffle : SDTypeProfile<1, 2, [
232 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
234 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
235 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
237 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
238 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
241 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
242 SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
244 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
245 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
248 def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch
249 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1>
252 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier
253 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
256 def SDTAtomicFence : SDTypeProfile<0, 2, [
257 SDTCisSameAs<0,1>, SDTCisPtrTy<0>
259 def SDTAtomic3 : SDTypeProfile<1, 3, [
260 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
262 def SDTAtomic2 : SDTypeProfile<1, 2, [
263 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
265 def SDTAtomicStore : SDTypeProfile<0, 2, [
266 SDTCisPtrTy<0>, SDTCisInt<1>
268 def SDTAtomicLoad : SDTypeProfile<1, 1, [
269 SDTCisInt<0>, SDTCisPtrTy<1>
272 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
273 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
276 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
277 SDTypeProfile<0, 1, constraints>;
278 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
279 SDTypeProfile<0, 2, constraints>;
281 //===----------------------------------------------------------------------===//
282 // Selection DAG Node Properties.
284 // Note: These are hard coded into tblgen.
286 class SDNodeProperty;
287 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
288 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
289 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
290 def SDNPOutGlue : SDNodeProperty; // Write a flag result
291 def SDNPInGlue : SDNodeProperty; // Read a flag operand
292 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand
293 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
294 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
295 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
296 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
297 def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
298 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match
299 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent
301 //===----------------------------------------------------------------------===//
302 // Selection DAG Pattern Operations
303 class SDPatternOperator;
305 //===----------------------------------------------------------------------===//
306 // Selection DAG Node definitions.
308 class SDNode<string opcode, SDTypeProfile typeprof,
309 list<SDNodeProperty> props = [], string sdclass = "SDNode">
310 : SDPatternOperator {
311 string Opcode = opcode;
312 string SDClass = sdclass;
313 list<SDNodeProperty> Properties = props;
314 SDTypeProfile TypeProfile = typeprof;
317 // Special TableGen-recognized dag nodes
323 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
324 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
325 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
326 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
327 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
328 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
329 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
330 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
331 "GlobalAddressSDNode">;
332 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
333 "GlobalAddressSDNode">;
334 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
335 "GlobalAddressSDNode">;
336 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
337 "GlobalAddressSDNode">;
338 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
339 "ConstantPoolSDNode">;
340 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
341 "ConstantPoolSDNode">;
342 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
344 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
346 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
348 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
350 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
351 "ExternalSymbolSDNode">;
352 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
353 "ExternalSymbolSDNode">;
354 def mcsym: SDNode<"ISD::MCSymbol", SDTPtrLeaf, [], "MCSymbolSDNode">;
355 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
356 "BlockAddressSDNode">;
357 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
358 "BlockAddressSDNode">;
360 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
361 [SDNPCommutative, SDNPAssociative]>;
362 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
363 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
364 [SDNPCommutative, SDNPAssociative]>;
365 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
366 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
367 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
368 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
369 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
370 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
371 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
372 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
373 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
374 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
375 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
376 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
377 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
378 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
379 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
380 def and : SDNode<"ISD::AND" , SDTIntBinOp,
381 [SDNPCommutative, SDNPAssociative]>;
382 def or : SDNode<"ISD::OR" , SDTIntBinOp,
383 [SDNPCommutative, SDNPAssociative]>;
384 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
385 [SDNPCommutative, SDNPAssociative]>;
386 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
387 [SDNPCommutative, SDNPOutGlue]>;
388 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
389 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>;
390 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
392 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
393 [SDNPOutGlue, SDNPInGlue]>;
394 def smin : SDNode<"ISD::SMIN" , SDTIntBinOp>;
395 def smax : SDNode<"ISD::SMAX" , SDTIntBinOp>;
396 def umin : SDNode<"ISD::UMIN" , SDTIntBinOp>;
397 def umax : SDNode<"ISD::UMAX" , SDTIntBinOp>;
399 def sabsdiff : SDNode<"ISD::SABSDIFF" , SDTIntBinOp>;
400 def uabsdiff : SDNode<"ISD::UABSDIFF" , SDTIntBinOp>;
401 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
402 def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>;
403 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
404 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
405 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
406 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
407 def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>;
408 def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>;
409 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
410 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
411 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
412 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
413 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>;
414 def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>;
415 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
416 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
418 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
419 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
420 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
421 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
422 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
423 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>;
424 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>;
425 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
426 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp>;
427 def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp>;
428 def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>;
429 def fmaxnan : SDNode<"ISD::FMAXNAN" , SDTFPBinOp>;
430 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
431 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
432 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
433 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
434 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
435 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
436 def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
437 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
438 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
439 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
440 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
441 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
442 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
443 def frnd : SDNode<"ISD::FROUND" , SDTFPUnaryOp>;
445 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
446 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
447 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
449 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
450 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
451 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
452 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
453 def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>;
454 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
456 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
457 def select : SDNode<"ISD::SELECT" , SDTSelect>;
458 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
459 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
461 def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>;
462 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
463 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
464 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
465 def catchret : SDNode<"ISD::CATCHRET" , SDTCatchret,
466 [SDNPHasChain, SDNPSideEffect]>;
467 def cleanupret : SDNode<"ISD::CLEANUPRET" , SDTNone, [SDNPHasChain]>;
468 def catchpad : SDNode<"ISD::CATCHPAD" , SDTNone,
469 [SDNPHasChain, SDNPSideEffect]>;
471 def trap : SDNode<"ISD::TRAP" , SDTNone,
472 [SDNPHasChain, SDNPSideEffect]>;
473 def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone,
474 [SDNPHasChain, SDNPSideEffect]>;
476 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
477 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
480 def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf,
481 [SDNPHasChain, SDNPSideEffect]>;
483 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
484 [SDNPHasChain, SDNPSideEffect]>;
486 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
487 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
488 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2,
489 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
490 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2,
491 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
492 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2,
493 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
494 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2,
495 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
496 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2,
497 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
498 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2,
499 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
500 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2,
501 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
502 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2,
503 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
504 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2,
505 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
506 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2,
507 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
508 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
509 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
510 def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad,
511 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
512 def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
513 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
515 def masked_store : SDNode<"ISD::MSTORE", SDTMaskedStore,
516 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
517 def masked_load : SDNode<"ISD::MLOAD", SDTMaskedLoad,
518 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
519 def masked_scatter : SDNode<"ISD::MSCATTER", SDTMaskedScatter,
520 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
521 def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather,
522 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
524 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
525 // and truncst (see below).
526 def ld : SDNode<"ISD::LOAD" , SDTLoad,
527 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
528 def st : SDNode<"ISD::STORE" , SDTStore,
529 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
530 def ist : SDNode<"ISD::STORE" , SDTIStore,
531 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
533 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
534 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
535 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
537 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
538 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
539 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
540 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
541 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
542 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>;
544 // This operator does not do subvector type checking. The ARM
545 // backend, at least, needs it.
546 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
547 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
550 // This operator does subvector type checking.
551 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
552 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
554 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
555 // these internally. Don't reference these directly.
556 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
557 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
559 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
560 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
562 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
563 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
565 // Do not use cvt directly. Use cvt forms below
566 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
568 def SDT_assertext : SDTypeProfile<1, 1,
569 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
570 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
571 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
574 //===----------------------------------------------------------------------===//
575 // Selection DAG Condition Codes
577 class CondCode; // ISD::CondCode enums
578 def SETOEQ : CondCode; def SETOGT : CondCode;
579 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
580 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
581 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
582 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
584 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
585 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
588 //===----------------------------------------------------------------------===//
589 // Selection DAG Node Transformation Functions.
591 // This mechanism allows targets to manipulate nodes in the output DAG once a
592 // match has been formed. This is typically used to manipulate immediate
595 class SDNodeXForm<SDNode opc, code xformFunction> {
597 code XFormFunction = xformFunction;
600 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
602 //===----------------------------------------------------------------------===//
603 // PatPred Subclasses.
605 // These allow specifying different sorts of predicates that control whether a
610 class CodePatPred<code predicate> : PatPred {
611 code PredicateCode = predicate;
615 //===----------------------------------------------------------------------===//
616 // Selection DAG Pattern Fragments.
618 // Pattern fragments are reusable chunks of dags that match specific things.
619 // They can take arguments and have C++ predicates that control whether they
620 // match. They are intended to make the patterns for common instructions more
621 // compact and readable.
624 /// PatFrag - Represents a pattern fragment. This can match something on the
625 /// DAG, from a single node to multiple nested other fragments.
627 class PatFrag<dag ops, dag frag, code pred = [{}],
628 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator {
631 code PredicateCode = pred;
632 code ImmediateCode = [{}];
633 SDNodeXForm OperandTransform = xform;
636 // OutPatFrag is a pattern fragment that is used as part of an output pattern
637 // (not an input pattern). These do not have predicates or transforms, but are
638 // used to avoid repeated subexpressions in output patterns.
639 class OutPatFrag<dag ops, dag frag>
640 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>;
642 // PatLeaf's are pattern fragments that have no operands. This is just a helper
643 // to define immediates and other common things concisely.
644 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
645 : PatFrag<(ops), frag, pred, xform>;
648 // ImmLeaf is a pattern fragment with a constraint on the immediate. The
649 // constraint is a function that is run on the immediate (always with the value
650 // sign extended out to an int64_t) as Imm. For example:
652 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>;
654 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also
655 // is preferred over using PatLeaf because it allows the code generator to
656 // reason more about the constraint.
658 // If FastIsel should ignore all instructions that have an operand of this type,
659 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce
660 // the code size of the generated fast instruction selector.
661 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
662 : PatFrag<(ops), (vt imm), [{}], xform> {
663 let ImmediateCode = pred;
664 bit FastIselShouldIgnore = 0;
670 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
671 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
673 def immAllOnesV: PatLeaf<(build_vector), [{
674 return ISD::isBuildVectorAllOnes(N);
676 def immAllZerosV: PatLeaf<(build_vector), [{
677 return ISD::isBuildVectorAllZeros(N);
682 // Other helper fragments.
683 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
684 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
685 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
687 // null_frag - The null pattern operator is used in multiclass instantiations
688 // which accept an SDPatternOperator for use in matching patterns for internal
689 // definitions. When expanding a pattern, if the null fragment is referenced
690 // in the expansion, the pattern is discarded and it is as-if '[]' had been
691 // specified. This allows multiclasses to have the isel patterns be optional.
692 def null_frag : SDPatternOperator;
695 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
696 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
698 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
699 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
702 // extending load fragments.
703 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
704 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
706 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
707 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
709 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
710 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
713 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
714 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
716 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
717 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
719 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
720 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
722 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
723 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
725 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
726 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
728 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
729 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
732 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
733 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
735 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
736 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
738 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
739 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
741 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
742 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
745 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
746 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
748 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
749 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
751 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
752 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
754 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
755 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
758 def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
759 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
761 def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
762 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
764 def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
765 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
767 def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
768 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
770 def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
771 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f32;
773 def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
774 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f64;
777 def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
778 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
780 def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
781 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
783 def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
784 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
786 def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
787 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
790 def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
791 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
793 def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
794 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
796 def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
797 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
799 def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
800 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
804 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
805 (st node:$val, node:$ptr), [{
806 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
808 def store : PatFrag<(ops node:$val, node:$ptr),
809 (unindexedstore node:$val, node:$ptr), [{
810 return !cast<StoreSDNode>(N)->isTruncatingStore();
813 // truncstore fragments.
814 def truncstore : PatFrag<(ops node:$val, node:$ptr),
815 (unindexedstore node:$val, node:$ptr), [{
816 return cast<StoreSDNode>(N)->isTruncatingStore();
818 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
819 (truncstore node:$val, node:$ptr), [{
820 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
822 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
823 (truncstore node:$val, node:$ptr), [{
824 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
826 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
827 (truncstore node:$val, node:$ptr), [{
828 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
830 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
831 (truncstore node:$val, node:$ptr), [{
832 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
834 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
835 (truncstore node:$val, node:$ptr), [{
836 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
839 def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr),
840 (truncstore node:$val, node:$ptr), [{
841 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
844 def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr),
845 (truncstore node:$val, node:$ptr), [{
846 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
849 def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr),
850 (truncstore node:$val, node:$ptr), [{
851 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
854 // indexed store fragments.
855 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
856 (ist node:$val, node:$base, node:$offset), [{
857 return !cast<StoreSDNode>(N)->isTruncatingStore();
860 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
861 (istore node:$val, node:$base, node:$offset), [{
862 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
863 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
866 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
867 (ist node:$val, node:$base, node:$offset), [{
868 return cast<StoreSDNode>(N)->isTruncatingStore();
870 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
871 (itruncstore node:$val, node:$base, node:$offset), [{
872 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
873 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
875 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
876 (pre_truncst node:$val, node:$base, node:$offset), [{
877 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
879 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
880 (pre_truncst node:$val, node:$base, node:$offset), [{
881 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
883 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
884 (pre_truncst node:$val, node:$base, node:$offset), [{
885 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
887 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
888 (pre_truncst node:$val, node:$base, node:$offset), [{
889 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
891 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
892 (pre_truncst node:$val, node:$base, node:$offset), [{
893 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
896 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
897 (istore node:$val, node:$ptr, node:$offset), [{
898 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
899 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
902 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
903 (itruncstore node:$val, node:$base, node:$offset), [{
904 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
905 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
907 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
908 (post_truncst node:$val, node:$base, node:$offset), [{
909 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
911 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
912 (post_truncst node:$val, node:$base, node:$offset), [{
913 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
915 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
916 (post_truncst node:$val, node:$base, node:$offset), [{
917 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
919 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
920 (post_truncst node:$val, node:$base, node:$offset), [{
921 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
923 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
924 (post_truncst node:$val, node:$base, node:$offset), [{
925 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
928 // nontemporal store fragments.
929 def nontemporalstore : PatFrag<(ops node:$val, node:$ptr),
930 (store node:$val, node:$ptr), [{
931 return cast<StoreSDNode>(N)->isNonTemporal();
934 def alignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
935 (nontemporalstore node:$val, node:$ptr), [{
936 StoreSDNode *St = cast<StoreSDNode>(N);
937 return St->getAlignment() >= St->getMemoryVT().getStoreSize();
940 def unalignednontemporalstore : PatFrag<(ops node:$val, node:$ptr),
941 (nontemporalstore node:$val, node:$ptr), [{
942 StoreSDNode *St = cast<StoreSDNode>(N);
943 return St->getAlignment() < St->getMemoryVT().getStoreSize();
946 // setcc convenience fragments.
947 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
948 (setcc node:$lhs, node:$rhs, SETOEQ)>;
949 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
950 (setcc node:$lhs, node:$rhs, SETOGT)>;
951 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
952 (setcc node:$lhs, node:$rhs, SETOGE)>;
953 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
954 (setcc node:$lhs, node:$rhs, SETOLT)>;
955 def setole : PatFrag<(ops node:$lhs, node:$rhs),
956 (setcc node:$lhs, node:$rhs, SETOLE)>;
957 def setone : PatFrag<(ops node:$lhs, node:$rhs),
958 (setcc node:$lhs, node:$rhs, SETONE)>;
959 def seto : PatFrag<(ops node:$lhs, node:$rhs),
960 (setcc node:$lhs, node:$rhs, SETO)>;
961 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
962 (setcc node:$lhs, node:$rhs, SETUO)>;
963 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
964 (setcc node:$lhs, node:$rhs, SETUEQ)>;
965 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
966 (setcc node:$lhs, node:$rhs, SETUGT)>;
967 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
968 (setcc node:$lhs, node:$rhs, SETUGE)>;
969 def setult : PatFrag<(ops node:$lhs, node:$rhs),
970 (setcc node:$lhs, node:$rhs, SETULT)>;
971 def setule : PatFrag<(ops node:$lhs, node:$rhs),
972 (setcc node:$lhs, node:$rhs, SETULE)>;
973 def setune : PatFrag<(ops node:$lhs, node:$rhs),
974 (setcc node:$lhs, node:$rhs, SETUNE)>;
975 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
976 (setcc node:$lhs, node:$rhs, SETEQ)>;
977 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
978 (setcc node:$lhs, node:$rhs, SETGT)>;
979 def setge : PatFrag<(ops node:$lhs, node:$rhs),
980 (setcc node:$lhs, node:$rhs, SETGE)>;
981 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
982 (setcc node:$lhs, node:$rhs, SETLT)>;
983 def setle : PatFrag<(ops node:$lhs, node:$rhs),
984 (setcc node:$lhs, node:$rhs, SETLE)>;
985 def setne : PatFrag<(ops node:$lhs, node:$rhs),
986 (setcc node:$lhs, node:$rhs, SETNE)>;
988 def atomic_cmp_swap_8 :
989 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
990 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
991 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
993 def atomic_cmp_swap_16 :
994 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
995 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
996 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
998 def atomic_cmp_swap_32 :
999 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
1000 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
1001 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
1003 def atomic_cmp_swap_64 :
1004 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
1005 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
1006 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
1009 multiclass binary_atomic_op<SDNode atomic_op> {
1010 def _8 : PatFrag<(ops node:$ptr, node:$val),
1011 (atomic_op node:$ptr, node:$val), [{
1012 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
1014 def _16 : PatFrag<(ops node:$ptr, node:$val),
1015 (atomic_op node:$ptr, node:$val), [{
1016 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
1018 def _32 : PatFrag<(ops node:$ptr, node:$val),
1019 (atomic_op node:$ptr, node:$val), [{
1020 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
1022 def _64 : PatFrag<(ops node:$ptr, node:$val),
1023 (atomic_op node:$ptr, node:$val), [{
1024 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
1028 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
1029 defm atomic_swap : binary_atomic_op<atomic_swap>;
1030 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
1031 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
1032 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
1033 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
1034 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
1035 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
1036 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
1037 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
1038 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
1039 defm atomic_store : binary_atomic_op<atomic_store>;
1042 PatFrag<(ops node:$ptr),
1043 (atomic_load node:$ptr), [{
1044 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
1046 def atomic_load_16 :
1047 PatFrag<(ops node:$ptr),
1048 (atomic_load node:$ptr), [{
1049 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
1051 def atomic_load_32 :
1052 PatFrag<(ops node:$ptr),
1053 (atomic_load node:$ptr), [{
1054 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
1056 def atomic_load_64 :
1057 PatFrag<(ops node:$ptr),
1058 (atomic_load node:$ptr), [{
1059 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
1062 //===----------------------------------------------------------------------===//
1063 // Selection DAG CONVERT_RNDSAT patterns
1065 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1066 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1067 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
1070 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1071 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1072 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
1075 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1076 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1077 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
1080 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1081 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1082 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
1085 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1086 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1087 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
1090 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1091 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1092 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
1095 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1096 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1097 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
1100 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1101 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1102 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
1105 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1106 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1107 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
1110 //===----------------------------------------------------------------------===//
1111 // Selection DAG Pattern Support.
1113 // Patterns are what are actually matched against by the target-flavored
1114 // instruction selection DAG. Instructions defined by the target implicitly
1115 // define patterns in most cases, but patterns can also be explicitly added when
1116 // an operation is defined by a sequence of instructions (e.g. loading a large
1117 // immediate value on RISC targets that do not support immediates as large as
1121 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
1122 dag PatternToMatch = patternToMatch;
1123 list<dag> ResultInstrs = resultInstrs;
1124 list<Predicate> Predicates = []; // See class Instruction in Target.td.
1125 int AddedComplexity = 0; // See class Instruction in Target.td.
1128 // Pat - A simple (but common) form of a pattern, which produces a simple result
1129 // not needing a full list.
1130 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
1132 //===----------------------------------------------------------------------===//
1133 // Complex pattern definitions.
1136 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
1137 // in C++. NumOperands is the number of operands returned by the select function;
1138 // SelectFunc is the name of the function used to pattern match the max. pattern;
1139 // RootNodes are the list of possible root nodes of the sub-dags to match.
1140 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
1142 class ComplexPattern<ValueType ty, int numops, string fn,
1143 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
1145 int NumOperands = numops;
1146 string SelectFunc = fn;
1147 list<SDNode> RootNodes = roots;
1148 list<SDNodeProperty> Properties = props;