1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand is has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand is has floating point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisSameAs - The two specified operands have identical types.
40 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
41 int OtherOperandNum = OtherOp;
44 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
45 // smaller than the 'Other' operand.
46 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
47 int OtherOperandNum = OtherOp;
50 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
51 int BigOperandNum = BigOp;
54 /// SDTCisIntVectorOfSameSize - This indicates that ThisOp and OtherOp are
55 /// vector types, and that ThisOp is the result of
56 /// MVT::getIntVectorWithNumElements with the number of elements
58 class SDTCisIntVectorOfSameSize<int ThisOp, int OtherOp>
59 : SDTypeConstraint<ThisOp> {
60 int OtherOpNum = OtherOp;
63 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
64 /// type as the element type of OtherOp, which is a vector type.
65 class SDTCisEltOfVec<int ThisOp, int OtherOp>
66 : SDTypeConstraint<ThisOp> {
67 int OtherOpNum = OtherOp;
70 //===----------------------------------------------------------------------===//
71 // Selection DAG Type Profile definitions.
73 // These use the constraints defined above to describe the type requirements of
74 // the various nodes. These are not hard coded into tblgen, allowing targets to
75 // add their own if needed.
78 // SDTypeProfile - This profile describes the type requirements of a Selection
80 class SDTypeProfile<int numresults, int numoperands,
81 list<SDTypeConstraint> constraints> {
82 int NumResults = numresults;
83 int NumOperands = numoperands;
84 list<SDTypeConstraint> Constraints = constraints;
88 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
89 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
90 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
91 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
92 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
93 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
95 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
98 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
99 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
101 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
104 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
105 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
107 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
108 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
110 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
111 SDTCisSameAs<0, 1>, SDTCisInt<0>
113 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
114 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
116 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
117 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
119 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
120 SDTCisSameAs<0, 1>, SDTCisFP<0>
122 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
123 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
125 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
126 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
128 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
129 SDTCisFP<0>, SDTCisInt<1>
131 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
132 SDTCisInt<0>, SDTCisFP<1>
134 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
135 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
136 SDTCisVTSmallerThanOp<2, 1>
139 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
140 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
143 def SDTSelect : SDTypeProfile<1, 3, [ // select
144 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
147 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
148 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
152 def SDTBr : SDTypeProfile<0, 1, [ // br
156 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
157 SDTCisInt<0>, SDTCisVT<1, OtherVT>
160 def SDTBrind : SDTypeProfile<0, 1, [ // brind
164 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
166 def SDTLoad : SDTypeProfile<1, 1, [ // load
170 def SDTStore : SDTypeProfile<0, 2, [ // store
174 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
175 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
178 def SDTVecShuffle : SDTypeProfile<1, 3, [
179 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisIntVectorOfSameSize<3, 0>
181 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
182 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
184 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
185 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
188 def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch
189 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
192 def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier
193 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
196 def STDAtomic3 : SDTypeProfile<1, 3, [
197 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
199 def STDAtomic2 : SDTypeProfile<1, 2, [
200 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
203 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
204 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
207 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
208 SDTypeProfile<0, 1, constraints>;
209 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
210 SDTypeProfile<0, 2, constraints>;
212 //===----------------------------------------------------------------------===//
213 // Selection DAG Node Properties.
215 // Note: These are hard coded into tblgen.
217 class SDNodeProperty;
218 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
219 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
220 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
221 def SDNPOutFlag : SDNodeProperty; // Write a flag result
222 def SDNPInFlag : SDNodeProperty; // Read a flag operand
223 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
224 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
225 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
226 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
227 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
229 //===----------------------------------------------------------------------===//
230 // Selection DAG Node definitions.
232 class SDNode<string opcode, SDTypeProfile typeprof,
233 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
234 string Opcode = opcode;
235 string SDClass = sdclass;
236 list<SDNodeProperty> Properties = props;
237 SDTypeProfile TypeProfile = typeprof;
246 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
247 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
248 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
249 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
250 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
251 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
252 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
253 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
254 "GlobalAddressSDNode">;
255 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
256 "GlobalAddressSDNode">;
257 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
258 "GlobalAddressSDNode">;
259 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
260 "GlobalAddressSDNode">;
261 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
262 "ConstantPoolSDNode">;
263 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
264 "ConstantPoolSDNode">;
265 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
267 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
269 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
271 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
273 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
274 "ExternalSymbolSDNode">;
275 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
276 "ExternalSymbolSDNode">;
278 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
279 [SDNPCommutative, SDNPAssociative]>;
280 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
281 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
282 [SDNPCommutative, SDNPAssociative]>;
283 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
284 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
285 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
286 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
287 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
288 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
289 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
290 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
291 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
292 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
293 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
294 def and : SDNode<"ISD::AND" , SDTIntBinOp,
295 [SDNPCommutative, SDNPAssociative]>;
296 def or : SDNode<"ISD::OR" , SDTIntBinOp,
297 [SDNPCommutative, SDNPAssociative]>;
298 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
299 [SDNPCommutative, SDNPAssociative]>;
300 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
301 [SDNPCommutative, SDNPOutFlag]>;
302 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
303 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
304 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
306 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
307 [SDNPOutFlag, SDNPInFlag]>;
309 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
310 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
311 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
312 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
313 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
314 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
315 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
316 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
317 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
318 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
319 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
320 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
323 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
324 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
325 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
326 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
327 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
328 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
329 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
330 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
331 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
332 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
333 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
334 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
335 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
336 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
337 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
339 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
340 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
341 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
343 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
344 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
345 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
346 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
348 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
349 def select : SDNode<"ISD::SELECT" , SDTSelect>;
350 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
351 def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
353 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
354 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
355 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
356 def ret : SDNode<"ISD::RET" , SDTNone, [SDNPHasChain]>;
357 def trap : SDNode<"ISD::TRAP" , SDTNone,
358 [SDNPHasChain, SDNPSideEffect]>;
360 def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch,
361 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
363 def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
364 [SDNPHasChain, SDNPSideEffect]>;
366 def atomic_cmp_swap_8 : SDNode<"ISD::ATOMIC_CMP_SWAP_8" , STDAtomic3,
367 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
368 def atomic_load_add_8 : SDNode<"ISD::ATOMIC_LOAD_ADD_8" , STDAtomic2,
369 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
370 def atomic_swap_8 : SDNode<"ISD::ATOMIC_SWAP_8", STDAtomic2,
371 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
372 def atomic_load_sub_8 : SDNode<"ISD::ATOMIC_LOAD_SUB_8" , STDAtomic2,
373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
374 def atomic_load_and_8 : SDNode<"ISD::ATOMIC_LOAD_AND_8" , STDAtomic2,
375 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
376 def atomic_load_or_8 : SDNode<"ISD::ATOMIC_LOAD_OR_8" , STDAtomic2,
377 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
378 def atomic_load_xor_8 : SDNode<"ISD::ATOMIC_LOAD_XOR_8" , STDAtomic2,
379 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
380 def atomic_load_nand_8: SDNode<"ISD::ATOMIC_LOAD_NAND_8", STDAtomic2,
381 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
382 def atomic_load_min_8 : SDNode<"ISD::ATOMIC_LOAD_MIN_8", STDAtomic2,
383 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
384 def atomic_load_max_8 : SDNode<"ISD::ATOMIC_LOAD_MAX_8", STDAtomic2,
385 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
386 def atomic_load_umin_8 : SDNode<"ISD::ATOMIC_LOAD_UMIN_8", STDAtomic2,
387 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
388 def atomic_load_umax_8 : SDNode<"ISD::ATOMIC_LOAD_UMAX_8", STDAtomic2,
389 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
390 def atomic_cmp_swap_16 : SDNode<"ISD::ATOMIC_CMP_SWAP_16" , STDAtomic3,
391 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
392 def atomic_load_add_16 : SDNode<"ISD::ATOMIC_LOAD_ADD_16" , STDAtomic2,
393 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
394 def atomic_swap_16 : SDNode<"ISD::ATOMIC_SWAP_16", STDAtomic2,
395 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
396 def atomic_load_sub_16 : SDNode<"ISD::ATOMIC_LOAD_SUB_16" , STDAtomic2,
397 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
398 def atomic_load_and_16 : SDNode<"ISD::ATOMIC_LOAD_AND_16" , STDAtomic2,
399 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
400 def atomic_load_or_16 : SDNode<"ISD::ATOMIC_LOAD_OR_16" , STDAtomic2,
401 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
402 def atomic_load_xor_16 : SDNode<"ISD::ATOMIC_LOAD_XOR_16" , STDAtomic2,
403 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
404 def atomic_load_nand_16: SDNode<"ISD::ATOMIC_LOAD_NAND_16", STDAtomic2,
405 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
406 def atomic_load_min_16 : SDNode<"ISD::ATOMIC_LOAD_MIN_16", STDAtomic2,
407 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
408 def atomic_load_max_16 : SDNode<"ISD::ATOMIC_LOAD_MAX_16", STDAtomic2,
409 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
410 def atomic_load_umin_16 : SDNode<"ISD::ATOMIC_LOAD_UMIN_16", STDAtomic2,
411 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
412 def atomic_load_umax_16 : SDNode<"ISD::ATOMIC_LOAD_UMAX_16", STDAtomic2,
413 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
414 def atomic_cmp_swap_32 : SDNode<"ISD::ATOMIC_CMP_SWAP_32" , STDAtomic3,
415 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
416 def atomic_load_add_32 : SDNode<"ISD::ATOMIC_LOAD_ADD_32" , STDAtomic2,
417 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
418 def atomic_swap_32 : SDNode<"ISD::ATOMIC_SWAP_32", STDAtomic2,
419 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
420 def atomic_load_sub_32 : SDNode<"ISD::ATOMIC_LOAD_SUB_32" , STDAtomic2,
421 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
422 def atomic_load_and_32 : SDNode<"ISD::ATOMIC_LOAD_AND_32" , STDAtomic2,
423 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
424 def atomic_load_or_32 : SDNode<"ISD::ATOMIC_LOAD_OR_32" , STDAtomic2,
425 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
426 def atomic_load_xor_32 : SDNode<"ISD::ATOMIC_LOAD_XOR_32" , STDAtomic2,
427 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
428 def atomic_load_nand_32: SDNode<"ISD::ATOMIC_LOAD_NAND_32", STDAtomic2,
429 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
430 def atomic_load_min_32 : SDNode<"ISD::ATOMIC_LOAD_MIN_32", STDAtomic2,
431 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
432 def atomic_load_max_32 : SDNode<"ISD::ATOMIC_LOAD_MAX_32", STDAtomic2,
433 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
434 def atomic_load_umin_32 : SDNode<"ISD::ATOMIC_LOAD_UMIN_32", STDAtomic2,
435 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
436 def atomic_load_umax_32 : SDNode<"ISD::ATOMIC_LOAD_UMAX_32", STDAtomic2,
437 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
438 def atomic_cmp_swap_64 : SDNode<"ISD::ATOMIC_CMP_SWAP_64" , STDAtomic3,
439 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
440 def atomic_load_add_64 : SDNode<"ISD::ATOMIC_LOAD_ADD_64" , STDAtomic2,
441 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
442 def atomic_swap_64 : SDNode<"ISD::ATOMIC_SWAP_64", STDAtomic2,
443 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
444 def atomic_load_sub_64 : SDNode<"ISD::ATOMIC_LOAD_SUB_64" , STDAtomic2,
445 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
446 def atomic_load_and_64 : SDNode<"ISD::ATOMIC_LOAD_AND_64" , STDAtomic2,
447 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
448 def atomic_load_or_64 : SDNode<"ISD::ATOMIC_LOAD_OR_64" , STDAtomic2,
449 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
450 def atomic_load_xor_64 : SDNode<"ISD::ATOMIC_LOAD_XOR_64" , STDAtomic2,
451 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
452 def atomic_load_nand_64: SDNode<"ISD::ATOMIC_LOAD_NAND_64", STDAtomic2,
453 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
454 def atomic_load_min_64 : SDNode<"ISD::ATOMIC_LOAD_MIN_64", STDAtomic2,
455 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
456 def atomic_load_max_64 : SDNode<"ISD::ATOMIC_LOAD_MAX_64", STDAtomic2,
457 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
458 def atomic_load_umin_64 : SDNode<"ISD::ATOMIC_LOAD_UMIN_64", STDAtomic2,
459 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
460 def atomic_load_umax_64 : SDNode<"ISD::ATOMIC_LOAD_UMAX_64", STDAtomic2,
461 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
463 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
464 // and truncst (see below).
465 def ld : SDNode<"ISD::LOAD" , SDTLoad,
466 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
467 def st : SDNode<"ISD::STORE" , SDTStore,
468 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
469 def ist : SDNode<"ISD::STORE" , SDTIStore,
470 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
472 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
473 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
474 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
476 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
477 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
478 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
479 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
481 def extract_subreg : SDNode<"ISD::EXTRACT_SUBREG",
482 SDTypeProfile<1, 2, []>>;
483 def insert_subreg : SDNode<"ISD::INSERT_SUBREG",
484 SDTypeProfile<1, 3, []>>;
486 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
487 // these internally. Don't reference these directly.
488 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
489 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
491 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
492 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
494 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
495 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
497 // Do not use cvt directly. Use cvt forms below
498 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
500 //===----------------------------------------------------------------------===//
501 // Selection DAG Condition Codes
503 class CondCode; // ISD::CondCode enums
504 def SETOEQ : CondCode; def SETOGT : CondCode;
505 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
506 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
507 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
508 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
510 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
511 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
514 //===----------------------------------------------------------------------===//
515 // Selection DAG Node Transformation Functions.
517 // This mechanism allows targets to manipulate nodes in the output DAG once a
518 // match has been formed. This is typically used to manipulate immediate
521 class SDNodeXForm<SDNode opc, code xformFunction> {
523 code XFormFunction = xformFunction;
526 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
529 //===----------------------------------------------------------------------===//
530 // Selection DAG Pattern Fragments.
532 // Pattern fragments are reusable chunks of dags that match specific things.
533 // They can take arguments and have C++ predicates that control whether they
534 // match. They are intended to make the patterns for common instructions more
535 // compact and readable.
538 /// PatFrag - Represents a pattern fragment. This can match something on the
539 /// DAG, frame a single node to multiply nested other fragments.
541 class PatFrag<dag ops, dag frag, code pred = [{}],
542 SDNodeXForm xform = NOOP_SDNodeXForm> {
545 code Predicate = pred;
546 SDNodeXForm OperandTransform = xform;
549 // PatLeaf's are pattern fragments that have no operands. This is just a helper
550 // to define immediates and other common things concisely.
551 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
552 : PatFrag<(ops), frag, pred, xform>;
556 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
557 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
559 def immAllOnes : PatLeaf<(imm), [{ return N->isAllOnesValue(); }]>;
560 def immAllOnesV: PatLeaf<(build_vector), [{
561 return ISD::isBuildVectorAllOnes(N);
563 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
564 return ISD::isBuildVectorAllOnes(N);
566 def immAllZerosV: PatLeaf<(build_vector), [{
567 return ISD::isBuildVectorAllZeros(N);
569 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
570 return ISD::isBuildVectorAllZeros(N);
575 // Other helper fragments.
576 def not : PatFrag<(ops node:$in), (xor node:$in, immAllOnes)>;
577 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
578 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
579 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
582 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
583 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
585 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
586 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
589 // extending load fragments.
590 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
591 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
593 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
594 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
596 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
597 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
600 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
601 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
603 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
604 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
606 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
607 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
609 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
610 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
612 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
613 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
615 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
616 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
619 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
620 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
622 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
623 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
625 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
626 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
628 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
629 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
632 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
633 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
635 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
636 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
638 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
639 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
641 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
642 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
646 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
647 (st node:$val, node:$ptr), [{
648 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
650 def store : PatFrag<(ops node:$val, node:$ptr),
651 (unindexedstore node:$val, node:$ptr), [{
652 return !cast<StoreSDNode>(N)->isTruncatingStore();
655 // truncstore fragments.
656 def truncstore : PatFrag<(ops node:$val, node:$ptr),
657 (unindexedstore node:$val, node:$ptr), [{
658 return cast<StoreSDNode>(N)->isTruncatingStore();
660 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
661 (truncstore node:$val, node:$ptr), [{
662 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
664 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
665 (truncstore node:$val, node:$ptr), [{
666 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
668 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
669 (truncstore node:$val, node:$ptr), [{
670 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
672 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
673 (truncstore node:$val, node:$ptr), [{
674 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
676 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
677 (truncstore node:$val, node:$ptr), [{
678 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
681 // indexed store fragments.
682 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
683 (ist node:$val, node:$base, node:$offset), [{
684 return !cast<StoreSDNode>(N)->isTruncatingStore();
687 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
688 (istore node:$val, node:$base, node:$offset), [{
689 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
690 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
693 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
694 (ist node:$val, node:$base, node:$offset), [{
695 return cast<StoreSDNode>(N)->isTruncatingStore();
697 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
698 (itruncstore node:$val, node:$base, node:$offset), [{
699 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
700 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
702 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
703 (pre_truncst node:$val, node:$base, node:$offset), [{
704 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
706 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
707 (pre_truncst node:$val, node:$base, node:$offset), [{
708 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
710 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
711 (pre_truncst node:$val, node:$base, node:$offset), [{
712 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
714 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
715 (pre_truncst node:$val, node:$base, node:$offset), [{
716 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
718 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
719 (pre_truncst node:$val, node:$base, node:$offset), [{
720 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
723 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
724 (istore node:$val, node:$ptr, node:$offset), [{
725 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
726 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
729 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
730 (itruncstore node:$val, node:$base, node:$offset), [{
731 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
732 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
734 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
735 (post_truncst node:$val, node:$base, node:$offset), [{
736 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
738 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
739 (post_truncst node:$val, node:$base, node:$offset), [{
740 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
742 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
743 (post_truncst node:$val, node:$base, node:$offset), [{
744 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
746 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
747 (post_truncst node:$val, node:$base, node:$offset), [{
748 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
750 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
751 (post_truncst node:$val, node:$base, node:$offset), [{
752 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
755 // setcc convenience fragments.
756 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
757 (setcc node:$lhs, node:$rhs, SETOEQ)>;
758 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
759 (setcc node:$lhs, node:$rhs, SETOGT)>;
760 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
761 (setcc node:$lhs, node:$rhs, SETOGE)>;
762 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
763 (setcc node:$lhs, node:$rhs, SETOLT)>;
764 def setole : PatFrag<(ops node:$lhs, node:$rhs),
765 (setcc node:$lhs, node:$rhs, SETOLE)>;
766 def setone : PatFrag<(ops node:$lhs, node:$rhs),
767 (setcc node:$lhs, node:$rhs, SETONE)>;
768 def seto : PatFrag<(ops node:$lhs, node:$rhs),
769 (setcc node:$lhs, node:$rhs, SETO)>;
770 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
771 (setcc node:$lhs, node:$rhs, SETUO)>;
772 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
773 (setcc node:$lhs, node:$rhs, SETUEQ)>;
774 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
775 (setcc node:$lhs, node:$rhs, SETUGT)>;
776 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
777 (setcc node:$lhs, node:$rhs, SETUGE)>;
778 def setult : PatFrag<(ops node:$lhs, node:$rhs),
779 (setcc node:$lhs, node:$rhs, SETULT)>;
780 def setule : PatFrag<(ops node:$lhs, node:$rhs),
781 (setcc node:$lhs, node:$rhs, SETULE)>;
782 def setune : PatFrag<(ops node:$lhs, node:$rhs),
783 (setcc node:$lhs, node:$rhs, SETUNE)>;
784 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
785 (setcc node:$lhs, node:$rhs, SETEQ)>;
786 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
787 (setcc node:$lhs, node:$rhs, SETGT)>;
788 def setge : PatFrag<(ops node:$lhs, node:$rhs),
789 (setcc node:$lhs, node:$rhs, SETGE)>;
790 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
791 (setcc node:$lhs, node:$rhs, SETLT)>;
792 def setle : PatFrag<(ops node:$lhs, node:$rhs),
793 (setcc node:$lhs, node:$rhs, SETLE)>;
794 def setne : PatFrag<(ops node:$lhs, node:$rhs),
795 (setcc node:$lhs, node:$rhs, SETNE)>;
797 //===----------------------------------------------------------------------===//
798 // Selection DAG CONVERT_RNDSAT patterns
800 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
801 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
802 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
805 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
806 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
807 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
810 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
811 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
812 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
815 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
816 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
817 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
820 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
821 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
822 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
825 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
826 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
827 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
830 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
831 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
832 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
835 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
836 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
837 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
840 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
841 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
842 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
845 //===----------------------------------------------------------------------===//
846 // Selection DAG Pattern Support.
848 // Patterns are what are actually matched against the target-flavored
849 // instruction selection DAG. Instructions defined by the target implicitly
850 // define patterns in most cases, but patterns can also be explicitly added when
851 // an operation is defined by a sequence of instructions (e.g. loading a large
852 // immediate value on RISC targets that do not support immediates as large as
856 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
857 dag PatternToMatch = patternToMatch;
858 list<dag> ResultInstrs = resultInstrs;
859 list<Predicate> Predicates = []; // See class Instruction in Target.td.
860 int AddedComplexity = 0; // See class Instruction in Target.td.
863 // Pat - A simple (but common) form of a pattern, which produces a simple result
864 // not needing a full list.
865 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
867 //===----------------------------------------------------------------------===//
868 // Complex pattern definitions.
872 // Pass the parent Operand as root to CP function rather
873 // than the root of the sub-DAG
874 def CPAttrParentAsRoot : CPAttribute;
876 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
877 // in C++. NumOperands is the number of operands returned by the select function;
878 // SelectFunc is the name of the function used to pattern match the max. pattern;
879 // RootNodes are the list of possible root nodes of the sub-dags to match.
880 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
882 class ComplexPattern<ValueType ty, int numops, string fn,
883 list<SDNode> roots = [], list<SDNodeProperty> props = [],
884 list<CPAttribute> attrs = []> {
886 int NumOperands = numops;
887 string SelectFunc = fn;
888 list<SDNode> RootNodes = roots;
889 list<SDNodeProperty> Properties = props;
890 list<CPAttribute> Attributes = attrs;
893 //===----------------------------------------------------------------------===//
896 def SDT_dwarf_loc : SDTypeProfile<0, 3,
897 [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
898 def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;