1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand has floating-point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisVec - The specified operand has a vector type.
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
42 // SDTCisSameAs - The two specified operands have identical types.
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
44 int OtherOperandNum = OtherOp;
47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
48 // smaller than the 'Other' operand.
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
50 int OtherOperandNum = OtherOp;
53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
54 int BigOperandNum = BigOp;
57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
58 /// type as the element type of OtherOp, which is a vector type.
59 class SDTCisEltOfVec<int ThisOp, int OtherOp>
60 : SDTypeConstraint<ThisOp> {
61 int OtherOpNum = OtherOp;
64 //===----------------------------------------------------------------------===//
65 // Selection DAG Type Profile definitions.
67 // These use the constraints defined above to describe the type requirements of
68 // the various nodes. These are not hard coded into tblgen, allowing targets to
69 // add their own if needed.
72 // SDTypeProfile - This profile describes the type requirements of a Selection
74 class SDTypeProfile<int numresults, int numoperands,
75 list<SDTypeConstraint> constraints> {
76 int NumResults = numresults;
77 int NumOperands = numoperands;
78 list<SDTypeConstraint> Constraints = constraints;
82 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
83 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
84 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
85 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
86 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
87 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
89 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
90 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
92 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
93 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
95 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
99 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
100 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
102 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
103 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
105 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
106 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
108 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
109 SDTCisSameAs<0, 1>, SDTCisInt<0>
111 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
112 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
114 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
115 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
117 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
118 SDTCisSameAs<0, 1>, SDTCisFP<0>
120 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
121 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
123 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
124 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
126 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
127 SDTCisFP<0>, SDTCisInt<1>
129 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
130 SDTCisInt<0>, SDTCisFP<1>
132 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
133 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
134 SDTCisVTSmallerThanOp<2, 1>
137 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
138 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
141 def SDTSelect : SDTypeProfile<1, 3, [ // select
142 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
145 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
146 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
150 def SDTBr : SDTypeProfile<0, 1, [ // br
154 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
155 SDTCisInt<0>, SDTCisVT<1, OtherVT>
158 def SDTBrind : SDTypeProfile<0, 1, [ // brind
162 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
164 def SDTLoad : SDTypeProfile<1, 1, [ // load
168 def SDTStore : SDTypeProfile<0, 2, [ // store
172 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
173 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
176 def SDTVecShuffle : SDTypeProfile<1, 2, [
177 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
179 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
180 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
182 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
183 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
186 def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch
187 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
190 def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier
191 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
194 def STDAtomic3 : SDTypeProfile<1, 3, [
195 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
197 def STDAtomic2 : SDTypeProfile<1, 2, [
198 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
201 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
202 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
205 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
206 SDTypeProfile<0, 1, constraints>;
207 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
208 SDTypeProfile<0, 2, constraints>;
210 //===----------------------------------------------------------------------===//
211 // Selection DAG Node Properties.
213 // Note: These are hard coded into tblgen.
215 class SDNodeProperty;
216 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
217 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
218 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
219 def SDNPOutFlag : SDNodeProperty; // Write a flag result
220 def SDNPInFlag : SDNodeProperty; // Read a flag operand
221 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
222 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
223 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
224 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
225 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
226 def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
227 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match
228 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent
230 //===----------------------------------------------------------------------===//
231 // Selection DAG Pattern Operations
232 class SDPatternOperator;
234 //===----------------------------------------------------------------------===//
235 // Selection DAG Node definitions.
237 class SDNode<string opcode, SDTypeProfile typeprof,
238 list<SDNodeProperty> props = [], string sdclass = "SDNode">
239 : SDPatternOperator {
240 string Opcode = opcode;
241 string SDClass = sdclass;
242 list<SDNodeProperty> Properties = props;
243 SDTypeProfile TypeProfile = typeprof;
246 // Special TableGen-recognized dag nodes
252 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
253 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
254 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
255 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
256 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
257 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
258 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
259 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
260 "GlobalAddressSDNode">;
261 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
262 "GlobalAddressSDNode">;
263 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
264 "GlobalAddressSDNode">;
265 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
266 "GlobalAddressSDNode">;
267 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
268 "ConstantPoolSDNode">;
269 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
270 "ConstantPoolSDNode">;
271 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
273 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
275 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
277 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
279 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
280 "ExternalSymbolSDNode">;
281 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
282 "ExternalSymbolSDNode">;
283 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
284 "BlockAddressSDNode">;
285 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
286 "BlockAddressSDNode">;
288 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
289 [SDNPCommutative, SDNPAssociative]>;
290 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
291 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
292 [SDNPCommutative, SDNPAssociative]>;
293 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
294 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
295 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
296 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
297 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
298 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
299 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
300 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
301 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
302 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
303 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
304 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
305 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
306 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
307 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
308 def and : SDNode<"ISD::AND" , SDTIntBinOp,
309 [SDNPCommutative, SDNPAssociative]>;
310 def or : SDNode<"ISD::OR" , SDTIntBinOp,
311 [SDNPCommutative, SDNPAssociative]>;
312 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
313 [SDNPCommutative, SDNPAssociative]>;
314 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
315 [SDNPCommutative, SDNPOutFlag]>;
316 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
317 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
318 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
320 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
321 [SDNPOutFlag, SDNPInFlag]>;
323 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
324 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
325 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
326 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
327 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
328 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
329 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
330 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
331 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
332 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
333 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
334 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
337 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
338 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
339 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
340 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
341 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
342 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
343 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
344 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
345 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
346 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
347 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
348 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
349 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
350 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
351 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
352 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
353 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
355 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
356 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
357 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
359 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
360 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
361 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
362 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
363 def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>;
364 def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>;
366 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
367 def select : SDNode<"ISD::SELECT" , SDTSelect>;
368 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
369 def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
371 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
372 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
373 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
374 def trap : SDNode<"ISD::TRAP" , SDTNone,
375 [SDNPHasChain, SDNPSideEffect]>;
377 def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch,
378 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
380 def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
381 [SDNPHasChain, SDNPSideEffect]>;
383 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , STDAtomic3,
384 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
385 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , STDAtomic2,
386 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
387 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2,
388 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
389 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , STDAtomic2,
390 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
391 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2,
392 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
393 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2,
394 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
395 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2,
396 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
397 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", STDAtomic2,
398 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
399 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2,
400 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
401 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2,
402 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
403 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2,
404 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
405 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2,
406 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
408 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
409 // and truncst (see below).
410 def ld : SDNode<"ISD::LOAD" , SDTLoad,
411 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
412 def st : SDNode<"ISD::STORE" , SDTStore,
413 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
414 def ist : SDNode<"ISD::STORE" , SDTIStore,
415 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
417 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
418 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
419 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
421 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
422 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
423 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
424 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
426 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
427 // these internally. Don't reference these directly.
428 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
429 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
431 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
432 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
434 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
435 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
437 // Do not use cvt directly. Use cvt forms below
438 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
440 //===----------------------------------------------------------------------===//
441 // Selection DAG Condition Codes
443 class CondCode; // ISD::CondCode enums
444 def SETOEQ : CondCode; def SETOGT : CondCode;
445 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
446 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
447 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
448 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
450 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
451 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
454 //===----------------------------------------------------------------------===//
455 // Selection DAG Node Transformation Functions.
457 // This mechanism allows targets to manipulate nodes in the output DAG once a
458 // match has been formed. This is typically used to manipulate immediate
461 class SDNodeXForm<SDNode opc, code xformFunction> {
463 code XFormFunction = xformFunction;
466 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
469 //===----------------------------------------------------------------------===//
470 // Selection DAG Pattern Fragments.
472 // Pattern fragments are reusable chunks of dags that match specific things.
473 // They can take arguments and have C++ predicates that control whether they
474 // match. They are intended to make the patterns for common instructions more
475 // compact and readable.
478 /// PatFrag - Represents a pattern fragment. This can match something on the
479 /// DAG, from a single node to multiple nested other fragments.
481 class PatFrag<dag ops, dag frag, code pred = [{}],
482 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator {
485 code Predicate = pred;
486 SDNodeXForm OperandTransform = xform;
489 // PatLeaf's are pattern fragments that have no operands. This is just a helper
490 // to define immediates and other common things concisely.
491 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
492 : PatFrag<(ops), frag, pred, xform>;
496 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
497 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
499 def immAllOnesV: PatLeaf<(build_vector), [{
500 return ISD::isBuildVectorAllOnes(N);
502 def immAllZerosV: PatLeaf<(build_vector), [{
503 return ISD::isBuildVectorAllZeros(N);
508 // Other helper fragments.
509 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
510 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
511 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
514 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
515 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
517 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
518 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
521 // extending load fragments.
522 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
523 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
525 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
526 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
528 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
529 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
532 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
533 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
535 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
536 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
538 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
539 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
541 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
542 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
544 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
545 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
547 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
548 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
551 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
552 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
554 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
555 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
557 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
558 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
560 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
561 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
564 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
565 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
567 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
568 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
570 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
571 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
573 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
574 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
578 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
579 (st node:$val, node:$ptr), [{
580 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
582 def store : PatFrag<(ops node:$val, node:$ptr),
583 (unindexedstore node:$val, node:$ptr), [{
584 return !cast<StoreSDNode>(N)->isTruncatingStore();
587 // truncstore fragments.
588 def truncstore : PatFrag<(ops node:$val, node:$ptr),
589 (unindexedstore node:$val, node:$ptr), [{
590 return cast<StoreSDNode>(N)->isTruncatingStore();
592 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
593 (truncstore node:$val, node:$ptr), [{
594 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
596 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
597 (truncstore node:$val, node:$ptr), [{
598 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
600 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
601 (truncstore node:$val, node:$ptr), [{
602 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
604 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
605 (truncstore node:$val, node:$ptr), [{
606 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
608 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
609 (truncstore node:$val, node:$ptr), [{
610 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
613 // indexed store fragments.
614 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
615 (ist node:$val, node:$base, node:$offset), [{
616 return !cast<StoreSDNode>(N)->isTruncatingStore();
619 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
620 (istore node:$val, node:$base, node:$offset), [{
621 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
622 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
625 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
626 (ist node:$val, node:$base, node:$offset), [{
627 return cast<StoreSDNode>(N)->isTruncatingStore();
629 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
630 (itruncstore node:$val, node:$base, node:$offset), [{
631 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
632 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
634 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
635 (pre_truncst node:$val, node:$base, node:$offset), [{
636 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
638 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
639 (pre_truncst node:$val, node:$base, node:$offset), [{
640 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
642 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
643 (pre_truncst node:$val, node:$base, node:$offset), [{
644 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
646 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
647 (pre_truncst node:$val, node:$base, node:$offset), [{
648 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
650 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
651 (pre_truncst node:$val, node:$base, node:$offset), [{
652 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
655 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
656 (istore node:$val, node:$ptr, node:$offset), [{
657 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
658 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
661 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
662 (itruncstore node:$val, node:$base, node:$offset), [{
663 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
664 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
666 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
667 (post_truncst node:$val, node:$base, node:$offset), [{
668 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
670 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
671 (post_truncst node:$val, node:$base, node:$offset), [{
672 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
674 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
675 (post_truncst node:$val, node:$base, node:$offset), [{
676 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
678 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
679 (post_truncst node:$val, node:$base, node:$offset), [{
680 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
682 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
683 (post_truncst node:$val, node:$base, node:$offset), [{
684 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
687 // setcc convenience fragments.
688 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
689 (setcc node:$lhs, node:$rhs, SETOEQ)>;
690 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
691 (setcc node:$lhs, node:$rhs, SETOGT)>;
692 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
693 (setcc node:$lhs, node:$rhs, SETOGE)>;
694 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
695 (setcc node:$lhs, node:$rhs, SETOLT)>;
696 def setole : PatFrag<(ops node:$lhs, node:$rhs),
697 (setcc node:$lhs, node:$rhs, SETOLE)>;
698 def setone : PatFrag<(ops node:$lhs, node:$rhs),
699 (setcc node:$lhs, node:$rhs, SETONE)>;
700 def seto : PatFrag<(ops node:$lhs, node:$rhs),
701 (setcc node:$lhs, node:$rhs, SETO)>;
702 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
703 (setcc node:$lhs, node:$rhs, SETUO)>;
704 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
705 (setcc node:$lhs, node:$rhs, SETUEQ)>;
706 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
707 (setcc node:$lhs, node:$rhs, SETUGT)>;
708 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
709 (setcc node:$lhs, node:$rhs, SETUGE)>;
710 def setult : PatFrag<(ops node:$lhs, node:$rhs),
711 (setcc node:$lhs, node:$rhs, SETULT)>;
712 def setule : PatFrag<(ops node:$lhs, node:$rhs),
713 (setcc node:$lhs, node:$rhs, SETULE)>;
714 def setune : PatFrag<(ops node:$lhs, node:$rhs),
715 (setcc node:$lhs, node:$rhs, SETUNE)>;
716 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
717 (setcc node:$lhs, node:$rhs, SETEQ)>;
718 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
719 (setcc node:$lhs, node:$rhs, SETGT)>;
720 def setge : PatFrag<(ops node:$lhs, node:$rhs),
721 (setcc node:$lhs, node:$rhs, SETGE)>;
722 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
723 (setcc node:$lhs, node:$rhs, SETLT)>;
724 def setle : PatFrag<(ops node:$lhs, node:$rhs),
725 (setcc node:$lhs, node:$rhs, SETLE)>;
726 def setne : PatFrag<(ops node:$lhs, node:$rhs),
727 (setcc node:$lhs, node:$rhs, SETNE)>;
729 def atomic_cmp_swap_8 :
730 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
731 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
732 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
734 def atomic_cmp_swap_16 :
735 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
736 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
737 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
739 def atomic_cmp_swap_32 :
740 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
741 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
742 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
744 def atomic_cmp_swap_64 :
745 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
746 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
747 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
750 multiclass binary_atomic_op<SDNode atomic_op> {
751 def _8 : PatFrag<(ops node:$ptr, node:$val),
752 (atomic_op node:$ptr, node:$val), [{
753 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
755 def _16 : PatFrag<(ops node:$ptr, node:$val),
756 (atomic_op node:$ptr, node:$val), [{
757 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
759 def _32 : PatFrag<(ops node:$ptr, node:$val),
760 (atomic_op node:$ptr, node:$val), [{
761 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
763 def _64 : PatFrag<(ops node:$ptr, node:$val),
764 (atomic_op node:$ptr, node:$val), [{
765 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
769 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
770 defm atomic_swap : binary_atomic_op<atomic_swap>;
771 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
772 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
773 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
774 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
775 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
776 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
777 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
778 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
779 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
781 //===----------------------------------------------------------------------===//
782 // Selection DAG CONVERT_RNDSAT patterns
784 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
785 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
786 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
789 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
790 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
791 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
794 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
795 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
796 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
799 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
800 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
801 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
804 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
805 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
806 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
809 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
810 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
811 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
814 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
815 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
816 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
819 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
820 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
821 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
824 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
825 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
826 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
829 //===----------------------------------------------------------------------===//
830 // Selection DAG Pattern Support.
832 // Patterns are what are actually matched against by the target-flavored
833 // instruction selection DAG. Instructions defined by the target implicitly
834 // define patterns in most cases, but patterns can also be explicitly added when
835 // an operation is defined by a sequence of instructions (e.g. loading a large
836 // immediate value on RISC targets that do not support immediates as large as
840 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
841 dag PatternToMatch = patternToMatch;
842 list<dag> ResultInstrs = resultInstrs;
843 list<Predicate> Predicates = []; // See class Instruction in Target.td.
844 int AddedComplexity = 0; // See class Instruction in Target.td.
847 // Pat - A simple (but common) form of a pattern, which produces a simple result
848 // not needing a full list.
849 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
851 //===----------------------------------------------------------------------===//
852 // Complex pattern definitions.
855 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
856 // in C++. NumOperands is the number of operands returned by the select function;
857 // SelectFunc is the name of the function used to pattern match the max. pattern;
858 // RootNodes are the list of possible root nodes of the sub-dags to match.
859 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
861 class ComplexPattern<ValueType ty, int numops, string fn,
862 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
864 int NumOperands = numops;
865 string SelectFunc = fn;
866 list<SDNode> RootNodes = roots;
867 list<SDNodeProperty> Properties = props;