1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand has floating-point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisVec - The specified operand has a vector type.
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
42 // SDTCisSameAs - The two specified operands have identical types.
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
44 int OtherOperandNum = OtherOp;
47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
48 // smaller than the 'Other' operand.
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
50 int OtherOperandNum = OtherOp;
53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
54 int BigOperandNum = BigOp;
57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
58 /// type as the element type of OtherOp, which is a vector type.
59 class SDTCisEltOfVec<int ThisOp, int OtherOp>
60 : SDTypeConstraint<ThisOp> {
61 int OtherOpNum = OtherOp;
64 //===----------------------------------------------------------------------===//
65 // Selection DAG Type Profile definitions.
67 // These use the constraints defined above to describe the type requirements of
68 // the various nodes. These are not hard coded into tblgen, allowing targets to
69 // add their own if needed.
72 // SDTypeProfile - This profile describes the type requirements of a Selection
74 class SDTypeProfile<int numresults, int numoperands,
75 list<SDTypeConstraint> constraints> {
76 int NumResults = numresults;
77 int NumOperands = numoperands;
78 list<SDTypeConstraint> Constraints = constraints;
82 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
83 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
84 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
85 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
86 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
87 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
89 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
90 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
92 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
93 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
95 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
96 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
98 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
99 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
101 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
102 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
104 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
105 SDTCisSameAs<0, 1>, SDTCisInt<0>
107 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
108 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
110 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
111 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
113 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
114 SDTCisSameAs<0, 1>, SDTCisFP<0>
116 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
117 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
119 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
120 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
122 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
123 SDTCisFP<0>, SDTCisInt<1>
125 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
126 SDTCisInt<0>, SDTCisFP<1>
128 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
129 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
130 SDTCisVTSmallerThanOp<2, 1>
133 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
134 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
137 def SDTSelect : SDTypeProfile<1, 3, [ // select
138 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
141 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
142 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
146 def SDTBr : SDTypeProfile<0, 1, [ // br
150 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
151 SDTCisInt<0>, SDTCisVT<1, OtherVT>
154 def SDTBrind : SDTypeProfile<0, 1, [ // brind
158 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
160 def SDTLoad : SDTypeProfile<1, 1, [ // load
164 def SDTStore : SDTypeProfile<0, 2, [ // store
168 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
169 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
172 def SDTVecShuffle : SDTypeProfile<1, 2, [
173 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
175 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
176 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
178 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
179 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
182 def STDPrefetch : SDTypeProfile<0, 3, [ // prefetch
183 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
186 def STDMemBarrier : SDTypeProfile<0, 5, [ // memory barier
187 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
190 def STDAtomic3 : SDTypeProfile<1, 3, [
191 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
193 def STDAtomic2 : SDTypeProfile<1, 2, [
194 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
197 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
198 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
201 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
202 SDTypeProfile<0, 1, constraints>;
203 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
204 SDTypeProfile<0, 2, constraints>;
206 //===----------------------------------------------------------------------===//
207 // Selection DAG Node Properties.
209 // Note: These are hard coded into tblgen.
211 class SDNodeProperty;
212 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
213 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
214 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
215 def SDNPOutFlag : SDNodeProperty; // Write a flag result
216 def SDNPInFlag : SDNodeProperty; // Read a flag operand
217 def SDNPOptInFlag : SDNodeProperty; // Optionally read a flag operand
218 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
219 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
220 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
221 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
222 def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
224 //===----------------------------------------------------------------------===//
225 // Selection DAG Node definitions.
227 class SDNode<string opcode, SDTypeProfile typeprof,
228 list<SDNodeProperty> props = [], string sdclass = "SDNode"> {
229 string Opcode = opcode;
230 string SDClass = sdclass;
231 list<SDNodeProperty> Properties = props;
232 SDTypeProfile TypeProfile = typeprof;
235 // Special TableGen-recognized dag nodes
241 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
242 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
243 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
244 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
245 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
246 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
247 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
248 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
249 "GlobalAddressSDNode">;
250 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
251 "GlobalAddressSDNode">;
252 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
253 "GlobalAddressSDNode">;
254 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
255 "GlobalAddressSDNode">;
256 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
257 "ConstantPoolSDNode">;
258 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
259 "ConstantPoolSDNode">;
260 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
262 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
264 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
266 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
268 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
269 "ExternalSymbolSDNode">;
270 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
271 "ExternalSymbolSDNode">;
272 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
273 "BlockAddressSDNode">;
274 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
275 "BlockAddressSDNode">;
277 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
278 [SDNPCommutative, SDNPAssociative]>;
279 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
280 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
281 [SDNPCommutative, SDNPAssociative]>;
282 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
283 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
284 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
285 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
286 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
287 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
288 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
289 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
290 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
291 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
292 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
293 def and : SDNode<"ISD::AND" , SDTIntBinOp,
294 [SDNPCommutative, SDNPAssociative]>;
295 def or : SDNode<"ISD::OR" , SDTIntBinOp,
296 [SDNPCommutative, SDNPAssociative]>;
297 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
298 [SDNPCommutative, SDNPAssociative]>;
299 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
300 [SDNPCommutative, SDNPOutFlag]>;
301 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
302 [SDNPCommutative, SDNPOutFlag, SDNPInFlag]>;
303 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
305 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
306 [SDNPOutFlag, SDNPInFlag]>;
308 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
309 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
310 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
311 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
312 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
313 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
314 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
315 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
316 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
317 def bitconvert : SDNode<"ISD::BIT_CONVERT", SDTUnaryOp>;
318 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
319 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
322 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
323 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
324 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
325 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
326 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
327 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
328 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
329 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
330 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
331 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
332 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
333 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
334 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
335 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
336 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
337 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
338 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
340 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
341 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
342 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
344 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
345 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
346 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
347 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
348 def f16_to_f32 : SDNode<"ISD::FP16_TO_FP32", SDTIntToFPOp>;
349 def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>;
351 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
352 def select : SDNode<"ISD::SELECT" , SDTSelect>;
353 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
354 def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
356 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
357 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
358 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
359 def trap : SDNode<"ISD::TRAP" , SDTNone,
360 [SDNPHasChain, SDNPSideEffect]>;
362 def prefetch : SDNode<"ISD::PREFETCH" , STDPrefetch,
363 [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
365 def membarrier : SDNode<"ISD::MEMBARRIER" , STDMemBarrier,
366 [SDNPHasChain, SDNPSideEffect]>;
368 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , STDAtomic3,
369 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
370 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , STDAtomic2,
371 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
372 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", STDAtomic2,
373 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
374 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , STDAtomic2,
375 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
376 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , STDAtomic2,
377 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
378 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , STDAtomic2,
379 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
380 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , STDAtomic2,
381 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
382 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", STDAtomic2,
383 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
384 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", STDAtomic2,
385 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
386 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", STDAtomic2,
387 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
388 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", STDAtomic2,
389 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
390 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", STDAtomic2,
391 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
393 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
394 // and truncst (see below).
395 def ld : SDNode<"ISD::LOAD" , SDTLoad,
396 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
397 def st : SDNode<"ISD::STORE" , SDTStore,
398 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
399 def ist : SDNode<"ISD::STORE" , SDTIStore,
400 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
402 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
403 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
404 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
406 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
407 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
408 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
409 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
411 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
412 // these internally. Don't reference these directly.
413 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
414 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
416 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
417 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
419 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
420 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
422 // Do not use cvt directly. Use cvt forms below
423 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
425 //===----------------------------------------------------------------------===//
426 // Selection DAG Condition Codes
428 class CondCode; // ISD::CondCode enums
429 def SETOEQ : CondCode; def SETOGT : CondCode;
430 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
431 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
432 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
433 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
435 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
436 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
439 //===----------------------------------------------------------------------===//
440 // Selection DAG Node Transformation Functions.
442 // This mechanism allows targets to manipulate nodes in the output DAG once a
443 // match has been formed. This is typically used to manipulate immediate
446 class SDNodeXForm<SDNode opc, code xformFunction> {
448 code XFormFunction = xformFunction;
451 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
454 //===----------------------------------------------------------------------===//
455 // Selection DAG Pattern Fragments.
457 // Pattern fragments are reusable chunks of dags that match specific things.
458 // They can take arguments and have C++ predicates that control whether they
459 // match. They are intended to make the patterns for common instructions more
460 // compact and readable.
463 /// PatFrag - Represents a pattern fragment. This can match something on the
464 /// DAG, frame a single node to multiply nested other fragments.
466 class PatFrag<dag ops, dag frag, code pred = [{}],
467 SDNodeXForm xform = NOOP_SDNodeXForm> {
470 code Predicate = pred;
471 SDNodeXForm OperandTransform = xform;
474 // PatLeaf's are pattern fragments that have no operands. This is just a helper
475 // to define immediates and other common things concisely.
476 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
477 : PatFrag<(ops), frag, pred, xform>;
481 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
482 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
484 def immAllOnesV: PatLeaf<(build_vector), [{
485 return ISD::isBuildVectorAllOnes(N);
487 def immAllOnesV_bc: PatLeaf<(bitconvert), [{
488 return ISD::isBuildVectorAllOnes(N);
490 def immAllZerosV: PatLeaf<(build_vector), [{
491 return ISD::isBuildVectorAllZeros(N);
493 def immAllZerosV_bc: PatLeaf<(bitconvert), [{
494 return ISD::isBuildVectorAllZeros(N);
499 // Other helper fragments.
500 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
501 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
502 def vnot_conv : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV_bc)>;
503 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
506 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
507 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
509 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
510 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
513 // extending load fragments.
514 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
515 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
517 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
518 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
520 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
521 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
524 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
525 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
527 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
528 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
530 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
531 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
533 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
534 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
536 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
537 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
539 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
540 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
543 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
544 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
546 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
547 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
549 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
550 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
552 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
553 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
556 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
557 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
559 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
560 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
562 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
563 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
565 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
566 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
570 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
571 (st node:$val, node:$ptr), [{
572 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
574 def store : PatFrag<(ops node:$val, node:$ptr),
575 (unindexedstore node:$val, node:$ptr), [{
576 return !cast<StoreSDNode>(N)->isTruncatingStore();
579 // truncstore fragments.
580 def truncstore : PatFrag<(ops node:$val, node:$ptr),
581 (unindexedstore node:$val, node:$ptr), [{
582 return cast<StoreSDNode>(N)->isTruncatingStore();
584 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
585 (truncstore node:$val, node:$ptr), [{
586 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
588 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
589 (truncstore node:$val, node:$ptr), [{
590 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
592 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
593 (truncstore node:$val, node:$ptr), [{
594 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
596 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
597 (truncstore node:$val, node:$ptr), [{
598 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
600 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
601 (truncstore node:$val, node:$ptr), [{
602 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
605 // indexed store fragments.
606 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
607 (ist node:$val, node:$base, node:$offset), [{
608 return !cast<StoreSDNode>(N)->isTruncatingStore();
611 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
612 (istore node:$val, node:$base, node:$offset), [{
613 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
614 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
617 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
618 (ist node:$val, node:$base, node:$offset), [{
619 return cast<StoreSDNode>(N)->isTruncatingStore();
621 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
622 (itruncstore node:$val, node:$base, node:$offset), [{
623 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
624 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
626 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
627 (pre_truncst node:$val, node:$base, node:$offset), [{
628 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
630 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
631 (pre_truncst node:$val, node:$base, node:$offset), [{
632 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
634 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
635 (pre_truncst node:$val, node:$base, node:$offset), [{
636 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
638 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
639 (pre_truncst node:$val, node:$base, node:$offset), [{
640 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
642 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
643 (pre_truncst node:$val, node:$base, node:$offset), [{
644 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
647 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
648 (istore node:$val, node:$ptr, node:$offset), [{
649 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
650 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
653 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
654 (itruncstore node:$val, node:$base, node:$offset), [{
655 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
656 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
658 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
659 (post_truncst node:$val, node:$base, node:$offset), [{
660 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
662 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
663 (post_truncst node:$val, node:$base, node:$offset), [{
664 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
666 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
667 (post_truncst node:$val, node:$base, node:$offset), [{
668 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
670 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
671 (post_truncst node:$val, node:$base, node:$offset), [{
672 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
674 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
675 (post_truncst node:$val, node:$base, node:$offset), [{
676 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
679 // setcc convenience fragments.
680 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
681 (setcc node:$lhs, node:$rhs, SETOEQ)>;
682 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
683 (setcc node:$lhs, node:$rhs, SETOGT)>;
684 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
685 (setcc node:$lhs, node:$rhs, SETOGE)>;
686 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
687 (setcc node:$lhs, node:$rhs, SETOLT)>;
688 def setole : PatFrag<(ops node:$lhs, node:$rhs),
689 (setcc node:$lhs, node:$rhs, SETOLE)>;
690 def setone : PatFrag<(ops node:$lhs, node:$rhs),
691 (setcc node:$lhs, node:$rhs, SETONE)>;
692 def seto : PatFrag<(ops node:$lhs, node:$rhs),
693 (setcc node:$lhs, node:$rhs, SETO)>;
694 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
695 (setcc node:$lhs, node:$rhs, SETUO)>;
696 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
697 (setcc node:$lhs, node:$rhs, SETUEQ)>;
698 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
699 (setcc node:$lhs, node:$rhs, SETUGT)>;
700 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
701 (setcc node:$lhs, node:$rhs, SETUGE)>;
702 def setult : PatFrag<(ops node:$lhs, node:$rhs),
703 (setcc node:$lhs, node:$rhs, SETULT)>;
704 def setule : PatFrag<(ops node:$lhs, node:$rhs),
705 (setcc node:$lhs, node:$rhs, SETULE)>;
706 def setune : PatFrag<(ops node:$lhs, node:$rhs),
707 (setcc node:$lhs, node:$rhs, SETUNE)>;
708 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
709 (setcc node:$lhs, node:$rhs, SETEQ)>;
710 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
711 (setcc node:$lhs, node:$rhs, SETGT)>;
712 def setge : PatFrag<(ops node:$lhs, node:$rhs),
713 (setcc node:$lhs, node:$rhs, SETGE)>;
714 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
715 (setcc node:$lhs, node:$rhs, SETLT)>;
716 def setle : PatFrag<(ops node:$lhs, node:$rhs),
717 (setcc node:$lhs, node:$rhs, SETLE)>;
718 def setne : PatFrag<(ops node:$lhs, node:$rhs),
719 (setcc node:$lhs, node:$rhs, SETNE)>;
721 def atomic_cmp_swap_8 :
722 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
723 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
724 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
726 def atomic_cmp_swap_16 :
727 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
728 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
729 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
731 def atomic_cmp_swap_32 :
732 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
733 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
734 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
736 def atomic_cmp_swap_64 :
737 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
738 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
739 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
742 multiclass binary_atomic_op<SDNode atomic_op> {
743 def _8 : PatFrag<(ops node:$ptr, node:$val),
744 (atomic_op node:$ptr, node:$val), [{
745 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
747 def _16 : PatFrag<(ops node:$ptr, node:$val),
748 (atomic_op node:$ptr, node:$val), [{
749 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
751 def _32 : PatFrag<(ops node:$ptr, node:$val),
752 (atomic_op node:$ptr, node:$val), [{
753 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
755 def _64 : PatFrag<(ops node:$ptr, node:$val),
756 (atomic_op node:$ptr, node:$val), [{
757 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
761 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
762 defm atomic_swap : binary_atomic_op<atomic_swap>;
763 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
764 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
765 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
766 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
767 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
768 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
769 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
770 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
771 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
773 //===----------------------------------------------------------------------===//
774 // Selection DAG CONVERT_RNDSAT patterns
776 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
777 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
778 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
781 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
782 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
783 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
786 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
787 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
788 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
791 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
792 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
793 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
796 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
797 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
798 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
801 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
802 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
803 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
806 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
807 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
808 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
811 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
812 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
813 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
816 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
817 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
818 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
821 //===----------------------------------------------------------------------===//
822 // Selection DAG Pattern Support.
824 // Patterns are what are actually matched against the target-flavored
825 // instruction selection DAG. Instructions defined by the target implicitly
826 // define patterns in most cases, but patterns can also be explicitly added when
827 // an operation is defined by a sequence of instructions (e.g. loading a large
828 // immediate value on RISC targets that do not support immediates as large as
832 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
833 dag PatternToMatch = patternToMatch;
834 list<dag> ResultInstrs = resultInstrs;
835 list<Predicate> Predicates = []; // See class Instruction in Target.td.
836 int AddedComplexity = 0; // See class Instruction in Target.td.
839 // Pat - A simple (but common) form of a pattern, which produces a simple result
840 // not needing a full list.
841 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
843 //===----------------------------------------------------------------------===//
844 // Complex pattern definitions.
847 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
848 // in C++. NumOperands is the number of operands returned by the select function;
849 // SelectFunc is the name of the function used to pattern match the max. pattern;
850 // RootNodes are the list of possible root nodes of the sub-dags to match.
851 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
853 class ComplexPattern<ValueType ty, int numops, string fn,
854 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
856 int NumOperands = numops;
857 string SelectFunc = fn;
858 list<SDNode> RootNodes = roots;
859 list<SDNodeProperty> Properties = props;