1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the target-independent interfaces used by SelectionDAG
11 // instruction selection generators.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Selection DAG Type Constraint definitions.
18 // Note that the semantics of these constraints are hard coded into tblgen. To
19 // modify or add constraints, you have to hack tblgen.
22 class SDTypeConstraint<int opnum> {
23 int OperandNum = opnum;
26 // SDTCisVT - The specified operand has exactly this VT.
27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
33 // SDTCisInt - The specified operand has integer type.
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
36 // SDTCisFP - The specified operand has floating-point type.
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
39 // SDTCisVec - The specified operand has a vector type.
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
42 // SDTCisSameAs - The two specified operands have identical types.
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
44 int OtherOperandNum = OtherOp;
47 // SDTCisVTSmallerThanOp - The specified operand is a VT SDNode, and its type is
48 // smaller than the 'Other' operand.
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
50 int OtherOperandNum = OtherOp;
53 class SDTCisOpSmallerThanOp<int SmallOp, int BigOp> : SDTypeConstraint<SmallOp>{
54 int BigOperandNum = BigOp;
57 /// SDTCisEltOfVec - This indicates that ThisOp is a scalar type of the same
58 /// type as the element type of OtherOp, which is a vector type.
59 class SDTCisEltOfVec<int ThisOp, int OtherOp>
60 : SDTypeConstraint<ThisOp> {
61 int OtherOpNum = OtherOp;
64 /// SDTCisSubVecOfVec - This indicates that ThisOp is a vector type
65 /// with length less that of OtherOp, which is a vector type.
66 class SDTCisSubVecOfVec<int ThisOp, int OtherOp>
67 : SDTypeConstraint<ThisOp> {
68 int OtherOpNum = OtherOp;
71 // SDTCVecEltisVT - The specified operand is vector type with element type
73 class SDTCVecEltisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
77 // SDTCisSameNumEltsAs - The two specified operands have identical number
79 class SDTCisSameNumEltsAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
80 int OtherOperandNum = OtherOp;
83 //===----------------------------------------------------------------------===//
84 // Selection DAG Type Profile definitions.
86 // These use the constraints defined above to describe the type requirements of
87 // the various nodes. These are not hard coded into tblgen, allowing targets to
88 // add their own if needed.
91 // SDTypeProfile - This profile describes the type requirements of a Selection
93 class SDTypeProfile<int numresults, int numoperands,
94 list<SDTypeConstraint> constraints> {
95 int NumResults = numresults;
96 int NumOperands = numoperands;
97 list<SDTypeConstraint> Constraints = constraints;
101 def SDTIntLeaf: SDTypeProfile<1, 0, [SDTCisInt<0>]>; // for 'imm'.
102 def SDTFPLeaf : SDTypeProfile<1, 0, [SDTCisFP<0>]>; // for 'fpimm'.
103 def SDTPtrLeaf: SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; // for '&g'.
104 def SDTOther : SDTypeProfile<1, 0, [SDTCisVT<0, OtherVT>]>; // for 'vt'.
105 def SDTUNDEF : SDTypeProfile<1, 0, []>; // for 'undef'.
106 def SDTUnaryOp : SDTypeProfile<1, 1, []>; // for bitconvert.
108 def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
109 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
111 def SDTIntShiftOp : SDTypeProfile<1, 2, [ // shl, sra, srl
112 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisInt<2>
114 def SDTIntBinHiLoOp : SDTypeProfile<2, 2, [ // mulhi, mullo, sdivrem, udivrem
115 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>,SDTCisInt<0>
118 def SDTFPBinOp : SDTypeProfile<1, 2, [ // fadd, fmul, etc.
119 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisFP<0>
121 def SDTFPSignOp : SDTypeProfile<1, 2, [ // fcopysign.
122 SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisFP<2>
124 def SDTFPTernaryOp : SDTypeProfile<1, 3, [ // fmadd, fnmsub, etc.
125 SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisFP<0>
127 def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
128 SDTCisSameAs<0, 1>, SDTCisInt<0>
130 def SDTIntExtendOp : SDTypeProfile<1, 1, [ // sext, zext, anyext
131 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<1, 0>
133 def SDTIntTruncOp : SDTypeProfile<1, 1, [ // trunc
134 SDTCisInt<0>, SDTCisInt<1>, SDTCisOpSmallerThanOp<0, 1>
136 def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
137 SDTCisSameAs<0, 1>, SDTCisFP<0>
139 def SDTFPRoundOp : SDTypeProfile<1, 1, [ // fround
140 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<0, 1>
142 def SDTFPExtendOp : SDTypeProfile<1, 1, [ // fextend
143 SDTCisFP<0>, SDTCisFP<1>, SDTCisOpSmallerThanOp<1, 0>
145 def SDTIntToFPOp : SDTypeProfile<1, 1, [ // [su]int_to_fp
146 SDTCisFP<0>, SDTCisInt<1>
148 def SDTFPToIntOp : SDTypeProfile<1, 1, [ // fp_to_[su]int
149 SDTCisInt<0>, SDTCisFP<1>
151 def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
152 SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
153 SDTCisVTSmallerThanOp<2, 1>
156 def SDTSetCC : SDTypeProfile<1, 3, [ // setcc
157 SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
160 def SDTSelect : SDTypeProfile<1, 3, [ // select
161 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
164 def SDTVSelect : SDTypeProfile<1, 3, [ // vselect
165 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
168 def SDTSelectCC : SDTypeProfile<1, 5, [ // select_cc
169 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
173 def SDTBr : SDTypeProfile<0, 1, [ // br
177 def SDTBrCC : SDTypeProfile<0, 4, [ // brcc
178 SDTCisVT<0, OtherVT>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
181 def SDTBrcond : SDTypeProfile<0, 2, [ // brcond
182 SDTCisInt<0>, SDTCisVT<1, OtherVT>
185 def SDTBrind : SDTypeProfile<0, 1, [ // brind
189 def SDTNone : SDTypeProfile<0, 0, []>; // ret, trap
191 def SDTLoad : SDTypeProfile<1, 1, [ // load
195 def SDTStore : SDTypeProfile<0, 2, [ // store
199 def SDTIStore : SDTypeProfile<1, 3, [ // indexed store
200 SDTCisSameAs<0, 2>, SDTCisPtrTy<0>, SDTCisPtrTy<3>
203 def SDTMaskedStore: SDTypeProfile<0, 3, [ // masked store
204 SDTCisPtrTy<0>, SDTCisVec<1>, SDTCisVec<2>
207 def SDTMaskedLoad: SDTypeProfile<1, 3, [ // masked load
208 SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameAs<0, 3>
211 def SDTMaskedGather: SDTypeProfile<2, 3, [ // masked gather
212 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>,
213 SDTCisPtrTy<4>, SDTCVecEltisVT<1, i1>, SDTCisSameNumEltsAs<0, 1>
216 def SDTMaskedScatter: SDTypeProfile<1, 3, [ // masked scatter
217 SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameNumEltsAs<0, 1>,
218 SDTCVecEltisVT<0, i1>, SDTCisPtrTy<3>
221 def SDTVecShuffle : SDTypeProfile<1, 2, [
222 SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
224 def SDTVecExtract : SDTypeProfile<1, 2, [ // vector extract
225 SDTCisEltOfVec<0, 1>, SDTCisPtrTy<2>
227 def SDTVecInsert : SDTypeProfile<1, 3, [ // vector insert
228 SDTCisEltOfVec<2, 1>, SDTCisSameAs<0, 1>, SDTCisPtrTy<3>
231 def SDTSubVecExtract : SDTypeProfile<1, 2, [// subvector extract
232 SDTCisSubVecOfVec<0,1>, SDTCisInt<2>
234 def SDTSubVecInsert : SDTypeProfile<1, 3, [ // subvector insert
235 SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
238 def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch
239 SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1>
242 def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barrier
243 SDTCisSameAs<0,1>, SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
246 def SDTAtomicFence : SDTypeProfile<0, 2, [
247 SDTCisSameAs<0,1>, SDTCisPtrTy<0>
249 def SDTAtomic3 : SDTypeProfile<1, 3, [
250 SDTCisSameAs<0,2>, SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
252 def SDTAtomic2 : SDTypeProfile<1, 2, [
253 SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
255 def SDTAtomicStore : SDTypeProfile<0, 2, [
256 SDTCisPtrTy<0>, SDTCisInt<1>
258 def SDTAtomicLoad : SDTypeProfile<1, 1, [
259 SDTCisInt<0>, SDTCisPtrTy<1>
262 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
263 SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
266 class SDCallSeqStart<list<SDTypeConstraint> constraints> :
267 SDTypeProfile<0, 1, constraints>;
268 class SDCallSeqEnd<list<SDTypeConstraint> constraints> :
269 SDTypeProfile<0, 2, constraints>;
271 //===----------------------------------------------------------------------===//
272 // Selection DAG Node Properties.
274 // Note: These are hard coded into tblgen.
276 class SDNodeProperty;
277 def SDNPCommutative : SDNodeProperty; // X op Y == Y op X
278 def SDNPAssociative : SDNodeProperty; // (X op Y) op Z == X op (Y op Z)
279 def SDNPHasChain : SDNodeProperty; // R/W chain operand and result
280 def SDNPOutGlue : SDNodeProperty; // Write a flag result
281 def SDNPInGlue : SDNodeProperty; // Read a flag operand
282 def SDNPOptInGlue : SDNodeProperty; // Optionally read a flag operand
283 def SDNPMayStore : SDNodeProperty; // May write to memory, sets 'mayStore'.
284 def SDNPMayLoad : SDNodeProperty; // May read memory, sets 'mayLoad'.
285 def SDNPSideEffect : SDNodeProperty; // Sets 'HasUnmodelledSideEffects'.
286 def SDNPMemOperand : SDNodeProperty; // Touches memory, has assoc MemOperand
287 def SDNPVariadic : SDNodeProperty; // Node has variable arguments.
288 def SDNPWantRoot : SDNodeProperty; // ComplexPattern gets the root of match
289 def SDNPWantParent : SDNodeProperty; // ComplexPattern gets the parent
291 //===----------------------------------------------------------------------===//
292 // Selection DAG Pattern Operations
293 class SDPatternOperator;
295 //===----------------------------------------------------------------------===//
296 // Selection DAG Node definitions.
298 class SDNode<string opcode, SDTypeProfile typeprof,
299 list<SDNodeProperty> props = [], string sdclass = "SDNode">
300 : SDPatternOperator {
301 string Opcode = opcode;
302 string SDClass = sdclass;
303 list<SDNodeProperty> Properties = props;
304 SDTypeProfile TypeProfile = typeprof;
307 // Special TableGen-recognized dag nodes
313 def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
314 def timm : SDNode<"ISD::TargetConstant",SDTIntLeaf, [], "ConstantSDNode">;
315 def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
316 def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
317 def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
318 def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;
319 def undef : SDNode<"ISD::UNDEF" , SDTUNDEF , []>;
320 def globaladdr : SDNode<"ISD::GlobalAddress", SDTPtrLeaf, [],
321 "GlobalAddressSDNode">;
322 def tglobaladdr : SDNode<"ISD::TargetGlobalAddress", SDTPtrLeaf, [],
323 "GlobalAddressSDNode">;
324 def globaltlsaddr : SDNode<"ISD::GlobalTLSAddress", SDTPtrLeaf, [],
325 "GlobalAddressSDNode">;
326 def tglobaltlsaddr : SDNode<"ISD::TargetGlobalTLSAddress", SDTPtrLeaf, [],
327 "GlobalAddressSDNode">;
328 def constpool : SDNode<"ISD::ConstantPool", SDTPtrLeaf, [],
329 "ConstantPoolSDNode">;
330 def tconstpool : SDNode<"ISD::TargetConstantPool", SDTPtrLeaf, [],
331 "ConstantPoolSDNode">;
332 def jumptable : SDNode<"ISD::JumpTable", SDTPtrLeaf, [],
334 def tjumptable : SDNode<"ISD::TargetJumpTable", SDTPtrLeaf, [],
336 def frameindex : SDNode<"ISD::FrameIndex", SDTPtrLeaf, [],
338 def tframeindex : SDNode<"ISD::TargetFrameIndex", SDTPtrLeaf, [],
340 def externalsym : SDNode<"ISD::ExternalSymbol", SDTPtrLeaf, [],
341 "ExternalSymbolSDNode">;
342 def texternalsym: SDNode<"ISD::TargetExternalSymbol", SDTPtrLeaf, [],
343 "ExternalSymbolSDNode">;
344 def mcsym: SDNode<"ISD::MCSymbol", SDTPtrLeaf, [], "MCSymbolSDNode">;
345 def blockaddress : SDNode<"ISD::BlockAddress", SDTPtrLeaf, [],
346 "BlockAddressSDNode">;
347 def tblockaddress: SDNode<"ISD::TargetBlockAddress", SDTPtrLeaf, [],
348 "BlockAddressSDNode">;
350 def add : SDNode<"ISD::ADD" , SDTIntBinOp ,
351 [SDNPCommutative, SDNPAssociative]>;
352 def sub : SDNode<"ISD::SUB" , SDTIntBinOp>;
353 def mul : SDNode<"ISD::MUL" , SDTIntBinOp,
354 [SDNPCommutative, SDNPAssociative]>;
355 def mulhs : SDNode<"ISD::MULHS" , SDTIntBinOp, [SDNPCommutative]>;
356 def mulhu : SDNode<"ISD::MULHU" , SDTIntBinOp, [SDNPCommutative]>;
357 def smullohi : SDNode<"ISD::SMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
358 def umullohi : SDNode<"ISD::UMUL_LOHI" , SDTIntBinHiLoOp, [SDNPCommutative]>;
359 def sdiv : SDNode<"ISD::SDIV" , SDTIntBinOp>;
360 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
361 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
362 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
363 def sdivrem : SDNode<"ISD::SDIVREM" , SDTIntBinHiLoOp>;
364 def udivrem : SDNode<"ISD::UDIVREM" , SDTIntBinHiLoOp>;
365 def srl : SDNode<"ISD::SRL" , SDTIntShiftOp>;
366 def sra : SDNode<"ISD::SRA" , SDTIntShiftOp>;
367 def shl : SDNode<"ISD::SHL" , SDTIntShiftOp>;
368 def rotl : SDNode<"ISD::ROTL" , SDTIntShiftOp>;
369 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
370 def and : SDNode<"ISD::AND" , SDTIntBinOp,
371 [SDNPCommutative, SDNPAssociative]>;
372 def or : SDNode<"ISD::OR" , SDTIntBinOp,
373 [SDNPCommutative, SDNPAssociative]>;
374 def xor : SDNode<"ISD::XOR" , SDTIntBinOp,
375 [SDNPCommutative, SDNPAssociative]>;
376 def addc : SDNode<"ISD::ADDC" , SDTIntBinOp,
377 [SDNPCommutative, SDNPOutGlue]>;
378 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
379 [SDNPCommutative, SDNPOutGlue, SDNPInGlue]>;
380 def subc : SDNode<"ISD::SUBC" , SDTIntBinOp,
382 def sube : SDNode<"ISD::SUBE" , SDTIntBinOp,
383 [SDNPOutGlue, SDNPInGlue]>;
384 def smin : SDNode<"ISD::SMIN" , SDTIntBinOp>;
385 def smax : SDNode<"ISD::SMAX" , SDTIntBinOp>;
386 def umin : SDNode<"ISD::UMIN" , SDTIntBinOp>;
387 def umax : SDNode<"ISD::UMAX" , SDTIntBinOp>;
389 def sabsdiff : SDNode<"ISD::SABSDIFF" , SDTIntBinOp>;
390 def uabsdiff : SDNode<"ISD::UABSDIFF" , SDTIntBinOp>;
391 def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
392 def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;
393 def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
394 def cttz : SDNode<"ISD::CTTZ" , SDTIntUnaryOp>;
395 def ctpop : SDNode<"ISD::CTPOP" , SDTIntUnaryOp>;
396 def ctlz_zero_undef : SDNode<"ISD::CTLZ_ZERO_UNDEF", SDTIntUnaryOp>;
397 def cttz_zero_undef : SDNode<"ISD::CTTZ_ZERO_UNDEF", SDTIntUnaryOp>;
398 def sext : SDNode<"ISD::SIGN_EXTEND", SDTIntExtendOp>;
399 def zext : SDNode<"ISD::ZERO_EXTEND", SDTIntExtendOp>;
400 def anyext : SDNode<"ISD::ANY_EXTEND" , SDTIntExtendOp>;
401 def trunc : SDNode<"ISD::TRUNCATE" , SDTIntTruncOp>;
402 def bitconvert : SDNode<"ISD::BITCAST" , SDTUnaryOp>;
403 def addrspacecast : SDNode<"ISD::ADDRSPACECAST", SDTUnaryOp>;
404 def extractelt : SDNode<"ISD::EXTRACT_VECTOR_ELT", SDTVecExtract>;
405 def insertelt : SDNode<"ISD::INSERT_VECTOR_ELT", SDTVecInsert>;
407 def fadd : SDNode<"ISD::FADD" , SDTFPBinOp, [SDNPCommutative]>;
408 def fsub : SDNode<"ISD::FSUB" , SDTFPBinOp>;
409 def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
410 def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
411 def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
412 def fma : SDNode<"ISD::FMA" , SDTFPTernaryOp>;
413 def fmad : SDNode<"ISD::FMAD" , SDTFPTernaryOp>;
414 def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
415 def fminnum : SDNode<"ISD::FMINNUM" , SDTFPBinOp>;
416 def fmaxnum : SDNode<"ISD::FMAXNUM" , SDTFPBinOp>;
417 def fminnan : SDNode<"ISD::FMINNAN" , SDTFPBinOp>;
418 def fmaxnan : SDNode<"ISD::FMAXNAN" , SDTFPBinOp>;
419 def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>;
420 def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
421 def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
422 def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>;
423 def fcos : SDNode<"ISD::FCOS" , SDTFPUnaryOp>;
424 def fexp2 : SDNode<"ISD::FEXP2" , SDTFPUnaryOp>;
425 def fpow : SDNode<"ISD::FPOW" , SDTFPBinOp>;
426 def flog2 : SDNode<"ISD::FLOG2" , SDTFPUnaryOp>;
427 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
428 def ftrunc : SDNode<"ISD::FTRUNC" , SDTFPUnaryOp>;
429 def fceil : SDNode<"ISD::FCEIL" , SDTFPUnaryOp>;
430 def ffloor : SDNode<"ISD::FFLOOR" , SDTFPUnaryOp>;
431 def fnearbyint : SDNode<"ISD::FNEARBYINT" , SDTFPUnaryOp>;
432 def frnd : SDNode<"ISD::FROUND" , SDTFPUnaryOp>;
434 def fround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
435 def fextend : SDNode<"ISD::FP_EXTEND" , SDTFPExtendOp>;
436 def fcopysign : SDNode<"ISD::FCOPYSIGN" , SDTFPSignOp>;
438 def sint_to_fp : SDNode<"ISD::SINT_TO_FP" , SDTIntToFPOp>;
439 def uint_to_fp : SDNode<"ISD::UINT_TO_FP" , SDTIntToFPOp>;
440 def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
441 def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
442 def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>;
443 def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
445 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
446 def select : SDNode<"ISD::SELECT" , SDTSelect>;
447 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
448 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
450 def brcc : SDNode<"ISD::BR_CC" , SDTBrCC, [SDNPHasChain]>;
451 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
452 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
453 def br : SDNode<"ISD::BR" , SDTBr, [SDNPHasChain]>;
454 def trap : SDNode<"ISD::TRAP" , SDTNone,
455 [SDNPHasChain, SDNPSideEffect]>;
456 def debugtrap : SDNode<"ISD::DEBUGTRAP" , SDTNone,
457 [SDNPHasChain, SDNPSideEffect]>;
459 def prefetch : SDNode<"ISD::PREFETCH" , SDTPrefetch,
460 [SDNPHasChain, SDNPMayLoad, SDNPMayStore,
463 def readcyclecounter : SDNode<"ISD::READCYCLECOUNTER", SDTIntLeaf,
464 [SDNPHasChain, SDNPSideEffect]>;
466 def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
467 [SDNPHasChain, SDNPSideEffect]>;
469 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
470 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
471 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2,
472 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
473 def atomic_swap : SDNode<"ISD::ATOMIC_SWAP", SDTAtomic2,
474 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
475 def atomic_load_sub : SDNode<"ISD::ATOMIC_LOAD_SUB" , SDTAtomic2,
476 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
477 def atomic_load_and : SDNode<"ISD::ATOMIC_LOAD_AND" , SDTAtomic2,
478 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
479 def atomic_load_or : SDNode<"ISD::ATOMIC_LOAD_OR" , SDTAtomic2,
480 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
481 def atomic_load_xor : SDNode<"ISD::ATOMIC_LOAD_XOR" , SDTAtomic2,
482 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
483 def atomic_load_nand: SDNode<"ISD::ATOMIC_LOAD_NAND", SDTAtomic2,
484 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
485 def atomic_load_min : SDNode<"ISD::ATOMIC_LOAD_MIN", SDTAtomic2,
486 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
487 def atomic_load_max : SDNode<"ISD::ATOMIC_LOAD_MAX", SDTAtomic2,
488 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
489 def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2,
490 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
491 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
492 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
493 def atomic_load : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad,
494 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
495 def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
496 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
498 def masked_store : SDNode<"ISD::MSTORE", SDTMaskedStore,
499 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
500 def masked_load : SDNode<"ISD::MLOAD", SDTMaskedLoad,
501 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
502 def masked_scatter : SDNode<"ISD::MSCATTER", SDTMaskedScatter,
503 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
504 def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather,
505 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
507 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
508 // and truncst (see below).
509 def ld : SDNode<"ISD::LOAD" , SDTLoad,
510 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
511 def st : SDNode<"ISD::STORE" , SDTStore,
512 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
513 def ist : SDNode<"ISD::STORE" , SDTIStore,
514 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
516 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
517 def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, -1, []>, []>;
518 def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>,
520 def vector_extract : SDNode<"ISD::EXTRACT_VECTOR_ELT",
521 SDTypeProfile<1, 2, [SDTCisPtrTy<2>]>, []>;
522 def vector_insert : SDNode<"ISD::INSERT_VECTOR_ELT",
523 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisPtrTy<3>]>, []>;
524 def concat_vectors : SDNode<"ISD::CONCAT_VECTORS",
525 SDTypeProfile<1, 2, [SDTCisSubVecOfVec<1, 0>, SDTCisSameAs<1, 2>]>,[]>;
527 // This operator does not do subvector type checking. The ARM
528 // backend, at least, needs it.
529 def vector_extract_subvec : SDNode<"ISD::EXTRACT_SUBVECTOR",
530 SDTypeProfile<1, 2, [SDTCisInt<2>, SDTCisVec<1>, SDTCisVec<0>]>,
533 // This operator does subvector type checking.
534 def extract_subvector : SDNode<"ISD::EXTRACT_SUBVECTOR", SDTSubVecExtract, []>;
535 def insert_subvector : SDNode<"ISD::INSERT_SUBVECTOR", SDTSubVecInsert, []>;
537 // Nodes for intrinsics, you should use the intrinsic itself and let tblgen use
538 // these internally. Don't reference these directly.
539 def intrinsic_void : SDNode<"ISD::INTRINSIC_VOID",
540 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
542 def intrinsic_w_chain : SDNode<"ISD::INTRINSIC_W_CHAIN",
543 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>,
545 def intrinsic_wo_chain : SDNode<"ISD::INTRINSIC_WO_CHAIN",
546 SDTypeProfile<1, -1, [SDTCisPtrTy<1>]>, []>;
548 // Do not use cvt directly. Use cvt forms below
549 def cvt : SDNode<"ISD::CONVERT_RNDSAT", SDTConvertOp>;
551 def SDT_assertext : SDTypeProfile<1, 1,
552 [SDTCisInt<0>, SDTCisInt<1>, SDTCisSameAs<1, 0>]>;
553 def assertsext : SDNode<"ISD::AssertSext", SDT_assertext>;
554 def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
557 //===----------------------------------------------------------------------===//
558 // Selection DAG Condition Codes
560 class CondCode; // ISD::CondCode enums
561 def SETOEQ : CondCode; def SETOGT : CondCode;
562 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
563 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
564 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
565 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
567 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
568 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
571 //===----------------------------------------------------------------------===//
572 // Selection DAG Node Transformation Functions.
574 // This mechanism allows targets to manipulate nodes in the output DAG once a
575 // match has been formed. This is typically used to manipulate immediate
578 class SDNodeXForm<SDNode opc, code xformFunction> {
580 code XFormFunction = xformFunction;
583 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
585 //===----------------------------------------------------------------------===//
586 // PatPred Subclasses.
588 // These allow specifying different sorts of predicates that control whether a
593 class CodePatPred<code predicate> : PatPred {
594 code PredicateCode = predicate;
598 //===----------------------------------------------------------------------===//
599 // Selection DAG Pattern Fragments.
601 // Pattern fragments are reusable chunks of dags that match specific things.
602 // They can take arguments and have C++ predicates that control whether they
603 // match. They are intended to make the patterns for common instructions more
604 // compact and readable.
607 /// PatFrag - Represents a pattern fragment. This can match something on the
608 /// DAG, from a single node to multiple nested other fragments.
610 class PatFrag<dag ops, dag frag, code pred = [{}],
611 SDNodeXForm xform = NOOP_SDNodeXForm> : SDPatternOperator {
614 code PredicateCode = pred;
615 code ImmediateCode = [{}];
616 SDNodeXForm OperandTransform = xform;
619 // OutPatFrag is a pattern fragment that is used as part of an output pattern
620 // (not an input pattern). These do not have predicates or transforms, but are
621 // used to avoid repeated subexpressions in output patterns.
622 class OutPatFrag<dag ops, dag frag>
623 : PatFrag<ops, frag, [{}], NOOP_SDNodeXForm>;
625 // PatLeaf's are pattern fragments that have no operands. This is just a helper
626 // to define immediates and other common things concisely.
627 class PatLeaf<dag frag, code pred = [{}], SDNodeXForm xform = NOOP_SDNodeXForm>
628 : PatFrag<(ops), frag, pred, xform>;
631 // ImmLeaf is a pattern fragment with a constraint on the immediate. The
632 // constraint is a function that is run on the immediate (always with the value
633 // sign extended out to an int64_t) as Imm. For example:
635 // def immSExt8 : ImmLeaf<i16, [{ return (char)Imm == Imm; }]>;
637 // this is a more convenient form to match 'imm' nodes in than PatLeaf and also
638 // is preferred over using PatLeaf because it allows the code generator to
639 // reason more about the constraint.
641 // If FastIsel should ignore all instructions that have an operand of this type,
642 // the FastIselShouldIgnore flag can be set. This is an optimization to reduce
643 // the code size of the generated fast instruction selector.
644 class ImmLeaf<ValueType vt, code pred, SDNodeXForm xform = NOOP_SDNodeXForm>
645 : PatFrag<(ops), (vt imm), [{}], xform> {
646 let ImmediateCode = pred;
647 bit FastIselShouldIgnore = 0;
653 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
654 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
656 def immAllOnesV: PatLeaf<(build_vector), [{
657 return ISD::isBuildVectorAllOnes(N);
659 def immAllZerosV: PatLeaf<(build_vector), [{
660 return ISD::isBuildVectorAllZeros(N);
665 // Other helper fragments.
666 def not : PatFrag<(ops node:$in), (xor node:$in, -1)>;
667 def vnot : PatFrag<(ops node:$in), (xor node:$in, immAllOnesV)>;
668 def ineg : PatFrag<(ops node:$in), (sub 0, node:$in)>;
670 // null_frag - The null pattern operator is used in multiclass instantiations
671 // which accept an SDPatternOperator for use in matching patterns for internal
672 // definitions. When expanding a pattern, if the null fragment is referenced
673 // in the expansion, the pattern is discarded and it is as-if '[]' had been
674 // specified. This allows multiclasses to have the isel patterns be optional.
675 def null_frag : SDPatternOperator;
678 def unindexedload : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
679 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
681 def load : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
682 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
685 // extending load fragments.
686 def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
687 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
689 def sextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
690 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
692 def zextload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
693 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
696 def extloadi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
697 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
699 def extloadi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
700 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
702 def extloadi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
703 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
705 def extloadi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
706 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
708 def extloadf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
709 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f32;
711 def extloadf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
712 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::f64;
715 def sextloadi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
716 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
718 def sextloadi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
719 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
721 def sextloadi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
722 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
724 def sextloadi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
725 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
728 def zextloadi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
729 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i1;
731 def zextloadi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
732 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
734 def zextloadi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
735 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
737 def zextloadi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
738 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
741 def extloadvi1 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
742 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
744 def extloadvi8 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
745 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
747 def extloadvi16 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
748 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
750 def extloadvi32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
751 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
753 def extloadvf32 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
754 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f32;
756 def extloadvf64 : PatFrag<(ops node:$ptr), (extload node:$ptr), [{
757 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::f64;
760 def sextloadvi1 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
761 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
763 def sextloadvi8 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
764 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
766 def sextloadvi16 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
767 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
769 def sextloadvi32 : PatFrag<(ops node:$ptr), (sextload node:$ptr), [{
770 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
773 def zextloadvi1 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
774 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i1;
776 def zextloadvi8 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
777 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
779 def zextloadvi16 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
780 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
782 def zextloadvi32 : PatFrag<(ops node:$ptr), (zextload node:$ptr), [{
783 return cast<LoadSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
787 def unindexedstore : PatFrag<(ops node:$val, node:$ptr),
788 (st node:$val, node:$ptr), [{
789 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
791 def store : PatFrag<(ops node:$val, node:$ptr),
792 (unindexedstore node:$val, node:$ptr), [{
793 return !cast<StoreSDNode>(N)->isTruncatingStore();
796 // truncstore fragments.
797 def truncstore : PatFrag<(ops node:$val, node:$ptr),
798 (unindexedstore node:$val, node:$ptr), [{
799 return cast<StoreSDNode>(N)->isTruncatingStore();
801 def truncstorei8 : PatFrag<(ops node:$val, node:$ptr),
802 (truncstore node:$val, node:$ptr), [{
803 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
805 def truncstorei16 : PatFrag<(ops node:$val, node:$ptr),
806 (truncstore node:$val, node:$ptr), [{
807 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
809 def truncstorei32 : PatFrag<(ops node:$val, node:$ptr),
810 (truncstore node:$val, node:$ptr), [{
811 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
813 def truncstoref32 : PatFrag<(ops node:$val, node:$ptr),
814 (truncstore node:$val, node:$ptr), [{
815 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
817 def truncstoref64 : PatFrag<(ops node:$val, node:$ptr),
818 (truncstore node:$val, node:$ptr), [{
819 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;
822 def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr),
823 (truncstore node:$val, node:$ptr), [{
824 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;
827 def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr),
828 (truncstore node:$val, node:$ptr), [{
829 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;
832 def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr),
833 (truncstore node:$val, node:$ptr), [{
834 return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;
837 // indexed store fragments.
838 def istore : PatFrag<(ops node:$val, node:$base, node:$offset),
839 (ist node:$val, node:$base, node:$offset), [{
840 return !cast<StoreSDNode>(N)->isTruncatingStore();
843 def pre_store : PatFrag<(ops node:$val, node:$base, node:$offset),
844 (istore node:$val, node:$base, node:$offset), [{
845 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
846 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
849 def itruncstore : PatFrag<(ops node:$val, node:$base, node:$offset),
850 (ist node:$val, node:$base, node:$offset), [{
851 return cast<StoreSDNode>(N)->isTruncatingStore();
853 def pre_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
854 (itruncstore node:$val, node:$base, node:$offset), [{
855 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
856 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
858 def pre_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
859 (pre_truncst node:$val, node:$base, node:$offset), [{
860 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
862 def pre_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
863 (pre_truncst node:$val, node:$base, node:$offset), [{
864 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
866 def pre_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
867 (pre_truncst node:$val, node:$base, node:$offset), [{
868 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
870 def pre_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
871 (pre_truncst node:$val, node:$base, node:$offset), [{
872 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
874 def pre_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
875 (pre_truncst node:$val, node:$base, node:$offset), [{
876 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
879 def post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
880 (istore node:$val, node:$ptr, node:$offset), [{
881 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
882 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
885 def post_truncst : PatFrag<(ops node:$val, node:$base, node:$offset),
886 (itruncstore node:$val, node:$base, node:$offset), [{
887 ISD::MemIndexedMode AM = cast<StoreSDNode>(N)->getAddressingMode();
888 return AM == ISD::POST_INC || AM == ISD::POST_DEC;
890 def post_truncsti1 : PatFrag<(ops node:$val, node:$base, node:$offset),
891 (post_truncst node:$val, node:$base, node:$offset), [{
892 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
894 def post_truncsti8 : PatFrag<(ops node:$val, node:$base, node:$offset),
895 (post_truncst node:$val, node:$base, node:$offset), [{
896 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
898 def post_truncsti16 : PatFrag<(ops node:$val, node:$base, node:$offset),
899 (post_truncst node:$val, node:$base, node:$offset), [{
900 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
902 def post_truncsti32 : PatFrag<(ops node:$val, node:$base, node:$offset),
903 (post_truncst node:$val, node:$base, node:$offset), [{
904 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i32;
906 def post_truncstf32 : PatFrag<(ops node:$val, node:$base, node:$offset),
907 (post_truncst node:$val, node:$base, node:$offset), [{
908 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;
911 // setcc convenience fragments.
912 def setoeq : PatFrag<(ops node:$lhs, node:$rhs),
913 (setcc node:$lhs, node:$rhs, SETOEQ)>;
914 def setogt : PatFrag<(ops node:$lhs, node:$rhs),
915 (setcc node:$lhs, node:$rhs, SETOGT)>;
916 def setoge : PatFrag<(ops node:$lhs, node:$rhs),
917 (setcc node:$lhs, node:$rhs, SETOGE)>;
918 def setolt : PatFrag<(ops node:$lhs, node:$rhs),
919 (setcc node:$lhs, node:$rhs, SETOLT)>;
920 def setole : PatFrag<(ops node:$lhs, node:$rhs),
921 (setcc node:$lhs, node:$rhs, SETOLE)>;
922 def setone : PatFrag<(ops node:$lhs, node:$rhs),
923 (setcc node:$lhs, node:$rhs, SETONE)>;
924 def seto : PatFrag<(ops node:$lhs, node:$rhs),
925 (setcc node:$lhs, node:$rhs, SETO)>;
926 def setuo : PatFrag<(ops node:$lhs, node:$rhs),
927 (setcc node:$lhs, node:$rhs, SETUO)>;
928 def setueq : PatFrag<(ops node:$lhs, node:$rhs),
929 (setcc node:$lhs, node:$rhs, SETUEQ)>;
930 def setugt : PatFrag<(ops node:$lhs, node:$rhs),
931 (setcc node:$lhs, node:$rhs, SETUGT)>;
932 def setuge : PatFrag<(ops node:$lhs, node:$rhs),
933 (setcc node:$lhs, node:$rhs, SETUGE)>;
934 def setult : PatFrag<(ops node:$lhs, node:$rhs),
935 (setcc node:$lhs, node:$rhs, SETULT)>;
936 def setule : PatFrag<(ops node:$lhs, node:$rhs),
937 (setcc node:$lhs, node:$rhs, SETULE)>;
938 def setune : PatFrag<(ops node:$lhs, node:$rhs),
939 (setcc node:$lhs, node:$rhs, SETUNE)>;
940 def seteq : PatFrag<(ops node:$lhs, node:$rhs),
941 (setcc node:$lhs, node:$rhs, SETEQ)>;
942 def setgt : PatFrag<(ops node:$lhs, node:$rhs),
943 (setcc node:$lhs, node:$rhs, SETGT)>;
944 def setge : PatFrag<(ops node:$lhs, node:$rhs),
945 (setcc node:$lhs, node:$rhs, SETGE)>;
946 def setlt : PatFrag<(ops node:$lhs, node:$rhs),
947 (setcc node:$lhs, node:$rhs, SETLT)>;
948 def setle : PatFrag<(ops node:$lhs, node:$rhs),
949 (setcc node:$lhs, node:$rhs, SETLE)>;
950 def setne : PatFrag<(ops node:$lhs, node:$rhs),
951 (setcc node:$lhs, node:$rhs, SETNE)>;
953 def atomic_cmp_swap_8 :
954 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
955 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
956 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
958 def atomic_cmp_swap_16 :
959 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
960 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
961 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
963 def atomic_cmp_swap_32 :
964 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
965 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
966 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
968 def atomic_cmp_swap_64 :
969 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
970 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
971 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
974 multiclass binary_atomic_op<SDNode atomic_op> {
975 def _8 : PatFrag<(ops node:$ptr, node:$val),
976 (atomic_op node:$ptr, node:$val), [{
977 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
979 def _16 : PatFrag<(ops node:$ptr, node:$val),
980 (atomic_op node:$ptr, node:$val), [{
981 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
983 def _32 : PatFrag<(ops node:$ptr, node:$val),
984 (atomic_op node:$ptr, node:$val), [{
985 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
987 def _64 : PatFrag<(ops node:$ptr, node:$val),
988 (atomic_op node:$ptr, node:$val), [{
989 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
993 defm atomic_load_add : binary_atomic_op<atomic_load_add>;
994 defm atomic_swap : binary_atomic_op<atomic_swap>;
995 defm atomic_load_sub : binary_atomic_op<atomic_load_sub>;
996 defm atomic_load_and : binary_atomic_op<atomic_load_and>;
997 defm atomic_load_or : binary_atomic_op<atomic_load_or>;
998 defm atomic_load_xor : binary_atomic_op<atomic_load_xor>;
999 defm atomic_load_nand : binary_atomic_op<atomic_load_nand>;
1000 defm atomic_load_min : binary_atomic_op<atomic_load_min>;
1001 defm atomic_load_max : binary_atomic_op<atomic_load_max>;
1002 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
1003 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
1004 defm atomic_store : binary_atomic_op<atomic_store>;
1007 PatFrag<(ops node:$ptr),
1008 (atomic_load node:$ptr), [{
1009 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
1011 def atomic_load_16 :
1012 PatFrag<(ops node:$ptr),
1013 (atomic_load node:$ptr), [{
1014 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
1016 def atomic_load_32 :
1017 PatFrag<(ops node:$ptr),
1018 (atomic_load node:$ptr), [{
1019 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
1021 def atomic_load_64 :
1022 PatFrag<(ops node:$ptr),
1023 (atomic_load node:$ptr), [{
1024 return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
1027 //===----------------------------------------------------------------------===//
1028 // Selection DAG CONVERT_RNDSAT patterns
1030 def cvtff : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1031 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1032 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FF;
1035 def cvtss : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1036 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1037 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SS;
1040 def cvtsu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1041 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1042 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SU;
1045 def cvtus : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1046 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1047 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_US;
1050 def cvtuu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1051 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1052 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UU;
1055 def cvtsf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1056 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1057 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_SF;
1060 def cvtuf : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1061 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1062 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_UF;
1065 def cvtfs : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1066 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1067 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FS;
1070 def cvtfu : PatFrag<(ops node:$val, node:$dty, node:$sty, node:$rd, node:$sat),
1071 (cvt node:$val, node:$dty, node:$sty, node:$rd, node:$sat), [{
1072 return cast<CvtRndSatSDNode>(N)->getCvtCode() == ISD::CVT_FU;
1075 //===----------------------------------------------------------------------===//
1076 // Selection DAG Pattern Support.
1078 // Patterns are what are actually matched against by the target-flavored
1079 // instruction selection DAG. Instructions defined by the target implicitly
1080 // define patterns in most cases, but patterns can also be explicitly added when
1081 // an operation is defined by a sequence of instructions (e.g. loading a large
1082 // immediate value on RISC targets that do not support immediates as large as
1086 class Pattern<dag patternToMatch, list<dag> resultInstrs> {
1087 dag PatternToMatch = patternToMatch;
1088 list<dag> ResultInstrs = resultInstrs;
1089 list<Predicate> Predicates = []; // See class Instruction in Target.td.
1090 int AddedComplexity = 0; // See class Instruction in Target.td.
1093 // Pat - A simple (but common) form of a pattern, which produces a simple result
1094 // not needing a full list.
1095 class Pat<dag pattern, dag result> : Pattern<pattern, [result]>;
1097 //===----------------------------------------------------------------------===//
1098 // Complex pattern definitions.
1101 // Complex patterns, e.g. X86 addressing mode, requires pattern matching code
1102 // in C++. NumOperands is the number of operands returned by the select function;
1103 // SelectFunc is the name of the function used to pattern match the max. pattern;
1104 // RootNodes are the list of possible root nodes of the sub-dags to match.
1105 // e.g. X86 addressing mode - def addr : ComplexPattern<4, "SelectAddr", [add]>;
1107 class ComplexPattern<ValueType ty, int numops, string fn,
1108 list<SDNode> roots = [], list<SDNodeProperty> props = []> {
1110 int NumOperands = numops;
1111 string SelectFunc = fn;
1112 list<SDNode> RootNodes = roots;
1113 list<SDNodeProperty> Properties = props;