1 //==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the subtarget options of a Target machine.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
15 #define LLVM_TARGET_TARGETSUBTARGETINFO_H
17 #include "llvm/CodeGen/PBQPRAConstraint.h"
18 #include "llvm/MC/MCSubtargetInfo.h"
19 #include "llvm/Support/CodeGen.h"
24 class MachineFunction;
28 class TargetFrameLowering;
29 class TargetInstrInfo;
31 class TargetRegisterClass;
32 class TargetRegisterInfo;
33 class TargetSchedModel;
34 class TargetSelectionDAGInfo;
35 struct MachineSchedPolicy;
36 template <typename T> class SmallVectorImpl;
38 //===----------------------------------------------------------------------===//
40 /// TargetSubtargetInfo - Generic base class for all target subtargets. All
41 /// Target-specific options that control code generation and printing should
42 /// be exposed through a TargetSubtargetInfo-derived class.
44 class TargetSubtargetInfo : public MCSubtargetInfo {
45 TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
46 void operator=(const TargetSubtargetInfo &) = delete;
47 TargetSubtargetInfo() = delete;
49 protected: // Can only create subclasses...
50 TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
51 ArrayRef<SubtargetFeatureKV> PF,
52 ArrayRef<SubtargetFeatureKV> PD,
53 const SubtargetInfoKV *ProcSched,
54 const MCWriteProcResEntry *WPR,
55 const MCWriteLatencyEntry *WL,
56 const MCReadAdvanceEntry *RA, const InstrStage *IS,
57 const unsigned *OC, const unsigned *FP);
60 // AntiDepBreakMode - Type of anti-dependence breaking that should
61 // be performed before post-RA scheduling.
62 typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
63 typedef SmallVectorImpl<const TargetRegisterClass *> RegClassVector;
65 virtual ~TargetSubtargetInfo();
67 // Interfaces to the major aspects of target machine information:
69 // -- Instruction opcode and operand information
70 // -- Pipelines and scheduling information
71 // -- Stack frame information
72 // -- Selection DAG lowering information
74 // N.B. These objects may change during compilation. It's not safe to cache
75 // them between functions.
76 virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
77 virtual const TargetFrameLowering *getFrameLowering() const {
80 virtual const TargetLowering *getTargetLowering() const { return nullptr; }
81 virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const {
85 /// getRegisterInfo - If register information is available, return it. If
86 /// not, return null. This is kept separate from RegInfo until RegInfo has
87 /// details of graph coloring register allocation removed from it.
89 virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
91 /// getInstrItineraryData - Returns instruction itinerary data for the target
92 /// or specific subtarget.
94 virtual const InstrItineraryData *getInstrItineraryData() const {
98 /// Resolve a SchedClass at runtime, where SchedClass identifies an
99 /// MCSchedClassDesc with the isVariant property. This may return the ID of
100 /// another variant SchedClass, but repeated invocation must quickly terminate
101 /// in a nonvariant SchedClass.
102 virtual unsigned resolveSchedClass(unsigned SchedClass,
103 const MachineInstr *MI,
104 const TargetSchedModel *SchedModel) const {
108 /// \brief True if the subtarget should run MachineScheduler after aggressive
111 /// This currently replaces the SelectionDAG scheduler with the "source" order
112 /// scheduler (though see below for an option to turn this off and use the
113 /// TargetLowering preference). It does not yet disable the postRA scheduler.
114 virtual bool enableMachineScheduler() const;
116 /// \brief True if the machine scheduler should disable the TLI preference
117 /// for preRA scheduling with the source level scheduler.
118 virtual bool enableMachineSchedDefaultSched() const { return true; }
120 /// \brief True if the subtarget should enable joining global copies.
122 /// By default this is enabled if the machine scheduler is enabled, but
123 /// can be overridden.
124 virtual bool enableJoinGlobalCopies() const;
126 /// True if the subtarget should run a scheduler after register allocation.
128 /// By default this queries the PostRAScheduling bit in the scheduling model
129 /// which is the preferred way to influence this.
130 virtual bool enablePostRAScheduler() const;
132 /// \brief True if the subtarget should run the atomic expansion pass.
133 virtual bool enableAtomicExpand() const;
135 /// \brief Override generic scheduling policy within a region.
137 /// This is a convenient way for targets that don't provide any custom
138 /// scheduling heuristics (no custom MachineSchedStrategy) to make
139 /// changes to the generic scheduling policy.
140 virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
141 MachineInstr *begin, MachineInstr *end,
142 unsigned NumRegionInstrs) const {}
144 // \brief Perform target specific adjustments to the latency of a schedule
146 virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
148 // For use with PostRAScheduling: get the anti-dependence breaking that should
149 // be performed before post-RA scheduling.
150 virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }
152 // For use with PostRAScheduling: in CriticalPathRCs, return any register
153 // classes that should only be considered for anti-dependence breaking if they
154 // are on the critical path.
155 virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
156 return CriticalPathRCs.clear();
159 // For use with PostRAScheduling: get the minimum optimization level needed
160 // to enable post-RA scheduling.
161 virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
162 return CodeGenOpt::Default;
165 /// \brief True if the subtarget should run the local reassignment
166 /// heuristic of the register allocator.
167 /// This heuristic may be compile time intensive, \p OptLevel provides
168 /// a finer grain to tune the register allocator.
169 virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
171 /// \brief Enable use of alias analysis during code generation (during MI
172 /// scheduling, DAGCombine, etc.).
173 virtual bool useAA() const;
175 /// \brief Enable the use of the early if conversion pass.
176 virtual bool enableEarlyIfConversion() const { return false; }
178 /// \brief Return PBQPConstraint(s) for the target.
180 /// Override to provide custom PBQP constraints.
181 virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
185 /// Enable tracking of subregister liveness in register allocator.
186 virtual bool enableSubRegLiveness() const { return false; }
189 } // End llvm namespace