1 //===- llvm/Transforms/TargetTransformInfo.h --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass exposes codegen information to IR-level passes. Every
11 // transformation that uses codegen information is broken into three parts:
12 // 1. The IR-level analysis pass.
13 // 2. The IR-level transformation interface which provides the needed
15 // 3. Codegen-level implementation which uses target-specific hooks.
17 // This file defines #2, which is the interface that IR-level transformations
18 // use for querying the codegen.
20 //===----------------------------------------------------------------------===//
22 #ifndef LLVM_TRANSFORMS_TARGET_TRANSFORM_INTERFACE
23 #define LLVM_TRANSFORMS_TARGET_TRANSFORM_INTERFACE
25 #include "llvm/AddressingMode.h"
26 #include "llvm/IR/Intrinsics.h"
27 #include "llvm/IR/Type.h"
28 #include "llvm/Pass.h"
29 #include "llvm/Support/DataTypes.h"
33 class ScalarTargetTransformInfo;
34 class VectorTargetTransformInfo;
36 /// TargetTransformInfo - This pass provides access to the codegen
37 /// interfaces that are needed for IR-level transformations.
38 class TargetTransformInfo : public ImmutablePass {
40 const ScalarTargetTransformInfo *STTI;
41 const VectorTargetTransformInfo *VTTI;
45 /// @note This has to exist, because this is a pass, but it should never be
47 TargetTransformInfo();
49 TargetTransformInfo(const ScalarTargetTransformInfo* S,
50 const VectorTargetTransformInfo *V)
51 : ImmutablePass(ID), STTI(S), VTTI(V) {
52 initializeTargetTransformInfoPass(*PassRegistry::getPassRegistry());
55 TargetTransformInfo(const TargetTransformInfo &T) :
56 ImmutablePass(ID), STTI(T.STTI), VTTI(T.VTTI) { }
58 const ScalarTargetTransformInfo* getScalarTargetTransformInfo() const {
61 const VectorTargetTransformInfo* getVectorTargetTransformInfo() const {
65 /// Pass identification, replacement for typeid.
69 // ---------------------------------------------------------------------------//
70 // The classes below are inherited and implemented by target-specific classes
72 // ---------------------------------------------------------------------------//
74 /// ScalarTargetTransformInfo - This interface is used by IR-level passes
75 /// that need target-dependent information for generic scalar transformations.
76 /// LSR, and LowerInvoke use this interface.
77 class ScalarTargetTransformInfo {
79 /// PopcntHwSupport - Hardware support for population count. Compared to the
80 /// SW implementation, HW support is supposed to significantly boost the
81 /// performance when the population is dense, and it may or may not degrade
82 /// performance if the population is sparse. A HW support is considered as
83 /// "Fast" if it can outperform, or is on a par with, SW implementaion when
84 /// the population is sparse; otherwise, it is considered as "Slow".
85 enum PopcntHwSupport {
91 virtual ~ScalarTargetTransformInfo() {}
93 /// isLegalAddImmediate - Return true if the specified immediate is legal
94 /// add immediate, that is the target has add instructions which can add
95 /// a register with the immediate without having to materialize the
96 /// immediate into a register.
97 virtual bool isLegalAddImmediate(int64_t) const {
100 /// isLegalICmpImmediate - Return true if the specified immediate is legal
101 /// icmp immediate, that is the target has icmp instructions which can compare
102 /// a register against the immediate without having to materialize the
103 /// immediate into a register.
104 virtual bool isLegalICmpImmediate(int64_t) const {
107 /// isLegalAddressingMode - Return true if the addressing mode represented by
108 /// AM is legal for this target, for a load/store of the specified type.
109 /// The type may be VoidTy, in which case only return true if the addressing
110 /// mode is legal for a load/store of any legal type.
111 /// TODO: Handle pre/postinc as well.
112 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const {
115 /// isTruncateFree - Return true if it's free to truncate a value of
116 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
117 /// register EAX to i16 by referencing its sub-register AX.
118 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const {
121 /// Is this type legal.
122 virtual bool isTypeLegal(Type *Ty) const {
125 /// getJumpBufAlignment - returns the target's jmp_buf alignment in bytes
126 virtual unsigned getJumpBufAlignment() const {
129 /// getJumpBufSize - returns the target's jmp_buf size in bytes.
130 virtual unsigned getJumpBufSize() const {
133 /// shouldBuildLookupTables - Return true if switches should be turned into
134 /// lookup tables for the target.
135 virtual bool shouldBuildLookupTables() const {
138 /// getPopcntHwSupport - Return hardware support for population count.
139 virtual PopcntHwSupport getPopcntHwSupport(unsigned IntTyWidthInBit) const {
142 /// getIntImmCost - Return the expected cost of materializing the given
143 /// integer immediate of the specified type.
144 virtual unsigned getIntImmCost(const APInt&, Type*) const {
145 // The default assumption is that the immediate is cheap.
150 /// VectorTargetTransformInfo - This interface is used by the vectorizers
151 /// to estimate the profitability of vectorization for different instructions.
152 /// This interface provides the cost of different IR instructions. The cost
153 /// is unit-less and represents the estimated throughput of the instruction
154 /// (not the latency!) assuming that all branches are predicted, cache is hit,
156 class VectorTargetTransformInfo {
158 virtual ~VectorTargetTransformInfo() {}
161 Broadcast, // Broadcast element 0 to all other elements.
162 Reverse, // Reverse the order of the vector.
163 InsertSubvector, // InsertSubvector. Index indicates start offset.
164 ExtractSubvector // ExtractSubvector Index indicates start offset.
167 /// \return The number of scalar or vector registers that the target has.
168 /// If 'Vectors' is true, it returns the number of vector registers. If it is
169 /// set to false, it returns the number of scalar registers.
170 virtual unsigned getNumberOfRegisters(bool Vector) const {
174 /// \return The expected cost of arithmetic ops, such as mul, xor, fsub, etc.
175 virtual unsigned getArithmeticInstrCost(unsigned Opcode, Type *Ty) const {
179 /// \return The cost of a shuffle instruction of kind Kind and of type Tp.
180 /// The index and subtype parameters are used by the subvector insertion and
181 /// extraction shuffle kinds.
182 virtual unsigned getShuffleCost(ShuffleKind Kind, Type *Tp,
183 int Index = 0, Type *SubTp = 0) const {
187 /// \return The expected cost of cast instructions, such as bitcast, trunc,
189 virtual unsigned getCastInstrCost(unsigned Opcode, Type *Dst,
194 /// \return The expected cost of control-flow related instrutctions such as
196 virtual unsigned getCFInstrCost(unsigned Opcode) const {
200 /// \returns The expected cost of compare and select instructions.
201 virtual unsigned getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
202 Type *CondTy = 0) const {
206 /// \return The expected cost of vector Insert and Extract.
207 /// Use -1 to indicate that there is no information on the index value.
208 virtual unsigned getVectorInstrCost(unsigned Opcode, Type *Val,
209 unsigned Index = -1) const {
213 /// \return The cost of Load and Store instructions.
214 virtual unsigned getMemoryOpCost(unsigned Opcode, Type *Src,
216 unsigned AddressSpace) const {
220 /// \returns The cost of Intrinsic instructions.
221 virtual unsigned getIntrinsicInstrCost(Intrinsic::ID,
223 ArrayRef<Type*> Tys) const {
227 /// \returns The number of pieces into which the provided type must be
228 /// split during legalization. Zero is returned when the answer is unknown.
229 virtual unsigned getNumberOfParts(Type *Tp) const {
234 } // End llvm namespace