2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #ifndef _UAPI_I915_DRM_H_
28 #define _UAPI_I915_DRM_H_
32 /* Please note that modifications to all structs defined here are
33 * subject to backwards-compatibility constraints.
37 /* Each region is a minimum of 16k, and there are at most 255 of them.
39 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
40 * of chars for next/prev indices */
41 #define I915_LOG_MIN_TEX_REGION_SIZE 14
43 typedef struct _drm_i915_init {
46 I915_CLEANUP_DMA = 0x02,
47 I915_RESUME_DMA = 0x03
49 unsigned int mmio_offset;
50 int sarea_priv_offset;
51 unsigned int ring_start;
52 unsigned int ring_end;
53 unsigned int ring_size;
54 unsigned int front_offset;
55 unsigned int back_offset;
56 unsigned int depth_offset;
60 unsigned int pitch_bits;
61 unsigned int back_pitch;
62 unsigned int depth_pitch;
67 typedef struct _drm_i915_sarea {
68 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
69 int last_upload; /* last time texture was uploaded */
70 int last_enqueue; /* last time a buffer was enqueued */
71 int last_dispatch; /* age of the most recently dispatched buffer */
72 int ctxOwner; /* last context to upload state */
74 int pf_enabled; /* is pageflipping allowed? */
76 int pf_current_page; /* which buffer is being displayed? */
77 int perf_boxes; /* performance boxes to be displayed */
78 int width, height; /* screen size in pixels */
80 drm_handle_t front_handle;
84 drm_handle_t back_handle;
88 drm_handle_t depth_handle;
92 drm_handle_t tex_handle;
95 int log_tex_granularity;
97 int rotation; /* 0, 90, 180 or 270 */
101 int virtualX, virtualY;
103 unsigned int front_tiled;
104 unsigned int back_tiled;
105 unsigned int depth_tiled;
106 unsigned int rotated_tiled;
107 unsigned int rotated2_tiled;
118 /* fill out some space for old userspace triple buffer */
119 drm_handle_t unused_handle;
120 __u32 unused1, unused2, unused3;
122 /* buffer object handles for static buffers. May change
123 * over the lifetime of the client.
125 __u32 front_bo_handle;
126 __u32 back_bo_handle;
127 __u32 unused_bo_handle;
128 __u32 depth_bo_handle;
132 /* due to userspace building against these headers we need some compat here */
133 #define planeA_x pipeA_x
134 #define planeA_y pipeA_y
135 #define planeA_w pipeA_w
136 #define planeA_h pipeA_h
137 #define planeB_x pipeB_x
138 #define planeB_y pipeB_y
139 #define planeB_w pipeB_w
140 #define planeB_h pipeB_h
142 /* Flags for perf_boxes
144 #define I915_BOX_RING_EMPTY 0x1
145 #define I915_BOX_FLIP 0x2
146 #define I915_BOX_WAIT 0x4
147 #define I915_BOX_TEXTURE_LOAD 0x8
148 #define I915_BOX_LOST_CONTEXT 0x10
150 /* I915 specific ioctls
151 * The device specific ioctl range is 0x40 to 0x79.
153 #define DRM_I915_INIT 0x00
154 #define DRM_I915_FLUSH 0x01
155 #define DRM_I915_FLIP 0x02
156 #define DRM_I915_BATCHBUFFER 0x03
157 #define DRM_I915_IRQ_EMIT 0x04
158 #define DRM_I915_IRQ_WAIT 0x05
159 #define DRM_I915_GETPARAM 0x06
160 #define DRM_I915_SETPARAM 0x07
161 #define DRM_I915_ALLOC 0x08
162 #define DRM_I915_FREE 0x09
163 #define DRM_I915_INIT_HEAP 0x0a
164 #define DRM_I915_CMDBUFFER 0x0b
165 #define DRM_I915_DESTROY_HEAP 0x0c
166 #define DRM_I915_SET_VBLANK_PIPE 0x0d
167 #define DRM_I915_GET_VBLANK_PIPE 0x0e
168 #define DRM_I915_VBLANK_SWAP 0x0f
169 #define DRM_I915_HWS_ADDR 0x11
170 #define DRM_I915_GEM_INIT 0x13
171 #define DRM_I915_GEM_EXECBUFFER 0x14
172 #define DRM_I915_GEM_PIN 0x15
173 #define DRM_I915_GEM_UNPIN 0x16
174 #define DRM_I915_GEM_BUSY 0x17
175 #define DRM_I915_GEM_THROTTLE 0x18
176 #define DRM_I915_GEM_ENTERVT 0x19
177 #define DRM_I915_GEM_LEAVEVT 0x1a
178 #define DRM_I915_GEM_CREATE 0x1b
179 #define DRM_I915_GEM_PREAD 0x1c
180 #define DRM_I915_GEM_PWRITE 0x1d
181 #define DRM_I915_GEM_MMAP 0x1e
182 #define DRM_I915_GEM_SET_DOMAIN 0x1f
183 #define DRM_I915_GEM_SW_FINISH 0x20
184 #define DRM_I915_GEM_SET_TILING 0x21
185 #define DRM_I915_GEM_GET_TILING 0x22
186 #define DRM_I915_GEM_GET_APERTURE 0x23
187 #define DRM_I915_GEM_MMAP_GTT 0x24
188 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
189 #define DRM_I915_GEM_MADVISE 0x26
190 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
191 #define DRM_I915_OVERLAY_ATTRS 0x28
192 #define DRM_I915_GEM_EXECBUFFER2 0x29
193 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
194 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
195 #define DRM_I915_GEM_WAIT 0x2c
196 #define DRM_I915_GEM_CONTEXT_CREATE 0x2d
197 #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
198 #define DRM_I915_GEM_SET_CACHING 0x2f
199 #define DRM_I915_GEM_GET_CACHING 0x30
200 #define DRM_I915_REG_READ 0x31
202 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
203 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
204 #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
205 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
206 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
207 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
208 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
209 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
210 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
211 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
212 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
213 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
214 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
215 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
216 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
217 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
218 #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
219 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
220 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
221 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
222 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
223 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
224 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
225 #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
226 #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
227 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
228 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
229 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
230 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
231 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
232 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
233 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
234 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
235 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
236 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
237 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
238 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
239 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
240 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
241 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
242 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
243 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
244 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
245 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
246 #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
247 #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
248 #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
249 #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
251 /* Allow drivers to submit batchbuffers directly to hardware, relying
252 * on the security mechanisms provided by hardware.
254 typedef struct drm_i915_batchbuffer {
255 int start; /* agp offset */
256 int used; /* nr bytes in use */
257 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
258 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
259 int num_cliprects; /* mulitpass with multiple cliprects? */
260 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
261 } drm_i915_batchbuffer_t;
263 /* As above, but pass a pointer to userspace buffer which can be
264 * validated by the kernel prior to sending to hardware.
266 typedef struct _drm_i915_cmdbuffer {
267 char __user *buf; /* pointer to userspace command buffer */
268 int sz; /* nr bytes in buf */
269 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
270 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
271 int num_cliprects; /* mulitpass with multiple cliprects? */
272 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
273 } drm_i915_cmdbuffer_t;
275 /* Userspace can request & wait on irq's:
277 typedef struct drm_i915_irq_emit {
279 } drm_i915_irq_emit_t;
281 typedef struct drm_i915_irq_wait {
283 } drm_i915_irq_wait_t;
285 /* Ioctl to query kernel params:
287 #define I915_PARAM_IRQ_ACTIVE 1
288 #define I915_PARAM_ALLOW_BATCHBUFFER 2
289 #define I915_PARAM_LAST_DISPATCH 3
290 #define I915_PARAM_CHIPSET_ID 4
291 #define I915_PARAM_HAS_GEM 5
292 #define I915_PARAM_NUM_FENCES_AVAIL 6
293 #define I915_PARAM_HAS_OVERLAY 7
294 #define I915_PARAM_HAS_PAGEFLIPPING 8
295 #define I915_PARAM_HAS_EXECBUF2 9
296 #define I915_PARAM_HAS_BSD 10
297 #define I915_PARAM_HAS_BLT 11
298 #define I915_PARAM_HAS_RELAXED_FENCING 12
299 #define I915_PARAM_HAS_COHERENT_RINGS 13
300 #define I915_PARAM_HAS_EXEC_CONSTANTS 14
301 #define I915_PARAM_HAS_RELAXED_DELTA 15
302 #define I915_PARAM_HAS_GEN7_SOL_RESET 16
303 #define I915_PARAM_HAS_LLC 17
304 #define I915_PARAM_HAS_ALIASING_PPGTT 18
305 #define I915_PARAM_HAS_WAIT_TIMEOUT 19
306 #define I915_PARAM_HAS_SEMAPHORES 20
307 #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
308 #define I915_PARAM_RSVD_FOR_FUTURE_USE 22
309 #define I915_PARAM_HAS_SECURE_BATCHES 23
310 #define I915_PARAM_HAS_PINNED_BATCHES 24
311 #define I915_PARAM_HAS_EXEC_NO_RELOC 25
312 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
314 typedef struct drm_i915_getparam {
317 } drm_i915_getparam_t;
319 /* Ioctl to set kernel params:
321 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
322 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
323 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
324 #define I915_SETPARAM_NUM_USED_FENCES 4
326 typedef struct drm_i915_setparam {
329 } drm_i915_setparam_t;
331 /* A memory manager for regions of shared memory:
333 #define I915_MEM_REGION_AGP 1
335 typedef struct drm_i915_mem_alloc {
339 int __user *region_offset; /* offset from start of fb or agp */
340 } drm_i915_mem_alloc_t;
342 typedef struct drm_i915_mem_free {
345 } drm_i915_mem_free_t;
347 typedef struct drm_i915_mem_init_heap {
351 } drm_i915_mem_init_heap_t;
353 /* Allow memory manager to be torn down and re-initialized (eg on
356 typedef struct drm_i915_mem_destroy_heap {
358 } drm_i915_mem_destroy_heap_t;
360 /* Allow X server to configure which pipes to monitor for vblank signals
362 #define DRM_I915_VBLANK_PIPE_A 1
363 #define DRM_I915_VBLANK_PIPE_B 2
365 typedef struct drm_i915_vblank_pipe {
367 } drm_i915_vblank_pipe_t;
369 /* Schedule buffer swap at given vertical blank:
371 typedef struct drm_i915_vblank_swap {
372 drm_drawable_t drawable;
373 enum drm_vblank_seq_type seqtype;
374 unsigned int sequence;
375 } drm_i915_vblank_swap_t;
377 typedef struct drm_i915_hws_addr {
379 } drm_i915_hws_addr_t;
381 struct drm_i915_gem_init {
383 * Beginning offset in the GTT to be managed by the DRM memory
388 * Ending offset in the GTT to be managed by the DRM memory
394 struct drm_i915_gem_create {
396 * Requested size for the object.
398 * The (page-aligned) allocated size for the object will be returned.
402 * Returned handle for the object.
404 * Object handles are nonzero.
410 struct drm_i915_gem_pread {
411 /** Handle for the object being read. */
414 /** Offset into the object to read from */
416 /** Length of data to read */
419 * Pointer to write the data into.
421 * This is a fixed-size type for 32/64 compatibility.
426 struct drm_i915_gem_pwrite {
427 /** Handle for the object being written to. */
430 /** Offset into the object to write to */
432 /** Length of data to write */
435 * Pointer to read the data from.
437 * This is a fixed-size type for 32/64 compatibility.
442 struct drm_i915_gem_mmap {
443 /** Handle for the object being mapped. */
446 /** Offset in the object to map. */
449 * Length of data to map.
451 * The value will be page-aligned.
455 * Returned pointer the data was mapped at.
457 * This is a fixed-size type for 32/64 compatibility.
462 struct drm_i915_gem_mmap_gtt {
463 /** Handle for the object being mapped. */
467 * Fake offset to use for subsequent mmap call
469 * This is a fixed-size type for 32/64 compatibility.
474 struct drm_i915_gem_set_domain {
475 /** Handle for the object */
478 /** New read domains */
481 /** New write domain */
485 struct drm_i915_gem_sw_finish {
486 /** Handle for the object */
490 struct drm_i915_gem_relocation_entry {
492 * Handle of the buffer being pointed to by this relocation entry.
494 * It's appealing to make this be an index into the mm_validate_entry
495 * list to refer to the buffer, but this allows the driver to create
496 * a relocation list for state buffers and not re-write it per
497 * exec using the buffer.
502 * Value to be added to the offset of the target buffer to make up
503 * the relocation entry.
507 /** Offset in the buffer the relocation entry will be written into */
511 * Offset value of the target buffer that the relocation entry was last
514 * If the buffer has the same offset as last time, we can skip syncing
515 * and writing the relocation. This value is written back out by
516 * the execbuffer ioctl when the relocation is written.
518 __u64 presumed_offset;
521 * Target memory domains read by this operation.
526 * Target memory domains written by this operation.
528 * Note that only one domain may be written by the whole
529 * execbuffer operation, so that where there are conflicts,
530 * the application will get -EINVAL back.
536 * Intel memory domains
538 * Most of these just align with the various caches in
539 * the system and are used to flush and invalidate as
540 * objects end up cached in different domains.
543 #define I915_GEM_DOMAIN_CPU 0x00000001
544 /** Render cache, used by 2D and 3D drawing */
545 #define I915_GEM_DOMAIN_RENDER 0x00000002
546 /** Sampler cache, used by texture engine */
547 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
548 /** Command queue, used to load batch buffers */
549 #define I915_GEM_DOMAIN_COMMAND 0x00000008
550 /** Instruction cache, used by shader programs */
551 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
552 /** Vertex address cache */
553 #define I915_GEM_DOMAIN_VERTEX 0x00000020
554 /** GTT domain - aperture and scanout */
555 #define I915_GEM_DOMAIN_GTT 0x00000040
558 struct drm_i915_gem_exec_object {
560 * User's handle for a buffer to be bound into the GTT for this
565 /** Number of relocations to be performed on this buffer */
566 __u32 relocation_count;
568 * Pointer to array of struct drm_i915_gem_relocation_entry containing
569 * the relocations to be performed in this buffer.
573 /** Required alignment in graphics aperture */
577 * Returned value of the updated offset of the object, for future
578 * presumed_offset writes.
583 struct drm_i915_gem_execbuffer {
585 * List of buffers to be validated with their relocations to be
586 * performend on them.
588 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
590 * These buffers must be listed in an order such that all relocations
591 * a buffer is performing refer to buffers that have already appeared
592 * in the validate list.
597 /** Offset in the batchbuffer to start execution from. */
598 __u32 batch_start_offset;
599 /** Bytes used in batchbuffer from batch_start_offset */
604 /** This is a struct drm_clip_rect *cliprects */
608 struct drm_i915_gem_exec_object2 {
610 * User's handle for a buffer to be bound into the GTT for this
615 /** Number of relocations to be performed on this buffer */
616 __u32 relocation_count;
618 * Pointer to array of struct drm_i915_gem_relocation_entry containing
619 * the relocations to be performed in this buffer.
623 /** Required alignment in graphics aperture */
627 * Returned value of the updated offset of the object, for future
628 * presumed_offset writes.
632 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
633 #define EXEC_OBJECT_NEEDS_GTT (1<<1)
634 #define EXEC_OBJECT_WRITE (1<<2)
635 #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_WRITE<<1)
642 struct drm_i915_gem_execbuffer2 {
644 * List of gem_exec_object2 structs
649 /** Offset in the batchbuffer to start execution from. */
650 __u32 batch_start_offset;
651 /** Bytes used in batchbuffer from batch_start_offset */
656 /** This is a struct drm_clip_rect *cliprects */
658 #define I915_EXEC_RING_MASK (7<<0)
659 #define I915_EXEC_DEFAULT (0<<0)
660 #define I915_EXEC_RENDER (1<<0)
661 #define I915_EXEC_BSD (2<<0)
662 #define I915_EXEC_BLT (3<<0)
664 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
665 * Gen6+ only supports relative addressing to dynamic state (default) and
666 * absolute addressing.
668 * These flags are ignored for the BSD and BLT rings.
670 #define I915_EXEC_CONSTANTS_MASK (3<<6)
671 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
672 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
673 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
675 __u64 rsvd1; /* now used for context info */
679 /** Resets the SO write offset registers for transform feedback on gen7. */
680 #define I915_EXEC_GEN7_SOL_RESET (1<<8)
682 /** Request a privileged ("secure") batch buffer. Note only available for
683 * DRM_ROOT_ONLY | DRM_MASTER processes.
685 #define I915_EXEC_SECURE (1<<9)
687 /** Inform the kernel that the batch is and will always be pinned. This
688 * negates the requirement for a workaround to be performed to avoid
689 * an incoherent CS (such as can be found on 830/845). If this flag is
690 * not passed, the kernel will endeavour to make sure the batch is
691 * coherent with the CS before execution. If this flag is passed,
692 * userspace assumes the responsibility for ensuring the same.
694 #define I915_EXEC_IS_PINNED (1<<10)
696 /** Provide a hint to the kernel that the command stream and auxilliary
697 * state buffers already holds the correct presumed addresses and so the
698 * relocation process may be skipped if no buffers need to be moved in
699 * preparation for the execbuffer.
701 #define I915_EXEC_NO_RELOC (1<<11)
703 /** Use the reloc.handle as an index into the exec object array rather
704 * than as the per-file handle.
706 #define I915_EXEC_HANDLE_LUT (1<<12)
708 #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
710 #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
711 #define i915_execbuffer2_set_context_id(eb2, context) \
712 (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
713 #define i915_execbuffer2_get_context_id(eb2) \
714 ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
716 struct drm_i915_gem_pin {
717 /** Handle of the buffer to be pinned. */
721 /** alignment required within the aperture */
724 /** Returned GTT offset of the buffer. */
728 struct drm_i915_gem_unpin {
729 /** Handle of the buffer to be unpinned. */
734 struct drm_i915_gem_busy {
735 /** Handle of the buffer to check for busy */
738 /** Return busy status (1 if busy, 0 if idle).
739 * The high word is used to indicate on which rings the object
741 * 16:31 - busy (r or r/w) rings (16 render, 17 bsd, 18 blt, etc)
746 #define I915_CACHING_NONE 0
747 #define I915_CACHING_CACHED 1
749 struct drm_i915_gem_caching {
751 * Handle of the buffer to set/get the caching level of. */
755 * Cacheing level to apply or return value
757 * bits0-15 are for generic caching control (i.e. the above defined
758 * values). bits16-31 are reserved for platform-specific variations
759 * (e.g. l3$ caching on gen7). */
763 #define I915_TILING_NONE 0
764 #define I915_TILING_X 1
765 #define I915_TILING_Y 2
767 #define I915_BIT_6_SWIZZLE_NONE 0
768 #define I915_BIT_6_SWIZZLE_9 1
769 #define I915_BIT_6_SWIZZLE_9_10 2
770 #define I915_BIT_6_SWIZZLE_9_11 3
771 #define I915_BIT_6_SWIZZLE_9_10_11 4
772 /* Not seen by userland */
773 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
774 /* Seen by userland. */
775 #define I915_BIT_6_SWIZZLE_9_17 6
776 #define I915_BIT_6_SWIZZLE_9_10_17 7
778 struct drm_i915_gem_set_tiling {
779 /** Handle of the buffer to have its tiling state updated */
783 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
786 * This value is to be set on request, and will be updated by the
787 * kernel on successful return with the actual chosen tiling layout.
789 * The tiling mode may be demoted to I915_TILING_NONE when the system
790 * has bit 6 swizzling that can't be managed correctly by GEM.
792 * Buffer contents become undefined when changing tiling_mode.
797 * Stride in bytes for the object when in I915_TILING_X or
803 * Returned address bit 6 swizzling required for CPU access through
809 struct drm_i915_gem_get_tiling {
810 /** Handle of the buffer to get tiling state for. */
814 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
820 * Returned address bit 6 swizzling required for CPU access through
826 struct drm_i915_gem_get_aperture {
827 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
831 * Available space in the aperture used by i915_gem_execbuffer, in
834 __u64 aper_available_size;
837 struct drm_i915_get_pipe_from_crtc_id {
838 /** ID of CRTC being requested **/
841 /** pipe of requested CRTC **/
845 #define I915_MADV_WILLNEED 0
846 #define I915_MADV_DONTNEED 1
847 #define __I915_MADV_PURGED 2 /* internal state */
849 struct drm_i915_gem_madvise {
850 /** Handle of the buffer to change the backing store advice */
853 /* Advice: either the buffer will be needed again in the near future,
854 * or wont be and could be discarded under memory pressure.
858 /** Whether the backing store still exists. */
863 #define I915_OVERLAY_TYPE_MASK 0xff
864 #define I915_OVERLAY_YUV_PLANAR 0x01
865 #define I915_OVERLAY_YUV_PACKED 0x02
866 #define I915_OVERLAY_RGB 0x03
868 #define I915_OVERLAY_DEPTH_MASK 0xff00
869 #define I915_OVERLAY_RGB24 0x1000
870 #define I915_OVERLAY_RGB16 0x2000
871 #define I915_OVERLAY_RGB15 0x3000
872 #define I915_OVERLAY_YUV422 0x0100
873 #define I915_OVERLAY_YUV411 0x0200
874 #define I915_OVERLAY_YUV420 0x0300
875 #define I915_OVERLAY_YUV410 0x0400
877 #define I915_OVERLAY_SWAP_MASK 0xff0000
878 #define I915_OVERLAY_NO_SWAP 0x000000
879 #define I915_OVERLAY_UV_SWAP 0x010000
880 #define I915_OVERLAY_Y_SWAP 0x020000
881 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
883 #define I915_OVERLAY_FLAGS_MASK 0xff000000
884 #define I915_OVERLAY_ENABLE 0x01000000
886 struct drm_intel_overlay_put_image {
887 /* various flags and src format description */
889 /* source picture description */
891 /* stride values and offsets are in bytes, buffer relative */
892 __u16 stride_Y; /* stride for packed formats */
894 __u32 offset_Y; /* offset for packet formats */
900 /* to compensate the scaling factors for partially covered surfaces */
901 __u16 src_scan_width;
902 __u16 src_scan_height;
903 /* output crtc description */
912 #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
913 #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
914 struct drm_intel_overlay_attrs {
929 * Intel sprite handling
931 * Color keying works with a min/mask/max tuple. Both source and destination
932 * color keying is allowed.
935 * Sprite pixels within the min & max values, masked against the color channels
936 * specified in the mask field, will be transparent. All other pixels will
937 * be displayed on top of the primary plane. For RGB surfaces, only the min
938 * and mask fields will be used; ranged compares are not allowed.
940 * Destination keying:
941 * Primary plane pixels that match the min value, masked against the color
942 * channels specified in the mask field, will be replaced by corresponding
943 * pixels from the sprite plane.
945 * Note that source & destination keying are exclusive; only one can be
946 * active on a given plane.
949 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
950 #define I915_SET_COLORKEY_DESTINATION (1<<1)
951 #define I915_SET_COLORKEY_SOURCE (1<<2)
952 struct drm_intel_sprite_colorkey {
960 struct drm_i915_gem_wait {
961 /** Handle of BO we shall wait on */
964 /** Number of nanoseconds to wait, Returns time remaining. */
968 struct drm_i915_gem_context_create {
969 /* output: id of new context*/
974 struct drm_i915_gem_context_destroy {
979 struct drm_i915_reg_read {
981 __u64 val; /* Return value */
983 #endif /* _UAPI_I915_DRM_H_ */